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DE69631098D1 - Halbleiterstrukturen - Google Patents

Halbleiterstrukturen

Info

Publication number
DE69631098D1
DE69631098D1 DE69631098T DE69631098T DE69631098D1 DE 69631098 D1 DE69631098 D1 DE 69631098D1 DE 69631098 T DE69631098 T DE 69631098T DE 69631098 T DE69631098 T DE 69631098T DE 69631098 D1 DE69631098 D1 DE 69631098D1
Authority
DE
Germany
Prior art keywords
semiconductor structures
semiconductor
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69631098T
Other languages
English (en)
Inventor
Jeremy Allam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Europe Ltd
Original Assignee
Hitachi Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Europe Ltd filed Critical Hitachi Europe Ltd
Application granted granted Critical
Publication of DE69631098D1 publication Critical patent/DE69631098D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H01L29/864
    • H01L29/155
    • H01L29/737
    • H01L29/778
    • H01L29/868
    • H01L29/2003
DE69631098T 1995-08-03 1996-07-30 Halbleiterstrukturen Expired - Lifetime DE69631098D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95305436 1995-08-03

Publications (1)

Publication Number Publication Date
DE69631098D1 true DE69631098D1 (de) 2004-01-29

Family

ID=8221280

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631098T Expired - Lifetime DE69631098D1 (de) 1995-08-03 1996-07-30 Halbleiterstrukturen

Country Status (3)

Country Link
US (2) US6326650B1 (de)
JP (1) JPH09121061A (de)
DE (1) DE69631098D1 (de)

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US6703639B1 (en) 2002-12-17 2004-03-09 The United States Of America As Represented By The Secretary Of The Navy Nanofabrication for InAs/AlSb heterostructures
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US7045377B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7446002B2 (en) * 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US7202494B2 (en) * 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US7491587B2 (en) * 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US6878576B1 (en) * 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7045813B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7227174B2 (en) * 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US7229902B2 (en) * 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US7531829B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586165B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
AU2004300982B2 (en) * 2003-06-26 2007-10-25 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
US6897472B2 (en) * 2003-06-26 2005-05-24 Rj Mears, Llc Semiconductor device including MOSFET having band-engineered superlattice
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US7531850B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7535041B2 (en) * 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
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US7180103B2 (en) * 2004-09-24 2007-02-20 Agere Systems Inc. III-V power field effect transistors
US20060175631A1 (en) * 2005-02-04 2006-08-10 Raytheon Company Monolithic integrated circuit having enhanced breakdown voltage
US7902046B2 (en) * 2005-09-19 2011-03-08 The Board Of Trustees Of The Leland Stanford Junior University Thin buffer layers for SiGe growth on mismatched substrates
US7517702B2 (en) * 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
TW200746237A (en) * 2005-12-22 2007-12-16 Mears R J Llc Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7718996B2 (en) * 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
KR20070117238A (ko) * 2006-06-08 2007-12-12 삼성전기주식회사 반도체 발광 트랜지스터
KR100850950B1 (ko) * 2006-07-26 2008-08-08 엘지전자 주식회사 질화물계 발광 소자
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) * 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) * 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) * 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
JP5498662B2 (ja) * 2008-03-26 2014-05-21 国立大学法人 東京大学 半導体装置および半導体装置の製造方法
WO2010023273A1 (de) * 2008-08-28 2010-03-04 Forschungsverbund Berlin E.V. Schottky-drain transistor
TW201115735A (en) * 2009-10-21 2011-05-01 Univ Nat Chiao Tung Ohmic contact of III-V semiconductor device and manufacturing method
IL220675B (en) * 2012-06-28 2019-10-31 Elta Systems Ltd phototransistor
US9583590B2 (en) 2013-09-27 2017-02-28 Samsung Electronics Co., Ltd. Integrated circuit devices including FinFETs and methods of forming the same
EP3072158B1 (de) 2013-11-22 2024-11-13 Atomera Incorporated Vertikale halbleiterbauelemente mit einer übergitter-durchschlag-stoppschicht
WO2015077580A1 (en) 2013-11-22 2015-05-28 Mears Technologies, Inc. Semiconductor devices including superlattice depletion layer stack and related methods
WO2015191561A1 (en) 2014-06-09 2015-12-17 Mears Technologies, Inc. Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9590084B2 (en) * 2014-11-26 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Graded heterojunction nanowire device
US9741811B2 (en) 2014-12-15 2017-08-22 Samsung Electronics Co., Ltd. Integrated circuit devices including source/drain extension regions and methods of forming the same
US9673221B2 (en) 2015-03-03 2017-06-06 International Business Machines Corporation Semiconductor device with low band-to-band tunneling
JP2016213362A (ja) * 2015-05-12 2016-12-15 日本電信電話株式会社 アバランシェフォトダイオード
CN107810549B (zh) 2015-05-15 2021-12-17 阿托梅拉公司 具有提供晕圈注入峰值限制的超晶格层的半导体装置和相关方法
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9748430B2 (en) 2015-06-18 2017-08-29 Board Of Regents, The University Of Texas System Staircase avalanche photodiode with a staircase multiplication region composed of an AIInAsSb alloy
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
FR3053837B1 (fr) * 2016-07-08 2018-08-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Structure du type photodiode a avalanche et procede de fabrication d'une telle structure
JP7059771B2 (ja) * 2018-04-19 2022-04-26 日本電信電話株式会社 受光素子
JP7411965B2 (ja) 2019-02-20 2024-01-12 パナソニックIpマネジメント株式会社 撮像装置およびその駆動方法
CN112382690A (zh) * 2020-09-30 2021-02-19 昆明物理研究所 一种红外探测器材料的势垒层及其制备方法

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Also Published As

Publication number Publication date
US6326650B1 (en) 2001-12-04
US6436784B1 (en) 2002-08-20
JPH09121061A (ja) 1997-05-06

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