DE3584189D1 - Halbleiterspeichergeraet. - Google Patents
Halbleiterspeichergeraet.Info
- Publication number
- DE3584189D1 DE3584189D1 DE8585400865T DE3584189T DE3584189D1 DE 3584189 D1 DE3584189 D1 DE 3584189D1 DE 8585400865 T DE8585400865 T DE 8585400865T DE 3584189 T DE3584189 T DE 3584189T DE 3584189 D1 DE3584189 D1 DE 3584189D1
- Authority
- DE
- Germany
- Prior art keywords
- storage device
- semiconductor storage
- semiconductor
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H01L29/93—
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59088331A JPS60234295A (ja) | 1984-05-04 | 1984-05-04 | 半導体記憶装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3584189D1 true DE3584189D1 (de) | 1991-10-31 |
Family
ID=13939890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585400865T Expired - Fee Related DE3584189D1 (de) | 1984-05-04 | 1985-05-03 | Halbleiterspeichergeraet. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4636982A (de) |
EP (1) | EP0165106B1 (de) |
JP (1) | JPS60234295A (de) |
KR (1) | KR890004457B1 (de) |
DE (1) | DE3584189D1 (de) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61199297A (ja) * | 1985-02-28 | 1986-09-03 | Toshiba Corp | 半導体記憶装置 |
JPS62197992A (ja) * | 1986-02-25 | 1987-09-01 | Mitsubishi Electric Corp | ダイナミツクram |
JPH07111823B2 (ja) * | 1986-03-18 | 1995-11-29 | 三菱電機株式会社 | 半導体記憶装置 |
JPH06101229B2 (ja) * | 1986-09-09 | 1994-12-12 | 三菱電機株式会社 | ダイナミツク・ランダム・アクセス・メモリ |
US4789967A (en) * | 1986-09-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Random access memory device with block reset |
JPS63113298U (de) * | 1987-01-12 | 1988-07-21 | ||
JPH07107797B2 (ja) * | 1987-02-10 | 1995-11-15 | 三菱電機株式会社 | ダイナミツクランダムアクセスメモリ |
US5172335A (en) * | 1987-02-23 | 1992-12-15 | Hitachi, Ltd. | Semiconductor memory with divided bit load and data bus lines |
US4935901A (en) * | 1987-02-23 | 1990-06-19 | Hitachi, Ltd. | Semiconductor memory with divided bit load and data bus lines |
US5222047A (en) * | 1987-05-15 | 1993-06-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for driving word line in block access memory |
US5274596A (en) * | 1987-09-16 | 1993-12-28 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device having simultaneous operation of adjacent blocks |
US4975874B1 (en) * | 1988-11-01 | 1997-09-23 | Texas Instruments Inc | Metrix interconnection system with different width conductors |
US5758148A (en) * | 1989-03-10 | 1998-05-26 | Board Of Regents, The University Of Texas System | System and method for searching a data base using a content-searchable memory |
US4989180A (en) * | 1989-03-10 | 1991-01-29 | Board Of Regents, The University Of Texas System | Dynamic memory with logic-in-refresh |
US5777608A (en) * | 1989-03-10 | 1998-07-07 | Board Of Regents, The University Of Texas System | Apparatus and method for in-parallel scan-line graphics rendering using content-searchable memories |
JP2875321B2 (ja) * | 1990-01-29 | 1999-03-31 | 沖電気工業株式会社 | 半導体記憶装置 |
US5036493A (en) * | 1990-03-15 | 1991-07-30 | Digital Equipment Corporation | System and method for reducing power usage by multiple memory modules |
JP3058431B2 (ja) * | 1990-06-12 | 2000-07-04 | 株式会社東芝 | 半導体記憶装置 |
KR920005150A (ko) * | 1990-08-31 | 1992-03-28 | 김광호 | 씨모오스디램의 센스 앰프 구성방법 |
KR950004853B1 (ko) * | 1991-08-14 | 1995-05-15 | 삼성전자 주식회사 | 저전력용 블럭 선택 기능을 가지는 반도체 메모리 장치 |
JPH05144263A (ja) * | 1991-11-20 | 1993-06-11 | Fujitsu Ltd | 半導体記憶装置 |
JP3068352B2 (ja) * | 1992-12-01 | 2000-07-24 | 日本電気株式会社 | 半導体メモリ |
JP2566517B2 (ja) * | 1993-04-28 | 1996-12-25 | 三菱電機株式会社 | ダイナミック型半導体記憶装置 |
US6148034A (en) * | 1996-12-05 | 2000-11-14 | Linden Technology Limited | Apparatus and method for determining video encoding motion compensation vectors |
US6404660B1 (en) * | 1999-12-23 | 2002-06-11 | Rambus, Inc. | Semiconductor package with a controlled impedance bus and method of forming same |
US7120761B2 (en) * | 2000-12-20 | 2006-10-10 | Fujitsu Limited | Multi-port memory based on DRAM core |
US6889304B2 (en) | 2001-02-28 | 2005-05-03 | Rambus Inc. | Memory device supporting a dynamically configurable core organization |
US7500075B1 (en) | 2001-04-17 | 2009-03-03 | Rambus Inc. | Mechanism for enabling full data bus utilization without increasing data granularity |
US6825841B2 (en) * | 2001-09-07 | 2004-11-30 | Rambus Inc. | Granularity memory column access |
US6903956B2 (en) * | 2002-09-27 | 2005-06-07 | Oki Electric Industry Co., Ltd. | Semiconductor memory device |
US8190808B2 (en) * | 2004-08-17 | 2012-05-29 | Rambus Inc. | Memory device having staggered memory operations |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US7254075B2 (en) * | 2004-09-30 | 2007-08-07 | Rambus Inc. | Integrated circuit memory system having dynamic memory bank count and page size |
US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US7130238B1 (en) * | 2005-01-21 | 2006-10-31 | Altera Corporation | Divisible true dual port memory system supporting simple dual port memory subsystems |
US7289369B2 (en) * | 2005-04-18 | 2007-10-30 | International Business Machines Corporation | DRAM hierarchical data path |
CN1870873A (zh) * | 2005-05-28 | 2006-11-29 | 深圳富泰宏精密工业有限公司 | 铰链装置及应用该铰链装置的便携式电子装置 |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
JP2013114701A (ja) * | 2011-11-25 | 2013-06-10 | Toshiba Corp | 半導体記憶装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2647394C2 (de) * | 1976-10-20 | 1978-11-16 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | MOS-Halbleiterspeicherbaustein |
JPS58147884A (ja) * | 1982-02-26 | 1983-09-02 | Toshiba Corp | ダイナミック型半導体記憶装置 |
US4520465A (en) * | 1983-05-05 | 1985-05-28 | Motorola, Inc. | Method and apparatus for selectively precharging column lines of a memory |
JPS60136087A (ja) * | 1983-12-23 | 1985-07-19 | Hitachi Ltd | 半導体記憶装置 |
JPH0743925B2 (ja) * | 1984-03-28 | 1995-05-15 | 株式会社日立製作所 | 半導体記憶装置 |
-
1984
- 1984-05-04 JP JP59088331A patent/JPS60234295A/ja active Granted
-
1985
- 1985-05-01 US US06/729,200 patent/US4636982A/en not_active Expired - Fee Related
- 1985-05-03 KR KR8503025A patent/KR890004457B1/ko not_active IP Right Cessation
- 1985-05-03 DE DE8585400865T patent/DE3584189D1/de not_active Expired - Fee Related
- 1985-05-03 EP EP85400865A patent/EP0165106B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS60234295A (ja) | 1985-11-20 |
KR890004457B1 (en) | 1989-11-04 |
EP0165106A2 (de) | 1985-12-18 |
JPH0527194B2 (de) | 1993-04-20 |
US4636982A (en) | 1987-01-13 |
EP0165106B1 (de) | 1991-09-25 |
KR850008569A (ko) | 1985-12-18 |
EP0165106A3 (en) | 1989-02-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |