DE2932569C2 - Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen - Google Patents
Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-BauelementenInfo
- Publication number
- DE2932569C2 DE2932569C2 DE2932569A DE2932569A DE2932569C2 DE 2932569 C2 DE2932569 C2 DE 2932569C2 DE 2932569 A DE2932569 A DE 2932569A DE 2932569 A DE2932569 A DE 2932569A DE 2932569 C2 DE2932569 C2 DE 2932569C2
- Authority
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- Prior art keywords
- hydrogen
- density
- layer
- reducing
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 229910008065 Si-SiO Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 229910006405 Si—SiO Inorganic materials 0.000 claims description 2
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 150000002431 hydrogen Chemical class 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 238000005496 tempering Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 101000608653 Homo sapiens UbiA prenyltransferase domain-containing protein 1 Proteins 0.000 description 3
- 201000004224 Schnyder corneal dystrophy Diseases 0.000 description 3
- 102100039547 UbiA prenyltransferase domain-containing protein 1 Human genes 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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Description
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Die vorliegende Patentanmeldung betrifft ein Verfahren zur Reduzierung der Dichte der schnellen Oberflüchenzustände
bei MOS-Bauelementen, insbesondere bei oberflächenladungsgekoppelten Bauelementen
(SCCDs = Surface-Charge-Coupled-Devices), durch Ab-Sättigung der freien Valenzen an der Si-StCVGrenzfläche
mit Wasserstoff. Ein derartiges Verfahren ist aus der DE-OS 21 14 566 bekannt.
Besonders für oberflächenladungsgekoppelte Bauelemente, wie sie beispielsweise in dem Buch »Charge
Transfer Devices« von S6quin und Tompsett, Academic-Press, New York, (1975), S. 11/12, beschrieben sind, sind
niedrige Oberflächenzustandsdichten an der Si-SiO2-Grenzfläche
von entscheidender Bedeutung für die Übertragungseigenschaften (und Dunkelstrom). Üblicherweise
wird in der Technologie bei der Herstellung von MOS-Bauelementen nach einer sorgfältigen Gate-Oxidation
eine Wasserstofftemperung In Gasatmosphäre durchgeführt. Vom Wasserstoff ist aus einem Aufsatz von Deal
aus dem »Journal of the Electrochemical Society«, Bd. 121, Nr. 6, S. 198 c bis 205 c (1974) bekannt, daß er freie
Bindungen (dangling bonds) an der Sl-S^-Grenzfläche
absättigt. Wesentlich ist hierbei die Dissoziierung des H2-Molekuls
in atomaren Wasserstoff. Diese Temperung in Wasserstoff-Atmosphäre wird bei Temperaturen im
Bereich von 400 bis 500° C In einer Zeitdauer von ca. 30 Minuten durchgeführt. Oberflächenzustandsdichten, die
sich mit diesem Verfahren erreichen lassen, liegen bei (5 bis 10)· Wcm^eV'1; für oberflächenladungsgekoppelte
Bauelemente bedeutet dies einen normierten Übertragungsverlust von ungefähr (1 bis 2)· 10~* mit Grundladung,
was für viele Anwendungen, nicht ausreichend ist.
Die Aufgabe, die der Erfindung zugrundeliegt, besteht demnach in einer weiteren Reduzierung der Oberflächenzustandsdichte
und damit in der Optimierung der Übertragungseigenschaften von CCD-Bauelementen.
Diese Aufgabe wird bei einem Verfahren der eingangs genannten Art durch die Merkmale im kennzeichnenden
Teil des Patentanspruchs 1 gelöst. Aus der Zeitschrift IEEE Transactions on Electron Devices, Bd. ED-26,
Nr. 4 (April 1979), Seiten 647 bis 657 ist zwar eine gemäß dem Merkmal a) hergestellte Si.vN,H.-Schicht bekannt,
diese dient jedoch lediglich Passivierungszwecken.
Besonders vorteilhafte Weiterbildungen ergeben sich aus cien Unteransprüchen.
Als Reaktionsgas wird vorzugsweise Silan (SiH4) verwendet,
welches mit Stickstoff (N2) oder Ammoniak (NHi) verdünnt ist. Durch diesen zusätzlichen Einbau
von Stickstoff wird bei dem nachfolgenden Temperprozeß eine Umwandlung der amorphen Schicht in eine
polykristalline Modifikation verhindert.
Das Si: H-Alomverhältnis kann zwischen 2 bis 10
variieren, das N : Sl-Atomverhältnis kann bis 1,3 ansteigen.
Die Abscheidung wird bei der Herstellung von MOS-Bauelementen
zusätzlich zum normalen Doppel-Poly-Siliziun-Piozeß
durchgeführt. Vor der Temperung werden in die amorphe SixN,H.-Schicht mittels üblicher fotolilhografischer
Verfahren Kontaktfenster zum Anbringen der Golddrahtkontakte geätzt.
Entscheidend für die Einstellung der Oberflächenzusiandsdichien
ist der auf die Abscheidung der Wasserstoff enthaltenden Schicht folgende Temperprozeß.
Durch diese Temperung werden nämlich bevorzugt die Si-FI-Bindungen in der Schicht aufgebrochen, so daß
direkt der hierdurch frei werdende atomare Wasserstoff zur SiO2/SI-Grenzfläche diffundieren und dort die freien
Valenzen absättigen kann. Durch Optimierung dieser Temperung sind Oberflächenzustandsdichten von
(6 ± 2)· 18* cm 2eV ' erreichbar.
Weitere Einzelheiten sind den Fig. 1 bis 3 zu entnehmen.
Dabei zeigen die Fig. 1 und 2 Modelldarstellungen über den Vorgang der Absältigung der freien Valenzen
mit Wasrerstoff, wobei Fig. 1 den Stand der Technik und die Flg. 2 das neue Verfahren darstellen. Der Doppelpfeil
in Flg. 1 und 2 kennzeichnet die Übergangszone SlO2/Si, während die einfachen Pfeile die Diffustonswege
der Wasserstoffatome markieren. Die schraffierte Fläche zeigt den Elektrodenbereich an. Mit dem Symbol Ns, in
Flg. 1 Ist die Lage der schnellen Oberflächenzustände
bezeichnet (In Flg. 2 durch atomaren Wasserstoff Fi abgesättigt). Die Bezeichnung SixN1H. in Fig. 2 soll die
Lage der zusätzlich aufgebrachten amorphen Schicht nach der Lehre der Erfindung darstellen.
Folgende Reaktionen spielen sich bei den in den Fig. 1 und 2 dargestellten Modellen ab:
Figur 1 mit H2-GaS
(I)=Si- + H2 ^=Si-H + H
Figur 1 mit H2-GaS
(I)=Si- + H2 ^=Si-H + H
(2)==Si — + H v=Si — H
die Reaktion (1) verläuft sehr langsam.
Figur 2 mit SixNyHz-Schicht
(1) SixNyH, >
SixNyH,_, + H
(2)=Si— + H V=Si-H
Aus Fi g. 3 sind die durch das neue Verfahren zu erreichenden Werte zu entnehmen. Dabei ist in einem Kurvendiagramm
der Verlauf der typischen Oberflächenzustandsdichte Nss, der mit der Leitwertmethode an MOS-Kondensätoren
gemessen wurde, aufgeze'chnet, wobei der Abschnitt a den Wert der Obcrflächenzustandsdichtc
gemessen an einem Bauelement gemalj dem Stand der
Technik, der Abschnitt b den Wert nach Aufbringen der Si-Wasserstoff enthaltenden Schicht und der Abschnitt c
die Oberflächenzustandsdichte nach erfolgter leichter
Temperung der aufgebrachten amorphen Schicht in Stickstoff darstellen.
Wie aus dem Diagramm zu entnehmen ist, wird hier eine Oberfiächenzusiandsdichte Nss jcm :eV '] von
4- 108cm 2eV ' erreicht.
Das Verfahren ist anwendbar für alle SCCD-Bauelemente
sowie MOS-Bauelemente mit oberflächengenerierten Dunkelströmen. Die an nach dem erfindungsgemäßen
Verfahren hergestellten SCCD-Bauelementen gemessenen Ladungsverluste von 1 · 10' sind eine wichtige
Voraussetzung für ihre Anwendung als hochintegrierte Filter, Speicher und Sensoren. Die Übertragungseigenschaften sind optimal. Durch die niedrige Oberflächenzustandsdichte
ist ferner der Anteil des von der Oberflächengeneration herrührender. Sperrstroms sehr
klein. Der Dunkelstrom ist auf eine Elektrode bezogen um den Faktor 3 kleiner als bei den bisher bekannten
Anordnungen.
Hierzu 2 Blatt Zeichnungen
Claims (4)
1. Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen,
insbesondere bei oberflächenladungsgekoppelten Bauelementen, durch Absättigung der freien Valenzen
an der Si-SiOi-Grenzfläche mit Wasserstoff, dadurch gekennzeichnet, daß
a) die mit Elektroden versehenen Bauelementstrukturen an ihrer freien SiO2-Oberfläche mit einer,
durch eine elektrische Niederdruckg'immentladung
aus einer Silizium, Wasserstoff und Stickstoff enthaltenden Gasatmosphäre erzeugten
amorphen Schleuder Zusammensetzung SixN1H.
beschichtet werden und
b) anschließend die beschichtete Anordnung bei einer Temperatur, die über der Beschichtungstemperatur,
aber unterhalb 500° C liegt, getempert wird, wobei die freien Valenzen an der Si-SiO2-Grenzfläche
durch den aus der SixN1H--Schicht
ausdlffuiidierenden atomaren Wasserstoff abgesäliigt werden.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß als Reaktionsgas Silan (SiHj) mit Beimengungen
von Stickstoff und/oder Ammoniak verwendet wird und daß die Zusammensetzung der Schicht auf Si2. InN2-6-IjHi eingestellt wird.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß bei der Beschichtung der Gasdruck
auf einen Bereich von 6,6 bis 40 Pa und die Temperatur auf einen Bereich von 100 bis 450° C eingestellt
wird.
4. Verfahren nach Anspruch 1 bis 3, dadurch gekennzeichnet, daß die Schichtdicke auf 100 bis
1000 nm eingestellt wird.
10
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2932569A DE2932569C2 (de) | 1979-08-10 | 1979-08-10 | Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen |
GR61155A GR72931B (de) | 1979-08-10 | 1980-02-08 | |
US06/171,180 US4331709A (en) | 1979-08-10 | 1980-07-22 | Process of reducing density of fast surface states in MOS devices |
FR8016574A FR2463510A1 (fr) | 1979-08-10 | 1980-07-28 | Procede pour reduire la densite des etats de surface rapides dans le cas de composants mos |
CA000357883A CA1152227A (en) | 1979-08-10 | 1980-08-08 | Process of reducing density of fast surface states in mos devices |
GB8026066A GB2056174B (en) | 1979-08-10 | 1980-08-11 | Process for reducing the density of fast surface states inmos-components |
JP11017880A JPS5629368A (en) | 1979-08-10 | 1980-08-11 | Method of lowering fast surface level density for mos device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2932569A DE2932569C2 (de) | 1979-08-10 | 1979-08-10 | Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen |
Publications (2)
Publication Number | Publication Date |
---|---|
DE2932569A1 DE2932569A1 (de) | 1981-02-26 |
DE2932569C2 true DE2932569C2 (de) | 1983-04-07 |
Family
ID=6078215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2932569A Expired DE2932569C2 (de) | 1979-08-10 | 1979-08-10 | Verfahren zur Reduzierung der Dichte der schnellen Oberflächenzustände bei MOS-Bauelementen |
Country Status (7)
Country | Link |
---|---|
US (1) | US4331709A (de) |
JP (1) | JPS5629368A (de) |
CA (1) | CA1152227A (de) |
DE (1) | DE2932569C2 (de) |
FR (1) | FR2463510A1 (de) |
GB (1) | GB2056174B (de) |
GR (1) | GR72931B (de) |
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JPS5676539A (en) * | 1979-11-28 | 1981-06-24 | Sumitomo Electric Ind Ltd | Formation of insulating film on semiconductor substrate |
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GB2140202A (en) * | 1983-05-16 | 1984-11-21 | Philips Electronic Associated | Methods of manufacturing semiconductor devices |
CA1218470A (en) * | 1983-12-24 | 1987-02-24 | Hisayoshi Yamoto | Semiconductor device with polycrystalline silicon active region and ic including semiconductor device |
JP2724702B2 (ja) * | 1985-06-21 | 1998-03-09 | 日本テキサス・インスツルメンツ 株式会社 | 電荷結合型半導体装置の製造方法 |
US4692344A (en) * | 1986-02-28 | 1987-09-08 | Rca Corporation | Method of forming a dielectric film and semiconductor device including said film |
US4826733A (en) * | 1986-12-03 | 1989-05-02 | Dow Corning Corporation | Sin-containing coatings for electronic devices |
JP2589327B2 (ja) * | 1987-11-14 | 1997-03-12 | 株式会社リコー | 薄膜トランジスタの製造方法 |
US4840918A (en) * | 1988-05-09 | 1989-06-20 | Eastman Kodak Company | Method of noise reduction in CCD solid state imagers |
US4840917A (en) * | 1988-07-13 | 1989-06-20 | Eastman Kodak Company | Method of interface state reduction in MNOS capacitors |
US5264724A (en) * | 1989-02-13 | 1993-11-23 | The University Of Arkansas | Silicon nitride for application as the gate dielectric in MOS devices |
US4962065A (en) * | 1989-02-13 | 1990-10-09 | The University Of Arkansas | Annealing process to stabilize PECVD silicon nitride for application as the gate dielectric in MOS devices |
NL8901637A (nl) * | 1989-06-28 | 1991-01-16 | Gen Signal Thinfilm Company B | Werkwijze voor het verwijderen van defekten in een gemetalliseerd halfgeleiderinrichting. |
US5374833A (en) * | 1990-03-05 | 1994-12-20 | Vlsi Technology, Inc. | Structure for suppression of field inversion caused by charge build-up in the dielectric |
JP2666596B2 (ja) * | 1991-04-15 | 1997-10-22 | 株式会社デンソー | 酸化膜中のトラップ密度低減方法、及び半導体装置の製造方法 |
US6413805B1 (en) | 1993-03-12 | 2002-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device forming method |
JPH06349735A (ja) | 1993-06-12 | 1994-12-22 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US6713330B1 (en) | 1993-06-22 | 2004-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
US5488000A (en) | 1993-06-22 | 1996-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor using a nickel silicide layer to promote crystallization of the amorphous silicon layer |
US5529937A (en) * | 1993-07-27 | 1996-06-25 | Semiconductor Energy Laboratory Co., Ltd. | Process for fabricating thin film transistor |
US6897100B2 (en) | 1993-11-05 | 2005-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device |
CN1052566C (zh) * | 1993-11-05 | 2000-05-17 | 株式会社半导体能源研究所 | 制造半导体器件的方法 |
JP3729955B2 (ja) | 1996-01-19 | 2005-12-21 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US5985740A (en) | 1996-01-19 | 1999-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device including reduction of a catalyst |
JP3645378B2 (ja) | 1996-01-19 | 2005-05-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP3645380B2 (ja) | 1996-01-19 | 2005-05-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法、情報端末、ヘッドマウントディスプレイ、ナビゲーションシステム、携帯電話、ビデオカメラ、投射型表示装置 |
JP3645379B2 (ja) * | 1996-01-19 | 2005-05-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6478263B1 (en) * | 1997-01-17 | 2002-11-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and its manufacturing method |
US5888858A (en) | 1996-01-20 | 1999-03-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and fabrication method thereof |
US7056381B1 (en) * | 1996-01-26 | 2006-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Fabrication method of semiconductor device |
US6180439B1 (en) | 1996-01-26 | 2001-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating a semiconductor device |
US6465287B1 (en) | 1996-01-27 | 2002-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating a semiconductor device using a metal catalyst and high temperature crystallization |
US6100562A (en) | 1996-03-17 | 2000-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
JPH1070123A (ja) * | 1996-06-17 | 1998-03-10 | Siemens Ag | 表面状態の不動態化を容易にする層を有する装置構造 |
US6017806A (en) * | 1997-07-28 | 2000-01-25 | Texas Instruments Incorporated | Method to enhance deuterium anneal/implant to reduce channel-hot carrier degradation |
JP3516596B2 (ja) * | 1998-10-19 | 2004-04-05 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US6373114B1 (en) * | 1998-10-23 | 2002-04-16 | Micron Technology, Inc. | Barrier in gate stack for improved gate dielectric integrity |
US6670242B1 (en) | 1999-06-24 | 2003-12-30 | Agere Systems Inc. | Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer |
US6492712B1 (en) | 1999-06-24 | 2002-12-10 | Agere Systems Guardian Corp. | High quality oxide for use in integrated circuits |
US6551946B1 (en) | 1999-06-24 | 2003-04-22 | Agere Systems Inc. | Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature |
GB2355582A (en) * | 1999-06-24 | 2001-04-25 | Lucent Technologies Inc | Gate oxides |
US20030235957A1 (en) | 2002-06-25 | 2003-12-25 | Samir Chaudhry | Method and structure for graded gate oxides on vertical and non-planar surfaces |
GB2370416A (en) * | 2000-07-25 | 2002-06-26 | Agere Syst Guardian Corp | Hydrogenation of dangling bonds at a gate oxide/semiconductor interface |
DE10142267A1 (de) * | 2001-08-29 | 2003-03-27 | Infineon Technologies Ag | Verfahren zum Abscheiden von Siliziumnitrid |
USD720619S1 (en) | 2011-08-22 | 2015-01-06 | Kellogg North America Company | Container |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3627589A (en) * | 1970-04-01 | 1971-12-14 | Gen Electric | Method of stabilizing semiconductor devices |
FR2394173A1 (fr) * | 1977-06-06 | 1979-01-05 | Thomson Csf | Procede de fabrication de dispositifs electroniques qui comportent une couche mince de silicium amorphe et dispositif electronique obtenu par un tel procede |
US4134125A (en) * | 1977-07-20 | 1979-01-09 | Bell Telephone Laboratories, Incorporated | Passivation of metallized semiconductor substrates |
US4113514A (en) * | 1978-01-16 | 1978-09-12 | Rca Corporation | Method of passivating a semiconductor device by treatment with atomic hydrogen |
US4181751A (en) * | 1978-05-24 | 1980-01-01 | Hughes Aircraft Company | Process for the preparation of low temperature silicon nitride films by photochemical vapor deposition |
-
1979
- 1979-08-10 DE DE2932569A patent/DE2932569C2/de not_active Expired
-
1980
- 1980-02-08 GR GR61155A patent/GR72931B/el unknown
- 1980-07-22 US US06/171,180 patent/US4331709A/en not_active Expired - Lifetime
- 1980-07-28 FR FR8016574A patent/FR2463510A1/fr active Granted
- 1980-08-08 CA CA000357883A patent/CA1152227A/en not_active Expired
- 1980-08-11 GB GB8026066A patent/GB2056174B/en not_active Expired
- 1980-08-11 JP JP11017880A patent/JPS5629368A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
DE2932569A1 (de) | 1981-02-26 |
GR72931B (de) | 1984-01-12 |
JPS6229914B2 (de) | 1987-06-29 |
FR2463510A1 (fr) | 1981-02-20 |
FR2463510B1 (de) | 1984-08-24 |
CA1152227A (en) | 1983-08-16 |
JPS5629368A (en) | 1981-03-24 |
US4331709A (en) | 1982-05-25 |
GB2056174A (en) | 1981-03-11 |
GB2056174B (en) | 1983-06-08 |
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