DE10218155B4 - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device comprising: a first insulating film (10) formed over a semiconductor film; a first metal pattern (12a, 12b) buried in the first insulating film; and a first cap layer (13) formed on the first metal pattern and the first insulating film and made of zirconium nitride or a zirconium nitride compound, a film thickness of the first cap layer (13) being equal to or less than 18.7 nm.

Description

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure including a copper layer wiring, and a method of manufacturing the same.

2. Description of the Related Art

Along with the progress of semiconductor integrated circuit (LSI) process technology, various semiconductor elements are becoming more and more miniaturized. Also, with the high density, the increase in the number of layers and the reduction in the thickness of the wirings in the LSI, rapid progress has been made, and so the load applied to the wirings and the density of the current, respectively, are increasing flowing through the wiring, constantly closing. As a result, when the high-density current flows through the wirings, the wiring is easily broken, which is called electromigration (EM). It is believed that the driving force of electromigration is generated when metal atoms are moved and diffuse at high density due to the collision of the electron fluxes. As the quality degradation phenomenon due to electromigration becomes more intense as the element is miniaturized, development of the wiring material and the wiring structure is required, through which the high-density current can flow and which can achieve the high reliability.

As wiring in which the electromigration hardly occurs unlike in the aluminum wiring, the copper wiring is available.

However, the fine patterning of the copper layer is difficult. As one of the effective solutions for producing the copper wiring, the damascene method is used in practice, which includes the steps of forming the wiring trench in the insulating film in advance and then burying the copper layer therein. Also, the dual damascene method is known in which the via and the wiring are simultaneously formed by forming the via hole under the wiring trench.

An example of steps for making the passage through the damascene method is now in FIG 1A to 1D shown.

First, as in 1A shown an interlayer insulating film 102 on a semiconductor substrate 101 formed, and a first silicon oxide film 103 and a silicon nitride film 107 are on the interlayer insulating film 102 educated. Then, a first wiring ditch 104 in these films 103 . 107 formed by the first silicon oxide film 103 and the silicon nitride film 107 be patterned. Then a barrier metal layer 105 and a first copper layer 106 sequentially in the first wiring trench 104 and on the silicon nitride film 107 formed around the first wiring ditch 104 to completely bury. Then the first copper layer 106 and the barrier metal layer 105 polished by the chemical mechanical polishing (CMP) method and from the top surface of the silicon nitride film 107 away.

Therefore, as in 1B shown the first copper layer 106 that only in the first wiring ditch 104 remained as copper wiring 106a used. Then, a second silicon oxide film 108 on the silicon nitride film 107 or the copper wiring 106a educated.

After that, as in 1C shown a through hole 109 on the copper wiring 106a formed by the second silicon oxide film 108 is patterned.

Then, as in 1D shown a second barrier metal layer 110 and a second copper layer 111 in the through hole 109 and on the second silicon oxide film 108 educated. After that, the second copper layer 111 and the second barrier metal layer 110 polished by the CMP method and from the upper surface of the second silicon oxide film 108 away. Then the second copper layer 111 in the through hole 109 remained as a passage 111 used.

The multilayer copper wiring structure can be obtained by repeating the formation of the copper wiring and the formation of the via according to the above steps.

If the through hole 109 , as in 1C shown in the second silicon oxide film 108 Incidentally, the copper wiring is formed 106a from the through hole 109 exposed and exposed directly to the outside air.

As a result, it is possible that the copper wiring 106a contaminates, corrodes and oxidizes, and thus becomes a defective connection between the copper wiring 106a and the passage 111 causes. As a measure, the process for cleaning the copper wiring 106a from the through hole 109 executed. In this case, if the aspect ratio of the through-hole 109 increases it becomes difficult to surface the copper wiring 106a completely clean.

The publication EP 1 083 596 A1 shows a dual damascene structure with a dielectric layer comprising an opening with a buried copper layer. The top of the copper layer is covered with a thin film which may contain Si ₃ N ₄ or other dielectric materials. In addition, a cap layer may be provided covering the top of the dielectric layer.

From the publication US 5,426,330 For example, there is known a semiconductor manufacturing method in which a metal film is deposited on an insulating film having an opening, which in turn is covered with an adhesion promoting layer which may include titanium or titanium nitride.

As a further prior art, the following publications are mentioned: JP 05129224 A . DE 3784605 T2 and WO 00/54330 A1 ,

It is an object of the present invention to provide a semiconductor device by which surface oxidation / corrosion of metal patterns used for copper wiring or passage can be prevented, and a method of manufacturing the same.

These objects are solved by the features of claims 1 and 8.

According to the present invention, the cap layer formed of the substance with which the electrical resistance on the first metal pattern film becomes smaller than the electrical resistance on the insulating film is formed on the first insulating film and the first metal pattern. The metal pattern is, for example, the copper wiring or the copper passage.

As a material for such a capping layer, zirconium nitride which is chemically stable, its compound, etc. are available. It is preferable if the film thickness is less than 20 nm.

Therefore, when the hole or trench is formed on the first metal pattern and the second insulating film formed on the first insulating film, oxidation, corrosion and contamination of the first metal pattern under the hole or trench are prevented by the cap layer ,

In addition, the second metal pattern formed in the hole or trench is electrically connected to the first metal pattern through the cap layer. Since the cap layer acts as an insulating portion on the first insulating film, the patterning of the cap layer can be omitted.

The zirconium nitride or any of its compounds, and the non-inventive zirconium, titanium, hafnium forming such a capping layer, may be selectively etched on the first insulating film by adjusting the etching conditions while remaining on the first metal pattern. As a result, such a cap layer can be selectively removed from the upper surface of the first insulating film by the selective etching without a mask and remain on the first metal pattern.

If the copper diffusion from the first metal pattern containing the copper is to be surely prevented in the insulating film, the second cap layer made of the copper diffusion preventing insulating material may be formed on the cap layer.

BRIEF DESCRIPTION OF THE DRAWINGS

1A to 1D FIG. 11 are sectional views showing steps of forming the multilayer copper wiring structure of the prior art; FIG.

2A to 2F 10 are sectional views showing a semiconductor device manufacturing method according to a first embodiment of the present invention;

3 Fig. 10 is a sectional view showing a test piece used for testing a dependence of a resistivity of a zirconium nitride film used in the semiconductor device according to the embodiment of the present invention on the underlying layer;

4 Fig. 12 is a graph showing a relationship between a film thickness and the resistivity of the zirconium nitride film on the insulating film;

5 Fig. 12 is a graph showing a relationship between the film thickness and the resistivity of the zirconium nitride film on the metal film;

6A to 6L 10 are sectional views showing a semiconductor device manufacturing method according to a second embodiment of the present invention;

7 FIG. 12 is a graph of resistance changes of the wiring by annealing the copper wiring and the conductive cap layer formed thereon in FIG Semiconductor device according to the embodiment of the present invention;

8A to 8C FIG. 15 is views each showing a relationship between a film thickness of a ZrN cap layer on the copper wiring and a wiring resistance in the semiconductor device according to the embodiment of the present invention; FIG. and

9A to 9E 10 are sectional views showing a semiconductor device manufacturing method according to a third embodiment of the present invention.

10A to 10E 10 are sectional views showing a semiconductor device manufacturing method according to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be explained below with reference to the accompanying drawings.

First Embodiment

2A to 2F 10 are sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, a structure will be explained below 2A is shown.

An element isolation insulation layer 2 is on a p-type silicon (semiconductor) substrate 1 formed to surround a zone of active elements. A MOS transistor 3 is formed in the zone of active elements. The MOS transistor 3 has a gate electrode 3b on the silicon substrate 1 by means of a gate insulating film 3a is formed, and first and second n-type impurity diffusion layers 3c . 3d on the silicon substrate 1 respectively on both sides of the gate electrode 3b are formed to obtain the LDD structure. Furthermore, an insulating side wall 3e on both side surfaces of the gate electrode 3b educated.

A first interlayer insulating film 4 SiO ₂ is on the silicon substrate 1 formed to the MOS transistor 3 to cover. A first contact hole 4a and a second contact hole 4b are in the first interlayer insulating film 4 on the first n-type impurity diffusion layer 3c and the second n-type impurity diffusion layer, respectively 3d educated.

A first conductive plug 5a and a second conductive plug 5b are in the first and second contact holes 4a . 4b buried. The first and second conductive plugs 5a . 5b have a double-layered structure formed of a titanium nitride film and a tungsten film, respectively.

A first-layer wiring 7 connected to the second conductive plug 5b is connected and made of aluminum is on the first Zwischenschichtisolierfilm 4 educated. Further, a second interlayer insulating film is 8th of any of SiO ₂ , BPSG, PSG, etc., on the first interlayer insulating film 4 and first-layer wiring 7 educated. A contact hole 8a is in the second interlayer insulating film 8th on the first conductive plug 5a educated. A third conductive plug 9 which has a double-layered structure comprising the titanium nitride film and the tungsten film is in the contact hole 8a buried.

The second interlayer insulating film 8th and the third conductive plug 9 are with a third interlayer insulating film 10 covered, which has a thickness of 350 nm and is made of SiO ₂ . Then there is a first wiring ditch 10a and a second wiring trench 10b in the third interlayer insulating film 10 educated.

The first wiring ditch 10a has a shape, part of which is the third conductive plug 9 overlaps. A first copper wiring 12a with a multi-layered structure comprising a barrier metal layer 11a of tantalum, tantalum nitride, titanium nitride or the like and a copper layer 11b is in the first wiring trench 10a educated. Further, a second copper wiring 12b with the same layer structure as the first copper wiring 12a in the second wiring trench 10b educated.

After the first and second copper wiring 12a . 12b formed as described above, a first cap layer 13 zirconium nitride (ZrN), as in 2 B shown on the third interlayer insulating film 10 and the first and second copper wirings 12a . 12b educated. The formation of the zirconium nitride can be carried out by the CVD method using tetrakisdiethylaminozirconium (Zr {N (C ₂ H ₅ ) ₂ } ₄ ; TDEAZ) or the PVD method such as sputtering, evaporation or the like.

The ZrN cap layer 13 is formed to have a thickness larger than 0 nm but smaller than 20 nm. Such a ZrN cap layer 13 serves as a low resistance layer 13a , whose resistivity is less than about 300 μΩ · cm, in the zone where the ZrN capping layer 13 the barrier metal layer 11a and the copper layer 11b contacted the first and second copper wires 12a . 12b and as a high resistance layer 13b whose resistivity is greater than several thousand μΩ · cm or over tens of thousands μΩ · cm, in the zone where the ZrN cap layer 13 the third interlayer insulating film 10 contacted, which is formed of SiO ₂ . Their details will be described later.

Then, as in 2C a fourth interlayer insulating film is shown 14 with a thickness of 350 nm of SiO ₂ on the ZrN cap layer 13 formed by the CVD method. And a silicon nitride film 15 with a thickness of 50 nm is formed on the fourth interlayer insulating film 14 formed by CVD. Further, a fifth interlayer insulating film becomes 16 with a thickness of 300 nm of SiO ₂ on the silicon nitride film 15 educated. In this case, a zirconium nitride film having a thickness of less than 20 nm may be used in place of the silicon nitride film 15 be used.

After that, as in 2D Shown is the fifth interlayer insulating film 16 patterned, leaving a third wiring ditch 16a part of which is the first copper wiring 12a overlaps, and at the same time becomes a fourth wiring ditch 16b part of which is the second copper wiring 12b overlaps. Also the fourth interlayer insulating film 14 is patterned, so that a first through hole 14a is formed in the zone in which the third wiring trench 16a the first copper wiring 12a overlaps, and at the same time becomes a second through hole 14b formed in the zone in which the fourth wiring trench 16b the second copper wiring 12b overlaps.

The order of formation of the first and second through holes 14a . 14b and forming the third and fourth wiring trenches 16a . 16b can be selected arbitrarily. The silicon nitride film 15 may act as an etch stopper layer at the time when the third and fourth wiring trenches 16a . 16b be formed.

These through holes 14a . 14b are respectively on the first layer copper wiring 12a . 12b formed around the low resistance layer 13a the ZrN cap layer 13 to expose.

Then, as in 2E shown a barrier metal layer 17 with a thickness of 5 to 10 nm on inner peripheral surfaces and bottom surfaces of the first and second through holes 14a . 14b and the third and fourth wiring trenches 16a . 16b or on the upper surface of the fifth interlayer insulating film 16 educated. The barrier metal layer 17 is formed by the sputtering method and made of any of tantalum (Ta), tantalum nitride (TaN) and their laminated film or titanium nitride (TiN), for example.

In addition, a copper seed layer 18 on the barrier metal layer 17 formed by the sputtering method to have a thickness of 30 to 100 nm.

Then a copper layer 19 on the copper seed layer 18 formed by electrolytic plating, whereby the third and fourth wiring trenches 16a . 16b and the first and second through holes 14a . 14b be completely buried. Here is the copper seed layer 18 a part of the copper layer 19 ,

Then, as in 2F shown the copper layer 19 and the barrier metal layer 17 deposited on the fifth interlayer insulating film 16 are formed, removed by the CMP method. Therefore, the copper layer 19 , the copper seed layer 18 and the barrier metal layer 17 in the first and second through holes 14a . 14b remain as first or second passages 20a . 20b used. Furthermore, the copper layer 19 and the barrier metal layer 17 that in the third and fourth wiring trenches 16a . 16b remain as third and fourth copper wirings 21a . 21b used.

The third copper wiring 21a is with the first copper wiring 12a over the first passage 20a and the cap layer 13 electrically connected. Further, the fourth copper wiring 21b with the second copper wiring 12b over the second passage 20b and the cap layer 13 electrically connected.

Having a second layer cap layer (not shown) made of the same material as the above cap layer 13 is formed and has a thickness of less than 20 nm, on the third and fourth copper wirings 21a . 21b and the fifth interlayer insulating film 16 In addition, the copper wiring having the multilayer structure may be formed on the second interlayer insulating film 8th by repeating the formations of the interlayer insulating film, the copper wiring and the via according to the above steps.

However, the first and second passes are 20a . 20b with the first and second copper wirings, respectively 12a . 12b through the low resistance layer 13a the ZrN cap layer 13 connected, which has a thickness of less than 20 nm. Because the ZrN cap layer 13 in this case, on the third interlayer insulating film 10 made of SiO ₂ as a high resistance layer 13b serves, become the third copper wiring 21a and the fourth copper wiring 21b through the ZrN cap layer 13 never shorted. Because the zirconium nitride is chemically stable and oxidizes less than copper, it is additionally not possible that the ZrN cap layer 13 oxidized or corroded, even if such a layer is exposed through the through hole and the wiring trench. Therefore, the ZrN cap layer 13 serve as a conductive / insulating protective film that prevents oxidation and corrosion of the copper wiring and copper passage.

The fact that the value of the electrical resistance of the zirconium nitride film depends on the material of the underlying layer will be explained below.

First, as in 3 shown an insulating film 31 with a thickness of 100 nm of SiO ₂ and a metal film 32 with a thickness of 50 nm of titanium nitride (TiN) sequentially on a silicon wafer 30 formed, and then becomes a part of the insulating film 31 by patterning the metal film 32 exposed. Then, a zirconium nitride (ZrN) film 33 on the insulating film 31 and the metal film 32 formed by the CVD method. As a material used to form the zirconium nitride film 33 used by the CVD method, TDEAZ and ammonia (NH ₃ ) are used. Further, the temperature of the silicon wafer becomes 30 set to 380 ° C when the zirconium nitride film 33 should grow.

When a relationship between the film thickness and the resistivity of the zirconium nitride film 33 that on the SiO ₂ insulating film 31 is formed, while the film thickness of the ZrN film 33 obtained under such conditions, results obtained in 4 are shown. According to 4 is the resistivity of the zirconium nitride film 33 about 3300 μΩ · cm when the film thickness is 20 nm, and the resistivity increases abruptly when the film thickness is smaller than about 18.7 nm, and the resistivity reaches 10000 μΩ · cm when the film thickness is 17.8 nm is. Even if a silicon oxide nitride film, a silicon nitride film or a silicon oxide fluoride film is used as the insulating film 31 is used, similar results can be obtained.

When examining a relationship between the film thickness and the resistivity of the zirconium nitride film on the TiN metal film 32 On the other hand, results obtained in 5 are shown. If the copper film as a metal film 32 is used, similar results are achieved.

If the zirconium nitride film 33 on the insulating film 31 is formed to have the thickness of less than 20 nm, the resistivity increases according to 4 to give the insulating film whose resistivity is more than several thousand μΩ · cm. Even if the film thickness of the zirconium nitride film 33 is below 20 nm, the zirconium nitride film serves 33 on the metal film 32 in contrast, as a conductive film whose resistivity is less than about 300 μΩ · cm.

As a result, it is understood that the specific resistance of the zirconium nitride film depends on the material of the underlying film. This phenomenon is similar in the case where the zirconium nitride film is formed not by the CVD method but by the PVD method such as sputtering, evaporation or the like.

In this case, as a cap layer 13 For example, a film of any substance of the zirconium nitride compound formed by three non-inventive zirconium, titanium, hafnium, three non-inventive zirconium compound, titanium compound or hafnium compound in place of the zirconium nitride to have a thickness larger than 0 nm but smaller than 20 nm is. If the substance is the cap layer 13 is formed by the PVD method such as sputtering, etc., it is preferable to form such a substance on the third interlayer insulating film 10 using the oxygen in the third interlayer insulating film 10 by annealing the formed substance at the temperature of, for example, nearly 400 ° C to increase the electrical resistance. If the oxidation of the substance, the cap layer 13 represents, on the copper wiring 12a . 12b It is also preferable to use the cap layer 13 with upper portions of the first and second copper wirings (copper patterns) 12a . 12b to alloy.

Meanwhile, after the silicon oxide film having a thickness of 100 nm and the zirconium nitride film having a thickness of 10 nm were sequentially formed on the silicon wafer, the titanium nitride (TiN) film having a thickness of 50 nm was formed on the zirconium nitride film at the wafer temperature of 350 ° C formed by the CVD method using Tetrakisdiethylaminotitan (TDEAT) and ammonia (NH ₃ ). Then, when the specific resistance of the titanium nitride film was measured, 200 μΩ · cm was obtained. As a result, it was found that the resistance of the TiN film (metal film) formed on the portion whose resistance is more increased than that of the zirconium nitride film is not further increased.

Second Embodiment

In the first embodiment, the cap layer is 13 which is ZrN, or Zr, Hf or the like not according to the invention, on the copper wirings 12a . 12b and the third interlayer insulating film 10 educated. If the copper wiring 12a . 12b and the cap layer 13 alloyed together by the Annealprozeß, there is the possibility that copper elements of the cap layer 13 in the third interlayer insulating film 10 and the fourth interlayer insulating film 14 diffuse.

Therefore, steps for forming the semiconductor device having the structure by which the copper diffusion into the third and fourth interlayer insulating films are explained below 10 . 14 can be prevented infallibly.

6A to 6L 10 are sectional views showing steps of manufacturing a semiconductor device according to a second embodiment of the present invention. In 6A to 6L denote the same symbols as in 2A to 2F the same elements.

The following steps will first explain the steps required to complete the in 6A To form shown structure.

The element separation insulation layer 2 becomes on the p-type silicon substrate 1 is formed to surround the zone of the active elements, and then the MOS transistor 3 with the structure shown in the first embodiment is formed in the zone of the active elements.

Then, the first interlayer insulating film becomes 4 of SiO ₂ on the silicon substrate 1 formed to the MOS transistor 3 to cover. After that, the first contact hole 4a and the second contact hole 4b in the first interlayer insulating film 4 on the first n-type impurity diffusion layer 3c and the second n-type impurity diffusion layer, respectively 3d educated. Then the first conductive plug 5a and the second conductive plug 5b in the first contact hole 4a or the second contact hole 4b buried. The first and second conductive plugs 5a . 5b each have the double-layered structure comprising the titanium nitride film and the tungsten film.

Then the first-layer wiring 7 connected to the second conductive plug 5b and is made of aluminum on the first interlayer insulating film 4 educated. Thereafter, the second interlayer insulating film becomes 8th on the first interlayer insulating film 4 and first-layer wiring 7 educated. Then the contact hole 8a in the second interlayer insulating film 8th on the first conductive plug 5a and thereafter becomes the third conductive plug 9 with the double-layered structure comprising the titanium nitride film and the tungsten film in the contact hole 8a buried.

In this state, the third interlayer insulating film becomes 10 having a thickness of 300 nm and made of SiO ₂ on the second interlayer insulating film 8th and the third conductive plug 9 formed by the CVD method. Thereafter, the silicon nitride film having a thickness of 50 nm is formed on the third interlayer insulating film 10 by the CVD method as an insulating first stopper layer 40 educated.

After that, the resist becomes 39 on the first stopper layer 40 applied, and then become opening sections 39a . 39b that have wiring patterns that over the third conductive plug 9 by exposing / developing the resist 39 educated.

Then, as in 6B and 6C shown, the first and second wiring trenches 10a . 10b in the first stopper layer 40 and the third interlayer insulating film 10 formed by the etching, wherein the resist 39 is used as a mask. The first wiring ditch 10a has a shape of which a part on the third conductive plug 9 is positioned. In this case, the first and second wiring trenches 10a . 10b , as in 6C by etching the third interlayer insulating film 10 are formed while the first stopper layer 40 , in which openings are formed, is used as a mask.

Then, as in 6D shown, the first barrier metal layer 11a on inner peripheral surfaces and bottom surfaces of the first and second wiring trenches 10a . 10b or the upper surface of the first stopper layer 40 educated. The barrier metal layer 11a is formed by the sputtering method and made of, for example, any of Ta, TaN and their laminated film or TiN.

In addition, the copper seed layer becomes 11s on the barrier metal layer 11a formed by the sputtering method to have a thickness of 30 to 100 nm.

After that, as in 6E shown the copper layer 11b on the copper seed layer 11s formed by the electrolytic plating process, whereby the first and second wiring trenches 10a . 10b be completely buried. In this case, the copper seed layer is 11s in the copper layer 11b contain.

Then, as in 6F shown the copper layer 11b and the barrier metal layer 11a formed on the upper surface of the third interlayer insulating film 10 are formed, removed by the CMP method. Here, the first stopper layer is used 40 as a CMP stopper. Therefore, the copper layer 11b and the barrier metal layer 11a located in the first and second wiring trenches 10a . 10b remain as the first and second copper wirings 12a . 12b used.

After the first-layer copper wiring 12a . 12b As stated above, as in 6G shown the first cap layer 13 zirconium nitride (ZrN) on the first stopper layer 40 and the first and second copper wirings 12a . 12b educated. This first cap layer 13 is formed by the ZrN forming method explained in the first embodiment.

The first cap layer 13 ZrN is formed as explained in the first embodiment to have a thickness larger than 0 nm but smaller than 20 nm. Such a ZrN cap layer 13 serves as a low resistance layer 13a , whose resistivity is less than about 300 μΩ · cm, in the zone where the ZrN capping layer 13 the barrier metal layer 11a and the copper layer 11b contacted the first and second copper wires 12a . 12b and as a high resistance layer 13b whose resistivity is greater than several thousand μΩ · cm or over tens of thousands μΩ · cm, in the zone where the ZrN cap layer 13 the third interlayer insulating film 10 contacted, which is made of SiO ₂ .

Then, as in 6H shown an insulating second cap layer 41 having the copper diffusion preventing function on the first cap layer 13 educated. As second cap layer 41 For example, an insulating film of silicon carbide (SiC), silicon nitride (SiN), or a substance containing as a base member, an insulating film of silicon carbide oxide (SiCO), silicon oxynitride (SiON) or a substance containing the same as a base member, or the like by the plasma assisted chemical vapor deposition (PE-CVD) method to have a thickness of 20 to 100 nm.

Typically, the growth of these insulating layers takes place, the second cap layer 41 Further, by using the material gas in the vacuum chamber in which the silicon substrate is formed by using the PE-CVD apparatus of the parallel plate type 1 is arranged through the shower head, then by setting the substrate temperature at 350 to 400 ° C at the base, and then applying the high frequency power whose power is 300 to 600 W and whose frequency is 13.56 MHz to the electrode, the opposite the substrate.

In the formation of the silicon carbide, the organic silane composed mainly of methylsilane is used as the material, and further, methane, ammonia, nitrogen, helium, etc. are added if necessary.

Further, in the formation of the silicon carbide oxide, the oxygen source such as oxygen, nitrogen monoxide, etc. is added to the gas used to form the silicon carbide. If the oxygen is added to the insulating film, there is usually an advantage that the dielectric constant of the film can be reduced and therefore the adhesion between the insulating films can be improved, but the function as a copper diffusion preventing film is reduced.

In the formation of the silicon nitride, such silicon nitride grows by the PE-CVD method as well as the silicon carbide insulating film. In this case, silane gas such as SiH ₄ , Si ₂ H ₆ , etc. is typically used as the silicon material gas, and the silicon nitride can also be formed by using the organic silane gas. Nitrogen or ammonia is supplied to the atmosphere for growth as a nitrogen supply source together with the silicon material gas. In the formation of the silicon oxide nitride, the oxygen source such as oxygen, the nitrogen monoxide is added to the gas used to grow silicon nitride.

Then the second cap layer 41 formed under such conditions. After that, as in 6I a fourth interlayer insulating film is shown 42 which has a thickness of 600 nm and is made of SiO ₂ , and a second stopper layer 43 which has a thickness of 50 nm and is of silicon nitride, sequentially on the second cap layer 41 formed by the CVD method.

Subsequently, as in 6J shown, the second stopper layer 43 , the fourth interlayer insulating film 42 and the second cap layer 41 patterned so that first and second through holes 41a . 41b for exposing the low resistance layer 13a the first cap layer 13 in the second stopper layer 43 , the fourth interlayer insulating film 42 and the second cap layer 41 Further, third and fourth wiring trenches are formed 42a . 42b that the first and second through holes 41a . 41b overlap, in the second stopper layer 43 and the fourth interlayer insulating film 42 educated. The third and fourth wiring trenches 42a . 42b are formed to a depth of about 350 nm from the upper surface of the second stopper layer 43 to have.

It can be arbitrarily selected, which of the formation of the first and second through holes 41a . 41b and forming the third and fourth wiring trenches 42a . 42b executed earlier and separate resist patterns are respectively used as a mask. If the etching stopper layer such as the silicon nitride layer is formed in the middle of the fourth interlayer insulating film, the first and second through holes may be formed 41a . 41b and the third and fourth wiring trenches 42a . 42b are formed by the steps similar to the first embodiment. The formation of the etching stopper layer in the fourth interlayer insulating film may be used in the following embodiments.

Then, as in 6K shown a barrier metal layer 44a on respective inner peripheral surfaces and bottom surfaces of the first and second through holes 41a . 41b and the third and fourth wiring trenches 42a . 42b and on the upper surface of the second stopper layer 43 educated. The barrier metal layer 44a is formed by the sputtering method and made of, for example, any of Ta, TaN and their laminated film or TiN.

In addition, a copper seed layer 44s on the barrier metal layer 44a formed by the sputtering method to have a thickness of 30 to 100 nm.

Then a copper layer 44b on the copper seed layer 44s formed by the electrolytic plating method, whereby the third and fourth wiring trenches 42a . 42b and the first and second through holes 41a . 41b are completely buried. The copper seed layer 44s becomes integral with the copper layer 44b educated.

Next, steps for forming the in 6L shown structure are required.

The copper layer 44b and the barrier metal layer 44a are from the upper surface of the second stopper layer 43 removed by the CMP process, while the second stopper layer 43 is used as a polishing stopper. Therefore, the copper layer 44b and the barrier metal layer 44a in the first and second through holes 41a . 41b remain as first or second passes 45a . 45b used while the copper layer 44b and the barrier metal layer 44a that in the third and fourth wiring trenches 42a . 42b remain as third or fourth copper wirings 46a . 46b be used.

The third copper wiring 46a is through the first passage 45a and the cap layer 13 with the first copper wiring 12a electrically connected. Also the fourth copper wiring 46b is through the second passage 45b and the cap layer 13 with the second copper wiring 12b electrically connected.

Then a third cap layer 47 of the same material as the first cap layer 13 and a fourth cap layer 48 of the same material as the second cap layer 43 sequentially on the third and fourth copper wirings 46a . 46b and the second stopper layer 43 educated.

In addition, the copper wiring having the multi-layered structure becomes on the second interlayer insulating film 8th is formed by repeating the same formations of the interlayer insulating films, the copper wirings and the passages as described above.

In the semiconductor device constructed as above, the portions of the first and third cap layers 13 . 47 from ZrN, with the copper wiring 12a . 12b . 46a 46b are to be used as a layer of low resistance, while the sections of the first and third cap layers 13 . 47 that with the insulating first and second stopper layers 40 . 43 To connect, can serve as a layer with high resistance.

If the first and second copper wiring 12a . 12b and the first cap layer 13 alloyed by annealing, it is possible that the copper from the cap layer 13 in the fourth interlayer insulating film 42 diffused. However, in the present embodiment, further, the insulating second cap layer 41 For preventing the copper diffusion formed on the first cap layer, which is made of ZrN, the copper diffusion from the first and second copper wirings 12a . 12b in the fourth interlayer insulating film 42 through the second cap layer 41 be prevented infallibly. If the first and second stopper layers 40 . 43 are formed from the silicon nitride, they can also function as a copper diffusion prevention layer.

As was tested, how the sheet resistance of the copper wiring 12a . 12b is changed by the annealing after the first cap layer 13 made of ZrN on the copper wiring 12a . 12b was formed, as in 6G Incidentally, results were obtained in 7 are shown. Thus, it was found that the sheet resistance seldom changed.

A dashed line in 7 indicates a difference between the sheet resistance obtained when the annealing is not applied and the sheet resistance obtained when annealing is applied to the copper wiring 12a . 12b without formation of the first cap layer 13 , Furthermore, a continuous Line in 7 a difference between the sheet resistance obtained when the annealing is not applied and the sheet resistance obtained when annealing is applied to the copper wiring 12a . 12b , with the first cap layer 13 connected with a thickness of 2.5 nm. In addition, a dash-dot line in 7 a difference between the sheet resistance obtained when the annealing is not applied and the sheet resistance obtained when annealing is applied to the copper wiring 12a . 12b , with the first cap layer 13 connected to a thickness of 5.0 nm.

8A to 8C show the test result of a relationship between the resistance of the copper wirings, that is, the ZrN capping layer 13 and the copper wiring 12a . 12b in total, and the film thickness of the ZrN cap layer 13 , In this case, a plurality of vertical lines indicate wiring widths of 8 μm (O), 4 μm (□), 2 μm (♢), 1 μm (x), 0.54 μm (+), and 0.27 μm (Δ) in, respectively the order from the left.

8A shows a relationship between the resistance values of the copper wirings 12a . 12b and a cumulative percentage when the ZrN cap layer 13 not formed. 8B Fig. 14 shows a relationship between the resistance values of the copper wirings and the cumulative percentage when the ZrN cap layer 13 with a thickness of 2 nm on the copper wiring 12a . 12b is formed. 8C Fig. 14 shows a relationship between the resistance values of the copper wirings and the cumulative percentage when the ZrN cap layer 13 with a thickness of 4 nm on the copper wiring 12a . 12b is formed.

According to 8A to 8C No dependence of the resistance of the copper wires on the ZrN film thickness is found.

In this case, for the insulating / conductive cap layers 13 . 47 the film of any one of the zirconium nitride compound, the three non-inventive zirconium, titanium, hafnium, the three non-inventive zirconium compound, titanium compound and hafnium compound is used in place of the zirconium nitride. Such materials also apply to the following embodiments.

Third Embodiment

9A to 9E 10 are sectional views showing steps of forming a semiconductor device according to a third embodiment of the present invention. In 9A to 9E denote the same symbols as those in 6A to 6L the same elements.

According to the steps in 6A to 6F In the second embodiment, the MOS transistor becomes 3 on the silicon substrate 1 formed, then the Zwischenschichtisolierfilme 4 . 8th . 10 and the first stopper layer 40 formed, then the wiring 7 formed, then become conductive plugs 5a . 5b . 9 formed, and continue to be the first and second copper wirings 12a . 12b educated.

Then, as in 9A shown the first cap layer 13 ZrN on the first and second copper wires 12a . 12b and the first stopper layer 40 educated. The film thickness of the first cap layer 13 is not limited to a value below 20 nm as described in the first and second embodiments and the first cap layer 13 is formed to have, for example, a thickness of 40 nm.

Then, as in 9B shown the first cap layer 13 etched by selective etching so that such a first capping layer 13 from the upper surface of the third interlayer insulating film 10 is removed, but on the first and second copper wiring 12a . 12b remains. Such selective etching is carried out, for example, under the following conditions.

Although the film density of the ZrN layer depends on the CVD conditions such as the temperature of growth, the gas flow rate, the amount of addition of ammonia, etc., it differs in the metal phase (in the low resistance layer 13a ) on the metal film and in the insulating phase (in the high resistance layer 13b ) on the insulating film greatly. That is, in the ZrN layer, the film density of the insulating phase is typically 5.0 to 5.5 g / cm ³ , while the film density of the metal phase is 6.0 to 6.6 g / cm ³ . Therefore, since the etching rate of the ZrN layer depends on the film density according to various etchants, the ZrN insulating phase can be selectively removed by utilizing this property. If the aqueous solution such. For example, hydrofluoric acid, hydrochloric acid, sulfuric acid, etc., or the chemicals such as hydrogen peroxide, etc., are suitably heated as an etchant, the desired etching rate against the ZrN film can be obtained.

The etching rate of ZrN of the metal phase by the hydrofluoric acid at the temperature of 25 ° C is, for example, 40 nm / min, while the etching rate of ZrN is the insulating phase 53 nm / min. If the first cap layer 13 which has a thickness of 40 nm and is made of ZrN, as in 9A shown on the first and second copper wires 12a . 12b and the third interlayer insulating film 10 is formed and then the hydrofluoric acid having the concentration of 1 wt .-% of the first cap layer 13 for 45 seconds, therefore, the first cap layer 13 with a thickness of 10 nm only on the first and second copper wirings 12a . 12b remain as in 9B shown.

As the etching device for etching the ZrN, the stack type etching device or the sheet supply type etching device may be used. Around the first cap layer 13 However, for a short time to etch with good uniformity, it is preferable to use the sheet feed type etching apparatus.

After the first cap layer 13 etched by the selective etching as described above, the fourth interlayer insulating film becomes 42 which has a thickness of 600 nm and is made of SiO ₂ , and the second stopper layer 43 having a thickness of 50 nm, sequentially on the first cap layer 13 and the first stopper layer 40 formed by the CVD method, as in 9C shown.

Then, as in 9D shown, the second stopper layer 43 and the fourth interlayer insulating film 42 patterned. This will be the first and second through holes 41a . 41b for exposing the first cap layer 13 in the second stopper layer 43 , the fourth interlayer insulating film 42 and the second cap layer 41 and further, the third and fourth wiring trenches are formed 42a . 42b of which a part of the first and second through holes 41a . 41b overlaps, in the second stopper layer 43 and the fourth interlayer insulating film 42 educated. Therefore, the first cap layer 13 through the first and second through holes 41a . 41b exposed.

Next, steps for forming the in 9E shown structure are required.

As in the second embodiment, the barrier metal layer 44a on the inner peripheral surfaces and the bottom surfaces of the first and second through holes 41a . 41b and the third and fourth wiring trenches 42a . 42b or on the upper surface of the second stopper layer 43 educated. In addition, the copper seed layer (not shown) on the barrier metal layer 44a formed to have a thickness of 30 to 100 nm.

The barrier metal layer 44a is formed by the sputtering method and made of, for example, any of Ta, TaN and their laminated film or TiN. Further, the copper seed layer is formed by the sputtering method to have a thickness of 30 to 100 nm.

Then the copper layer becomes 44b formed on the copper seed layer by the electrolytic plating method. So will the third and fourth wiring trenches 42a . 42b and the first and second through holes 41a . 41b completely buried. In this case, the copper seed layer becomes integral with the copper layer 44b educated.

In addition, the copper layer 44b and the barrier metal layer 44a from the upper surface of the second stopper layer 43 removed by the CMP process, while the second stopper layer 43 is used as a polishing stopper. So are the copper layer 44b and the barrier metal layer 44a in the first and second through holes 41a . 41b remain as first or second passes 45a . 45b used while the copper layer 44b and the barrier metal layer 44a that in the third and fourth wiring trenches 42a . 42b remain as third or fourth copper wirings 46a . 46b be used.

The third copper wiring 46a is through the first passage 45a and the cap layer 13 with the first copper wiring 12a electrically connected. Further, the fourth copper wiring 46b through the second passage 45b and the cap layer 13 with the second copper wiring 12b electrically connected.

Thereafter, a second cap layer 49 made of the same material as the first cap layer 13 is on the third and fourth copper wirings 46a . 46b and the second stopper layer 43 educated. Then the second cap layer 49 like the first cap layer 13 selectively etched to only on the third and fourth copper wirings 46a . 46b to remain.

In addition, the copper wiring having the multi-layered structure becomes on the second interlayer insulating film 8th is formed by repeating the same formations of the interlayer insulating films, the copper wirings and the passages as described above.

In the semiconductor device formed according to the above steps, the ZrN cap layers 13 . 49 on the copper wires 12a . 12b . 46a . 46b remain, the oxidation of the copper wiring 12a . 12b . 46a . 46b prevent.

Further, since the ZrN cap layer formed on the third interlayer insulating film is removed, the limitation on the film thickness of the ZrN cap layer can be eliminated. Since the resistance value characteristic of the ZrN cap layer on the insulating film is abruptly changed at about the film thickness of 20 nm, it is difficult to control the film thickness. However, if the selective When etching the ZrN cap layer according to the present embodiment, the ZrN cap layer can never act as a low resistance layer on the insulating film.

The ZrN cap layer can be removed from the upper surface of the third interlayer insulating film by selectively performing the etching without the mask such as the resist, etc. with good precision. Therefore, the formation and the alignment of the resist patterns are not required, and thus the throughput is never greatly reduced.

Fourth Embodiment

In the third embodiment, the ZrN cap layer is selectively removed from the interlayer insulating layer. In this case, it is possible that if the copper in the copper wiring reacts with ZrN in the cap layer, the copper diffuses through the cap layer into the interlayer insulating film.

For this reason, like the second embodiment, the copper diffusion from the copper wiring into the interlayer insulating film can be surely prevented by covering the ZrN layer remaining on the copper wirings with the insulating cap layer. The structure and the steps for forming the same will be explained below.

First, according to the in 6A to 6F shown steps of the MOS transistor 3 on the silicon substrate 1 formed, then the Zwischenschichtisolierfilme 4 . 8th . 10 formed, then the first stopper layer is formed, the wiring 7 formed, then become the conductive connector 5a . 5b . 9 and further, the first and second copper wirings are formed 12a . 12b educated. Then, as in 9A shown the first cap layer 13 ZrN on the first and second copper wires 12a . 12b and the first stopper layer 40 educated. The film thickness of the first cap layer 13 is not limited to 20 nm or less, and the first cap layer 13 is formed to have a thickness of, for example, 40 nm.

Then, as in 10A shown the first cap layer 13 etched by selective etching to remove them from the upper surface of the third interlayer insulating film 10 remove and on the first and second copper wiring 12a . 12b to leave. The selective etching of the first cap layer 13 is performed by the method shown in the third embodiment.

Then, as in 10B shown the insulating second cap layer 41 having the copper diffusion preventing function on the first cap layer 13 educated. As second cap layer 41 For example, the insulating layer containing SiC, SiN as a base element or the insulating layer containing SiCO, SiON as a base element is formed by the PE-CVD method to have a thickness of 20 to 100 nm. The second cap layer 41 is formed according to the method explained in the second embodiment.

Then, as in 10C 4, the fourth interlayer insulating film 42 with a thickness of 600 nm of SiO ₂ and the second stopper layer 43 with a thickness of 50 nm sequentially on the second capping layer 41 formed by the CVD method.

After that, as in 10D shown, the second stopper layer 43 , the fourth interlayer insulating film 42 and the second cap layer 41 patterned. This will be the first and second through holes 41a . 41b for exposing the first cap layer 13 in the second stopper layer 43 , the fourth interlayer insulating film 42 and the second cap layer 41 and further, the third and fourth wiring trenches are formed 42a . 42b that the first and second through holes 41a . 41b overlap, in the second stopper layer 43 and the fourth interlayer insulating film 42 educated.

Next, steps for forming the in 10E shown structure are required.

As in the second embodiment, the barrier metal layer 44a on the inner peripheral surfaces and the bottom surfaces of the first and second through holes 41a . 41b and the third and fourth wiring trenches 42a . 42b or on the upper surface of the second stopper layer 43 educated. The barrier metal layer 44a is formed by the sputtering method and made of, for example, any of Ta, TaN and their laminated film or TiN.

Then, the copper seed layer (not shown) having a thickness of 30 to 100 nm is grown on the barrier metal layer 44a formed by the sputtering process.

In addition, the copper layer 44b formed on the copper seed layer by the electrolytic plating method, whereby the third and fourth wiring trenches 42a . 42b and the first and second through holes 41a . 41b be completely buried. In this case, the copper seed layer becomes the copper layer 44b integrally formed.

Then the copper layer 44b and the barrier metal layer 44a from the upper surface the second stopper layer 43 removed by the CMP method while the second stopper layer 43 is used as a polishing stopper. As a result, the copper layer 44b and the barrier metal layer 44a in the first and second through holes 41a . 41b remain as first or second passes 45a . 45b used, and further, the copper layer 44b and the barrier metal layer 44a that in the third and fourth wiring trenches 42a . 42b remain as third or fourth copper wirings 46a . 46b used.

The third copper wiring 46a is through the first passage 45a and the first cap layer 13 with the first copper wiring 12a electrically connected. Further, the fourth copper wiring 46b with the second copper wiring 12b through the second passage 45b and the first cap layer 13 electrically connected.

Thereafter, the third cap layer 47 ZrN on the third and fourth copper wires 46a . 46b and the second stopper layer 43 educated. In addition, the third cap layer 47 selectively etched to only apply to the third and fourth copper wirings 46a . 46b to leave.

Then the fourth cap layer 48 made of the same material as the second cap layer 41 is formed on the third cap layer 47 and the second stopper layer 43 leave.

Thereafter, the copper wiring having the multi-layered structure as described above is formed on the second interlayer insulating film 8th is formed by repeating the formations of the interlayer insulating films, the copper wirings and the passages.

In the semiconductor device formed according to the above steps, the ZrN cap layers are 13 . 47 that only work on the copper wiring 12a . 12b . 46a . 46b remain, with other cap layers 41 . 48 covered, which are formed from the copper diffusion prevention insulating material. Therefore, it can be prevented that the copper from the copper wiring 12a . 12b . 46a . 46b through the ZrN cap layers 13 . 47 diffused into the interlayer insulating film. Because the ZrN cap layers 13 . 47 In addition, the copper wirings can never be short-circuited from the upper surface of the interlayer insulating film, even if the film thickness is more than 20 nm.

Other Embodiment

In the above embodiments, the interlayer insulating film is formed of SiO ₂ . But the interlayer insulating film may be formed of low dielectric constant insulating material. As the effect of wiring delay on miniaturization of the device is exacerbated, the use of low dielectric constant insulating material becomes much more important. As the low-dielectric-constant insulating material, organic polymer, silicon oxide impregnated with carbon, or porous low-dielectric-constant insulating material may be cited as a typical material.

As a method of forming the low-dielectric-constant insulating material, the spin-coating process for uniformly applying the low-dielectric-constant liquid insulating material to the substrate while rotating the substrate or the PE-CVD method is the representative method. If the porous insulating film of low dielectric constant is formed by the coating process, a hollow body is formed by carrying out the thermolysis of unstable components and the formation of the mold intermediate structure and the thermolysis of the mold using the hydrolysis and the condensation polymerization by the sol-gel method and so the annealing process at about 400 ° C is necessary.

Further, in the above embodiments, as a precursor for burying the copper in the wiring trenches and the through holes, the barrier metal layer and the copper seed layer are formed by the sputtering. But these layers can be formed by the CVD method. For example, if titanium nitride is formed as a barrier metal by the CVD method, TDEAT and ammonia are used as the reaction gas. In addition, the copper seed layer can be formed by the CVD method. As the gas for growing the copper seed layer, for example, Cu (hfac) TMVS is used as the material.

As a method of forming the copper seed layer, the self-ionization plasma method can be used, whereby good coverage at fine through-holes, etc. can be achieved.

In the above embodiments, the dual damascene method is explained with the step of simultaneously burying the barrier metal and the copper in the through-holes and the wiring trench. However, the formation of the via and copper wiring is not limited to the dual damascene process. The damascene process whereby the barrier metal and the copper are buried in the through holes, then the wiring trenches are formed, and then again the barrier metal and the copper are buried in the wiring trenches may be used. In this case, the capping layer made of zirconium nitride or any of their compounds, or of the three non-inventive zirconium, titanium, hafnium or any of their non-inventive compounds may also be formed on the copper passages and copper wirings.

According to the present invention, the first cap layer as described above, which is made of the substance whose portion formed on the copper film has the smaller electrical resistance than the portion formed on the insulating film on the first insulating film and formed the first metal pattern. Therefore, if the holes or the trenches on the first metal pattern are formed by patterning the second insulating film formed on the first insulating film, the first metal pattern can be protected by the first capping layer, and thus the oxidation, corrosion and contamination of the first metal pattern can be protected first metal pattern can be prevented. In addition, since the second metal pattern buried in the holes and the trenches is electrically connected to the first metal pattern through the first cap layer, the electrical conduction between the second metal pattern and the first metal pattern can be ensured.

Further, since the first cap layer serves as an insulating portion on the first insulating film, the patterning of the first cap layer can be omitted, thereby contributing to the reduction of the steps. In this case, since the first cap layer, which is made of zirconium nitride or the like, can be formed while changing the film density on the first insulating film and on the first metal pattern, such a first cap layer can be removed from the upper surface of the insulating film by selective etching without mask be selectively removed. As a result, the patterning step can be simplified.

In addition, the second cap layer made of the copper diffusion prevention insulating material is formed on the cap layer. Therefore, even if the first metal pattern contains copper, the copper diffusion from the first metal pattern into the interlayer insulating film can be unfailingly prevented.

Claims (16)

A semiconductor device comprising: a first insulating film ( 10 ) formed over a semiconductor film; a first metal pattern ( 12a . 12b ) buried in the first insulating film; and a first cap layer ( 13 ) formed on the first metal pattern and the first insulating film and made of zirconium nitride or a zirconium nitride compound, wherein a film thickness of the first cap layer (FIG. 13 ) is equal to or less than 18.7 nm. A semiconductor device according to claim 1, further comprising: a second insulating film ( 14 . 42 ), the first cap layer ( 13 covered); a hole or trench formed in the second insulating film on the first metal pattern; and a second metal pattern buried in the hole or trench and electrically connected to the first metal pattern via the first cap layer. A semiconductor device according to claim 2, wherein a barrier metal layer ( 17 . 44a ) is formed between the second metal pattern and the first cap layer. A semiconductor device according to claim 3, wherein said barrier metal layer is formed of refractory metal nitride. A semiconductor device according to any one of claims 1 to 4, further comprising: a second capping layer ( 41 ) for covering the first cap layer ( 13 and copper diffusion-preventing insulating material different from the first cap layer. A semiconductor device according to claim 5, wherein said second cap layer is an insulating film containing silicon carbide and silicon nitride as base elements, or an insulating film containing silicon oxide carbide and silicon nitride as base elements. A semiconductor device according to claim 1, wherein said first metal pattern ( 12a . 12b ) is a copper pattern. A semiconductor device manufacturing method comprising the steps of: forming a first insulating film ( 10 ) over a semiconductor substrate; Forming a first trench or a first hole in the first insulating film; Forming a first metal pattern ( 12a . 12b by burying copper in the first trench or first hole; and forming a first cap layer ( 13 of zirconium nitride or a zirconium nitride compound on the first metal pattern and the first insulating film, wherein the first cap layer ( 13 ) is formed to have a thickness equal to or less than 18.7 nm. A semiconductor device manufacturing method according to claim 8, wherein a thermal Anneal process is applied after the first cap layer is formed. A semiconductor device manufacturing method according to claim 8, wherein said first cap layer ( 13 ) is alloyed with the first metal pattern after the first cap layer is formed. A semiconductor device manufacturing method according to claim 8, further comprising the steps of: forming a second insulating film ( 14 . 42 ) on the first cap layer ( 13 ); Forming a second trench or a second hole in the second insulating film over the first metal pattern; and forming a second metal pattern electrically connected to the first metal pattern through the first cap layer by burying copper in the second trench or the second hole. The semiconductor device manufacturing method of claim 11, further comprising the step of: forming a barrier metal layer ( 17 . 44a ) between the second metal pattern and the first cap layer. A semiconductor device manufacturing method according to claim 12, wherein said barrier metal layer is formed of refractory metal nitride. A semiconductor device manufacturing method according to claim 8, further comprising the step of: forming a second capping layer (12); 41 ) made of copper diffusion prevention insulating material different from the first cap layer on the first cap layer. A semiconductor device manufacturing method according to claim 14, wherein an insulating film containing silicon carbide and silicon nitride as base elements or an insulating film containing silicon oxide carbide and silicon oxide nitride as base elements is used as the second cap layer ( 41 ) is formed. The semiconductor device manufacturing method according to claim 8, wherein forming the first metal pattern is forming a copper pattern.

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