KR19990040756A - Metal wiring layer contact formation method of semiconductor device - Google Patents
Metal wiring layer contact formation method of semiconductor device Download PDFInfo
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- KR19990040756A KR19990040756A KR1019970061235A KR19970061235A KR19990040756A KR 19990040756 A KR19990040756 A KR 19990040756A KR 1019970061235 A KR1019970061235 A KR 1019970061235A KR 19970061235 A KR19970061235 A KR 19970061235A KR 19990040756 A KR19990040756 A KR 19990040756A
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 239000010949 copper Substances 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052802 copper Inorganic materials 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 19
- 239000010936 titanium Substances 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 229910002651 NO3 Inorganic materials 0.000 claims 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 abstract description 3
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 37
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910018565 CuAl Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자의 금속 배선층 콘택 형성 방법.A metal wiring layer contact forming method of a semiconductor device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 소자의 전도층 재료로 많이 사용되고 있는 알루미늄 합금은 소자의 고집적화에 따른 적용의 한계점으로 인하여, 높은 전도도 특성을 갖는 구리 합금으로 대체되고 있으나, 구리 합금은 반도체 소자 제조 공정 중 열처리 과정에서 쉽게 산화되는 특성이 있고, 접촉되어 있는 다른 금속들과 서로 쉽게 반응하는 성질이 있음.Aluminum alloys, which are widely used as conductive layer materials for semiconductor devices, have been replaced by copper alloys having high conductivity characteristics due to the limitations of application due to high integration of devices. However, copper alloys are easily oxidized during heat treatment during semiconductor device manufacturing processes. Character and easily reacts with other metals in contact.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
본 발명에서는 알루미늄을 사용한 제 1 배선층과 구리을 사용한 제 2 배선층의 콘택 형성시, 제 2 배선층이 형성될 부분의 하부면에 미리 장벽층을 형성함으로써, 제 1 배선층과 제 2 배선층의 직접적 접촉을 방지하며, 따라서 제 2 배선층으로 사용되는 구리의 금속 간 반응을 억제할 수 있고, 후속 열처리 공정에서 산화되는 것을 방지할 수 있음.In the present invention, in forming contact between the first wiring layer using aluminum and the second wiring layer using copper, a barrier layer is formed in advance on the lower surface of the portion where the second wiring layer is to be formed, thereby preventing direct contact between the first wiring layer and the second wiring layer. Therefore, the metal-to-metal reaction of copper used as a 2nd wiring layer can be suppressed, and can be prevented from oxidizing in a subsequent heat processing process.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 금속 배선층 형성 공정Metal wiring layer formation process of semiconductor device
Description
본 발명은 반도체 소자의 금속 배선층 콘택(contact) 형성 방법에 관한 것으로, 제 1 배선층용 알루미늄(Al)막과 제 2 배선층용 구리(Cu)막 사이에 얇은 장벽층(barrier layer)을 형성하여 두 배선층의 직접 접촉을 방지하는 금속 배선층의 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring layer contact of a semiconductor device, wherein a thin barrier layer is formed between an aluminum (Al) film for a first wiring layer and a copper (Cu) film for a second wiring layer. A method for forming a contact of a metal wiring layer to prevent direct contact of the wiring layer.
일반적으로, 반도체 소자의 전도층 재료로 많이 사용되고 있는 알루미늄 합금은 낮은 융점과 높은 비저항 등의 특성으로 인하여 초대규모 집적회로(Ultra Large Scale Integration)급 반도체 소자에서는 더 이상의 적용이 어렵게 되었다. 따라서, 대체 재료의 필요성이 대두 되었고, 그러한 재료 중의 하나가 바로 높은 전도도 특성을 갖는 구리 합금이다. 그러나 구리는 반도체 소자 제조 공정 중 열처리 과정에서 쉽게 산화되는 특성이 있으므로, 구리 박막 패턴 형성시 전면을 보호막 공정(encapsulation)으로 감싸주어야 하는 단점이 있다. 또한 구리는 다른 금속과 접촉시 서로 쉽게 반응하는 성질이 있다. 예를들어 구리가 알루미늄과 접촉하게 되면 접촉 부위가 쉽게 반응하여 CuAl2로 합성된다. 그러므로 구리 합금이 다른 금속층과의 접촉으로 쉽게 반응하는 것을 방지하기 위해서는, 구리 박막과 다른 금속층이 직접 접촉하지 못하도록 장벽층(barrier layer)을 형성시켜 주어야 한다.In general, aluminum alloys, which are widely used as conductive layer materials for semiconductor devices, are difficult to be applied to ultra large scale integration class semiconductor devices due to their low melting point and high resistivity. Thus, there is a need for alternative materials, one of which is copper alloys having high conductivity properties. However, since copper is easily oxidized during the heat treatment during the semiconductor device manufacturing process, the entire surface of the copper thin film pattern may be encapsulated. Copper also has the property of easily reacting with each other when in contact with other metals. For example, when copper comes into contact with aluminum, the contact sites readily react to form CuAl 2 . Therefore, in order to prevent the copper alloy from easily reacting by contact with another metal layer, a barrier layer should be formed so that the copper thin film and another metal layer do not directly contact each other.
본 발명은 상기한 문제점을 해결하여 소자의 전기적 특성이 우수하고 콘택 저항이 적은 금속 배선층의 콘택을 형성하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to form a contact of a metal wiring layer having excellent electrical characteristics and low contact resistance.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선층 콘택 형성 방법은, 소정의 공정을 거쳐 형성된 하부 형성막 상부 선택된 영역에 알루미늄 패턴을 형성하여 제 1 배선층을 형성하는 단계와, 상기 제 1 배선층 상부에 타이타늄막을 증착한 후, 상기 타이타늄막을 포함하는 전체 구조 상부에 절연막을 증착하고 식각하여 콘택 홀을 형성하되, 상기 제 1 배선층이 형성되어 있는 상부를 식각하여 상기 타이타늄막이 소정 두께로 남아 노출되도록 하는 단계와, 질화 공정을 진행하여 상기 콘택 홀 하부에 노출된 타이타늄막과 상기 콘택 홀 내부의 측벽 및 상부 면에 노출된 절연막을 질화시켜, 제 1 장벽층 및 제 2 장벽층을 형성시키는 단계와, 상기 제 1 장벽층 및 제 2 장벽층이 형성된 콘택 홀 내부를 포함하는 전체 구조 상부에 구리를 증착하고 패터닝하여 제 2 배선층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a metal wiring layer contact of a semiconductor device, the method including: forming a first wiring layer by forming an aluminum pattern on a region selected over a lower formation film formed through a predetermined process; 1 After depositing a titanium film on the wiring layer, the insulating film is deposited on the entire structure including the titanium film and etched to form a contact hole, but the upper part where the first wiring layer is formed is etched to leave the titanium film at a predetermined thickness. Exposing the titanium film exposed under the contact hole and the insulating film exposed on the sidewalls and the upper surface of the contact hole to form the first barrier layer and the second barrier layer. And copper on top of the entire structure including an interior of the contact hole in which the first barrier layer and the second barrier layer are formed. And depositing and patterning to form a second wiring layer.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 금속 배선층 콘택 형성 방법을 설명하기 위해 순차적으로 도시한 단면도.1 (a) to 1 (d) are cross-sectional views sequentially shown to explain a method for forming a metal wiring layer contact of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 하부 형성막 12 : 제 1 배선층11: lower formation film 12: first wiring layer
13 : 타이타늄막 13A : 제 1 장벽층용 질화타이타늄막13: titanium film 13A: titanium nitride film for first barrier layer
14 : 절연막 14A : 제 2 장벽층용 질화실리콘산화막14 Insulation Film 14A Silicon Nitride Oxide Film for Second Barrier Layer
15 : 제 2 배선층15: second wiring layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 금속 배선층 콘택 형성 방법을 설명하기 위해 순차적으로 도시한 단면도이다.1 (a) to 1 (d) are cross-sectional views sequentially illustrating a method of forming a metal wiring layer contact according to the present invention.
도 1(a)는 반도체 소자의 제조 공정 중 제 1 배선층(12)이 형성된 소자 구조의 단면도이다. 소정의 공정을 거쳐 형성된 하부 형성막(11) 상부 선택된 영역에 알루미늄 패턴을 형성하여 제 1 배선층(12)을 형성한다. 제 1 배선층(12) 상부에는 500 Å ∼ 1,500 Å 두께의 타이타늄막(13)을 증착한다. 타이타늄막(13)은 제 1 배선층(12)과 제 2 배선층의 콘택 형성시, 두 층의 직접적인 접촉을 방지하는 장벽층을 형성하기 위해 증착된다.FIG. 1A is a cross-sectional view of a device structure in which a first wiring layer 12 is formed during a manufacturing process of a semiconductor device. The first wiring layer 12 is formed by forming an aluminum pattern on a region selected above the lower formation film 11 formed through a predetermined process. A titanium film 13 having a thickness of 500 mV to 1,500 mV is deposited on the first wiring layer 12. The titanium film 13 is deposited to form a barrier layer that prevents direct contact between the two layers when forming contact between the first wiring layer 12 and the second wiring layer.
도 1(b)의 단면도는, 제 1 배선층(12) 상부에 증착된 타이타늄막(13)을 포함하는 전체 구조 상부에 절연막(14)을 증착한 후, 제 1 배선층(12)이 형성되어 있는 윗부분의 선택된 영역을 식각하여 타이타늄막(13)이 노출되도록 콘택 홀을 형성한 단면도이다. 절연막(14)은 저유전율 특성이 좋은 불화실리콘산화막(SiOF)을 사용하여 증착한다. 콘택 홀 형성시 노출되는 타이타늄막(13)은 200 Å ∼ 500 Å의 얇은 두께로 남아 있도록 제어하여 식각한다.1B is a cross-sectional view of the first wiring layer 12 after the insulating film 14 is deposited over the entire structure including the titanium film 13 deposited on the first wiring layer 12. A cross-sectional view of forming a contact hole to expose the titanium film 13 by etching the selected region of the upper portion. The insulating film 14 is deposited using a silicon fluoride oxide film (SiOF) having good low dielectric constant. The titanium film 13 exposed during the formation of the contact hole is etched by controlling the thin film to remain at a thin thickness of 200 mW to 500 mW.
위와 같은 공정으로, 노출된 부분이 매우 얇게 제어된 타이타늄막(13)은, 콘택 형성시 제 1 배선층과 상부에 형성될 제 2 배선층과의 직접 접촉을 방지하는 역할을 할 수 있는 장벽층으로 형성시키기 위하여 질화 처리한다. 질화 처리 공정은 암모니아(NH3) 가스 분위기에서 열처리를 실시하여, 암모니아 가스에 노출된 타이타늄막(13)의 타이타늄 원소와 암모니아 가스의 질소(N)가 반응하도록 한다. 따라서 노출된 타이타늄막(13)은 질화되어 제 1 장벽층용 질화타이타늄막(TiN ; 13A)으로 형성된다. 또한, 이 과정에서 절연막(14)으로 증착된 불화실리콘산화막의 일부분 즉, 암모니아 가스에 노출되는 상부 면 및 콘택 홀 내부의 측벽도 동시에 질화되어, 제 2 장벽층용 질화실리콘산화막(SiON ; 14A)이 형성된다. 도 1(c)에 제 1 장벽층용 질화타이타늄막(13A) 및 제 2 장벽층용 질화실리콘산화막(14A)이 형성된 단면도를 나타내었다.In the above process, the titanium film 13 in which the exposed portion is very thinly controlled is formed as a barrier layer that can serve to prevent direct contact between the first wiring layer and the second wiring layer to be formed thereon at the time of contact formation. Nitriding treatment to make. In the nitriding process, heat treatment is performed in an ammonia (NH 3 ) gas atmosphere so that the titanium element of the titanium film 13 exposed to the ammonia gas and nitrogen (N) in the ammonia gas react. Therefore, the exposed titanium film 13 is nitrided to form a titanium nitride film (TiN; 13A) for the first barrier layer. In this process, a part of the silicon fluoride oxide film deposited on the insulating film 14, that is, the upper surface exposed to the ammonia gas and the side wall inside the contact hole are simultaneously nitrided, so that the silicon nitride oxide film (SiON; 14A) for the second barrier layer is simultaneously formed. Is formed. 1C is a cross-sectional view in which the titanium nitride film 13A for the first barrier layer and the silicon nitride oxide film 14A for the second barrier layer are formed.
도 1(d)와 같이 콘택 홀 내부를 포함한 제 2 장벽층용 질화실리콘산화막(14A) 상부에 구리를 증착하고 패터닝하여 제 2 배선층(15)을 형성한다. 제 2 장벽층용 질화실리콘산화막(14A)은 내 산화 특성이 매우 우수하여, 제 2 배선층(15)으로 사용한 구리가 쉽게 산화되는 것을 방지할 수 있다. 또한 제 1 장벽층용 질화타이타늄막(13A)은 제 2 배선층(15)의 구리가 제 1 배선층(12)의 알루미늄과 직접 접촉하여 반응하는 것을 방지하여 준다. 따라서 결과적으로 높은 전도도 특성을 갖는 구리를 금속 배선으로 사용함에 있어서, 위와 같이 구리막에 장벽층을 형성하여 원활한 금속 배선 콘택을 형성할 수 있다.As illustrated in FIG. 1D, copper is deposited and patterned on the silicon nitride oxide film 14A for the second barrier layer including the inside of the contact hole to form the second wiring layer 15. The silicon nitride oxide film 14A for the second barrier layer is very excellent in oxidation resistance and can prevent the copper used as the second wiring layer 15 from being easily oxidized. Further, the titanium nitride film 13A for the first barrier layer prevents the copper of the second wiring layer 15 from directly reacting with the aluminum of the first wiring layer 12. As a result, in using copper having high conductivity as a metal wiring, a barrier layer may be formed on the copper film as described above to form a smooth metal wiring contact.
상술한 바와 같이 본 발명에 의하면, 초대규모 집적회로(ULSI)급 이상의 반도체 소자 제조시, 전도층 재료로 전도도 특성이 좋은 구리를 사용하면서도, 구리가 갖는 쉽게 산화되거나 접촉되는 다른 금속과 쉽게 반응하는 단점을 극복할 수 있다. 또한 질화 처리만으로 구리막을 보호할 수 있는 장벽층을 형성할 수 있어 제조 공정을 단순화 할 수 있다. 따라서 콘택 저항이 적어 소자의 전기적 특성이 향상되고, 소자 간의 금속 배선 연결을 원활히 할 수 있어 신뢰성이 향상된 소자를 제조할 수 있는 효과가 있다.As described above, according to the present invention, in the manufacture of ultra-large scale integrated circuit (ULSI) or more semiconductor devices, copper having good conductivity characteristics as a conductive layer material, while easily reacting with other metals that are easily oxidized or contacted with copper, is used. You can overcome the disadvantages. In addition, only a nitriding treatment can form a barrier layer that can protect the copper film, thereby simplifying the manufacturing process. Therefore, the electrical resistance of the device is improved due to the low contact resistance, and the metal wires can be smoothly connected between the devices, thereby improving the reliability of the device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019970061235A KR19990040756A (en) | 1997-11-19 | 1997-11-19 | Metal wiring layer contact formation method of semiconductor device |
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| KR1019970061235A KR19990040756A (en) | 1997-11-19 | 1997-11-19 | Metal wiring layer contact formation method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325303B1 (en) * | 1999-06-16 | 2002-02-21 | 김영환 | Metalline of semiconductor device and method for fabricating the same |
| KR100621228B1 (en) * | 2000-12-26 | 2006-09-13 | 매그나칩 반도체 유한회사 | Manufacturing method of wiring and wiring connection part of semiconductor device |
| KR100758886B1 (en) * | 2001-04-27 | 2007-09-19 | 후지쯔 가부시끼가이샤 | Semiconductor device and method of manufacturing the same |
-
1997
- 1997-11-19 KR KR1019970061235A patent/KR19990040756A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100325303B1 (en) * | 1999-06-16 | 2002-02-21 | 김영환 | Metalline of semiconductor device and method for fabricating the same |
| KR100621228B1 (en) * | 2000-12-26 | 2006-09-13 | 매그나칩 반도체 유한회사 | Manufacturing method of wiring and wiring connection part of semiconductor device |
| KR100758886B1 (en) * | 2001-04-27 | 2007-09-19 | 후지쯔 가부시끼가이샤 | Semiconductor device and method of manufacturing the same |
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