DE102021205550A1 - Method and device for determining at least one state variable of an intermediate circuit capacitor of an inverter and for operating an inverter - Google Patents

Abstract

The invention relates to a method for determining at least one state variable of an intermediate circuit capacitor (15) of an inverter (15), with an input current (i0) being detected at high frequency in an intermediate circuit, with output currents (ia, ib, ic) at the outputs of half bridges (A, B, C) of the inverter (10) are detected at high frequency, with a capacitor current (iZK) being determined and provided as a state variable of the intermediate circuit capacitor (15) based on the detected input current (i0) and the detected output currents (ia, ib, ic). The invention also relates to a method for operating an inverter (10) and associated devices (1, 50).

Description

The invention relates to a method and a device for determining at least one state variable of an intermediate circuit capacitor of an inverter. Furthermore, the invention relates to a method and a device for operating an inverter.

In a pulse-controlled inverter, for example a three-phase two-level inverter, with a DC voltage intermediate circuit, harmonics with regard to the current and voltage of the intermediate circuit capacitor depend on a switching frequency (which can also be referred to as clock frequency) of the pulse duration modulation. The harmonics decrease in this case, approximately linearly, with an increasing switching frequency. With regard to its loss mechanisms, the intermediate circuit capacitor can be modeled by an effectively effective series resistance. An intermediate circuit current has no mean value and is overlaid with harmonics. In order to determine the power loss in the intermediate circuit capacitor, a capacitor effective current value must be formed. Among other things, this provides for a squaring of the current curve over time, which makes it clear that large amplitudes of the harmonics produce significant losses. With increasing switching frequency of the pulse-controlled inverter, the harmonic losses of the intermediate circuit capacitor and thus its heating decrease.

With an increase in the switching frequency, however, the switching losses of clocked power semiconductors of the pulse-controlled inverter increase, approximately linearly. Power semiconductors in silicon carbide technology (SiC) have recently become available, which have the following advantageous properties: The power semiconductors can implement significantly faster switching processes (-100 kHz) and thus generate lower switching losses. A significantly higher switching frequency can thus be selected for the same average power loss. The power semiconductors also withstand (compared to Si-MOSFETs or IGBTs (~175°C)) significantly higher internal junction temperatures (~300°C). A larger internal junction temperature enables a larger temperature gradient compared to the outside temperature/a cooling system, which simplifies and improves the dissipation of a larger power loss.

Since the SiC power semiconductors tolerate a higher junction temperature, there is the possibility of a greater overload/overload capacity of the pulse-controlled inverter. The disadvantage here, however, is that the intermediate circuit capacitor simultaneously heats up via the effective value of the capacitor current, but does not tolerate a significantly higher temperature compared to the SiC power semiconductors. With SiC inverters, the intermediate circuit capacitor is a weak point due to the lower temperature tolerance. The effective value of the capacitor current cannot be measured directly, since the introduction of an inductive measuring device in series with the intermediate circuit capacitor leads to negative resonance properties in the intermediate circuit.

From B. Weber, T. Brandt and A. Mertens, Compensation of switching dead-time effects in voltage-fed PWM inverters using FPGA-based current oversampling, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, USA, 2016, pp. 3172-3179, doi: 10.1109/APEC.2016.7468318, a method for dead time compensation is known.

The invention is based on the object of creating a method and a device for determining at least one state variable of an intermediate circuit capacitor of an inverter.

The object is achieved according to the invention by a method having the features of patent claim 1 and a device having the features of patent claim 9 . Advantageous configurations of the invention result from the dependent claims.

In particular, a method for determining at least one state variable of an intermediate circuit capacitor of an inverter is provided, with an input current at an intermediate circuit being detected at high frequency, with output currents at outputs of half bridges of the inverter being detected at high frequency, with a capacitor current as a state variable of the intermediate circuit capacitor based on the detected Input current and the detected output currents is determined and made available.

Furthermore, in particular a device for determining at least one state variable of an intermediate circuit capacitor of an inverter is created, comprising a control device, wherein the control device is set up to receive an input current detected at high frequency in an intermediate circuit, to receive output currents detected at high frequency at outputs of half bridges of the inverter, and to determine and provide a capacitor current as a state variable of the intermediate circuit capacitor based on the detected input current and the detected output currents.

The method and the device make it possible to determine at least one state variable of the intermediate circuit capacitor. This is done by detecting an input current of an intermediate circuit at high frequency. The input current is in particular a current that is supplied to the intermediate circuit from outside, in particular from an electrical energy source. Furthermore, output currents from half-bridges are recorded at high frequency. In this case, the output currents serve in particular to feed an electrical machine. The high-frequency detection of the currents means in particular that the currents are detected oversampled. In particular, this means that a sampling frequency is significantly greater than a modulation frequency of the inverter, in particular greater by a factor of 10, 100 or 1000.

The inverter is designed in particular as a pulse-controlled inverter. For example, the inverter can be a three-phase two-level inverter. In principle, however, other topologies are also possible. The inverter is used in particular as a drive converter for feeding an electrical machine.

The currents are recorded and provided in particular by means of a sensor system suitable for this purpose, in particular by means of current sensors on the intermediate circuit or on the outputs or strands of the half-bridges. The output currents recorded with high resolution can be used in particular to generate values of the output currents or phase currents that are equivalent to a center-synchronous sampling. As a result of the high-resolution detection, noise in the equivalent values in particular can be filtered out in an improved manner, so that in particular a signal-to-noise ratio can be improved.

Only one intermediate circuit capacitor is always mentioned in this disclosure. In principle, however, it can also be provided that the intermediate circuit comprises a plurality of intermediate circuit capacitors. The respective explanations then apply analogously.

The control device can be designed individually or combined as a combination of hardware and software, for example as program code that is executed on a microcontroller or microprocessor. However, it can also be provided that parts are designed individually or combined as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). In particular, the control device comprises at least one computing device and at least one memory.

In particular, it is provided that the high-frequency detected, in particular oversampled, currents, and possibly also other variables, are evaluated by means of a field-programmable gate array (FPGA). A field-programmable gate array enables high-frequency signal acquisition and signal processing. In this case, high-frequency should mean in particular that an associated frequency range is above a modulation frequency of a pulse duration modulation of the pulse-controlled inverter. In particular, high-frequency denotes a frequency that is higher by a factor of 10, preferably by a factor of 100, particularly preferably by a factor of 1000, compared to the modulation frequency. If a modulation frequency is 20 kHz, for example, then a frequency of the signal detection and signal processing of the field-programmable gate array is 1 MHz, for example. Due to the parallel signal processing of a field-programmable gate array, this can advantageously process high-frequency (in particular -MHz) sampled quantities. Due to the high-frequency sampling, sampling or aliasing effects can be reduced as disturbance variables in the signal. Any noise components of the sensors can be digitally filtered in the field-programmable gate array, so that a very high signal-to-noise ratio can be provided for further digital processing. In comparison, a microcontroller (e.g. DSP) is significantly less suitable for processing high-frequency signals, since the recorded values of the DSP have to be transported and processed by the internal analog-to-digital converter (ADC) to the processor core, which leads to propagation delay-related and delays in evaluation due to preprocessing. With a field-programmable gate array, the sensed values of the ADC are instead available to the logic units immediately, that is, in real time. Inexpensive ADCs that can generate a high-frequency digital data stream (bit stream), e.g. delta-sigma converters, can also be evaluated with field-programmable gate arrays without further measures. In particular, the field-programmable gate array is part of a system-on-chip (SoC).

The field-programmable gate array can in particular be a field-programmable gate array that can be partially (ie partially) reconfigured at runtime. As a result, the field-programmable gate array can be updated in particular. The reconfiguration takes place in particular by way of partial reconfiguration, in which only part of the gate array is reconfigured or reprogrammed at runtime, but other parts of the gate array retain their respective configuration or programming. The reconfiguration is carried out in particular by means of a configuration control which carries out and monitors the reconfiguration. the Configuration control may be provided by a DSP or the device controller. Methods for automatic code generation can be used to reconfigure the at least one field-programmable gate field, such as the “Xilinx System Generator for DSP”, which can automatically carry out both source code modeling and a functional analysis. For example, the "System Generator for DSP" enables the modeling of FPGA functions in a Matlab Simulink environment so that the properties can be tested against other Simulink function blocks. The automatic code generation ensures that the field-programmable gate array behaves identically to Simulink modeling. A configuration of a field-programmable gate array includes, in particular, instructions with which the field-programmable gate array can be programmed in such a way that a specific functionality for data processing can be provided using the programmed (or configured or reconfigured) part of the field-programmable gate array. In the present case, such a functionality includes in particular the implementation of measures of the methods described in this disclosure.

In particular, it is provided that dead time effects occurring in the inverter due to switching delay times are compensated for by means of dead time compensation. This is done in particular by means of the control device, in particular by means of at least one field-programmable gate field of the control device. Dead time compensation attempts to compensate for a dead time effect. The dead time effect occurs because there is a mapping error between an estimated current voltage and a real voltage due to the switching times of power semiconductors in the pulse-controlled inverter. To compensate for the dead time effect, switching edges of power semiconductors are adjusted, that is, shifted in terms of a switching time. As a result, current output or phase voltages that are actually present can be precisely determined, in particular estimated, taking into account the high-frequency detected output or phase currents. The dead-time compensation is performed, for example, using the method described in B. Weber, T. Brandt and A. Mertens, Compensation of switching dead-time effects in voltage-fed PWM inverters using FPGA-based current oversampling, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC) , Long Beach, CA, USA, 2016, pp. 3172-3179, doi: 10.1109/APEC.2016.7468318.

As part of the method, the capacitor current i _ZK can be determined in particular as follows (cf. also 2 ). In this case, the determination takes place, in particular, taking into account the current switching states of the inverter. With the switching states of the inverter: _sa → [-1,1] switching state of the half-bridge A, s _b → [-1.11 switching state of the half-bridge B, _sc →[-1,1] switching state of the half-bridge C, and the high-frequency, in particular oversampled, output currents i _a , _ib , _ic (phase currents) of the half bridges, the result for a current i ₁ from the intermediate circuit to the half bridges is: $$i_1=s_a{i}_a+s_b{i}_b+s_c{i}_c$$

woraus sich der gesuchte Kondensatorstrom i_ZK ergibt: $$i_{ZK}=i_1-i_0$$

With the input current i ₀ recorded at high frequency, the node rule then yields: $$i_1=i_0+i_{ZK}$$

from which the required capacitor current i _ZK results: $$i_{ZK}=i_1-i_0$$

With the help of the known switching states of the half-bridges, the capacitor current can therefore be determined as a state variable from the detected input current and the detected output currents at any point in time t.

In one embodiment, it is provided that, starting from the determined capacitor current of the intermediate circuit capacitor, an effective capacitor current value is determined and provided as a state variable. In particular, the effective current value of the capacitor can be determined in relation to a modulation period of the inverter with the period duration T. The capacitor effective current value i _ZK,eff is then: $$i_{ZK,eff}=\sqrt{\frac{1}{T}{\displaystyle \underset{0}{\overset{T}{\int }}{i}_{ZK}^2\left(t\right)\mathrm{i.e}t}}$$

In principle, it is also possible to average over several modulation periods.

One specific embodiment provides for an intermediate circuit voltage to be detected at high frequency, with an effective series resistance of the intermediate circuit capacitor being determined and provided as a state variable based on the determined capacitor current and the detected intermediate circuit voltage. This allows a measure of a power loss in the intermediate circuit capacitor can be determined or estimated. The series resistance results with the detected intermediate circuit voltage u _ZK and the determined capacitor current i _ZK (for a point in time t) in particular: $$R_S=\frac{\mathrm{i.e}{\mathrm{and}}_{ZK}}{\mathrm{i.e}{i}_{ZK}}$$

The intermediate circuit voltage is recorded in particular by means of a voltage sensor system suitable for this purpose.

In one specific embodiment, it is provided that a power loss of the intermediate circuit capacitor is determined and provided as a state variable, based on the determined capacitor effective current value. As a result, a power loss occurring at the intermediate circuit capacitor can be determined or estimated directly. The power loss P _Verl is determined as follows, in particular taking into account the specific series resistance of the intermediate circuit capacitor: $$P_{Ve\mathrm{right}l}=R_s{i}_{ZK,eƒƒ}^2$$

As an alternative to this, the power loss P _Verl (for a point in time t) can also be determined as follows: $$P_{Ve\mathrm{right}l}=R_s{i}_{\mathrm{<figure-callout\; id="2"\; label="Z\; K"\; filenames="DE102021205550A1\_0008.png"\; state="\{\{state\}\}">Z</figure-callout>}K}^2$$

In one specific embodiment, it is provided that a temperature of the intermediate circuit capacitor is determined and provided as a state variable, based on the determined effective series resistance. As a result, a temperature of the intermediate circuit capacitor can be determined and made available, so that it can be monitored, for example, whether the intermediate circuit capacitor is being operated below a temperature threshold value or not. The temperature can be determined, for example, with the aid of an empirically determined and/or simulated characteristic curve, in which values for the series resistance of the intermediate circuit capacitor linked to temperature values are stored.

Further features for the configuration of the device result from the description of configurations of the method. The advantages of the device are in each case the same as in the embodiments of the method.

Furthermore, in particular a method for operating an inverter is also provided, with a method being carried out according to one of the previously described embodiments, with an operating strategy of the inverter being selected and/or adapted taking into account the determined at least one state variable. As a result, an operating mode of the inverter can be changed, in particular controlled or regulated, based on the at least one state variable of the intermediate circuit capacitor. As a result, operation of the inverter can be improved, in particular with regard to efficiency and overload capacity.

In particular, a device for operating an inverter is also created, comprising a device according to one of the embodiments described above, the control device also being set up to select and/or adapt an operating strategy of the inverter taking into account the determined at least one state variable.

In a further development of the method for operating the inverter, it is provided that a switching frequency of the inverter is selected taking into account the determined power loss. If a power loss increases, then a switching frequency is increased in particular, as a result of which the power loss can be reduced.

In a further development of the method for operating the inverter, it is provided that the switching frequency of the inverter is selected such that a total power loss from a switching power loss of power semiconductors of the inverter and the determined power loss of the intermediate circuit capacitor is or is minimized. Since the dependencies on the switching frequency for the power loss of the power semiconductors and the intermediate circuit capacitor are opposite, a total power loss is determined. A minimum of the total power loss can then be achieved by changing the switching frequency.

• 1 eine schematische Darstellung einer Ausführungsform der Vorrichtung zum Bestimmen mindestens einer Zustandsgröße eines Zwischenkreiskondensators eines Wechselrichters;
• 2 eine schematische Darstellung zur Verdeutlichung der Ausführungsform der Vorrichtung aus 1;
• 3 eine schematische Darstellung zur Verdeutlichung einer Ausführungsform eines Verfahrens und einer Vorrichtung zum Betreiben des Wechselrichters;
• 4 ein schematisches Ablaufdiagramm zur Verdeutlichung von Ausführungsformen der in dieser Offenbarung beschriebenen Verfahren.

The invention is explained in more detail below on the basis of preferred exemplary embodiments with reference to the figures. Here show:

• 1 a schematic representation of an embodiment of the device for determining at least one state variable of an intermediate circuit capacitor of an inverter;
• 2 a schematic representation to clarify the embodiment of the device 1 ;
• 3 a schematic representation to illustrate an embodiment of a Ver driving and a device for operating the inverter;
• 4 a schematic flowchart to illustrate embodiments of the methods described in this disclosure.

In 1 a schematic representation of an embodiment of the device 1 for determining at least one state variable of an intermediate circuit capacitor of an inverter 10 is shown. The device 1 includes a control device 2. In the embodiment shown, the control device 2 includes a digital signal processor 3 and a field-programmable gate array 4. In principle, the control device 2 can alternatively or additionally also include other types of computing devices, for example an ASIC. The field-programmable gate field 4 allows high-frequency signal processing and signal evaluation. The digital signal processor 3 and the field-programmable gate array 4 are designed in particular as a system-on-chip (SoC). The device 1 executes the methods described in this disclosure, which are explained below with reference to the device 1 .

The field-programmable gate array 4 comprises a number of modules 4-x which perform different functions, as will be explained below.

Also shown is an inverter 10, which is designed as a three-phase two-level inverter in the example, and a sensor system 12. The sensor system 12 includes current sensors 12-1, 12-2, 12-3, 12-4 and an analog-to-digital converter 12- 5. The sensor system 12 can also be part of the device 1 .

An electrical machine 20 is also shown, which is fed by the pulse-controlled inverter 10 via three strands 11-1, 11-2, 11-3. For feeding, the pulse-controlled inverter 10 generates a rotary field in a manner known per se and is controlled for this purpose by the module 4-1. In particular, the module 4-1 provides modulation control.

The input current i ₀ and the output currents i _a , _ib , _ic of half-bridges of the inverter 10 are detected at high frequency by the sensor system 12 , received by the control device 2 and processed by the module 4 - 2 . In particular, the input current i ₀ and the output currents i _a , _ib , _ic are oversampled with a sampling frequency that is a factor of 10, 100 or even 1000 above a modulation frequency of the pulse-controlled inverter 10 .

To illustrate the currents i ₀ , i _a , _ib , _ic is in the 2 a schematic circuit diagram of the inverter 10 shown, it being assumed that the intermediate circuit capacitor 15 in the in 1 shown inverter 10 is integrated. In this case, the intermediate circuit capacitor 15 is modeled in particular in the form of an intermediate circuit capacitance CZK and a series resistance R _s connected in series with it. The input current i ₀ is recorded at high frequency. The inverter 10 includes three half-bridges A, B, C, whose output currents i _a , i _b , i _c are also detected at high frequency.

Based on the high-frequency detected input current i ₀ and the high-frequency detected output currents i _a , _ib , _ic, the control device 2 determines a capacitor current i _ZK as a state variable of the intermediate circuit capacitor 15 and makes it available. The capacitor current i _ZK can be determined, for example, using the module 4-2 ( 1 ) be performed.

It can be provided that, based on the determined capacitor current i _ZK of the intermediate circuit capacitor 15, a capacitor effective current value i _ZK,eff is determined and provided as a state variable.

It can be provided that an intermediate circuit voltage u _ZK ( 2 ) is detected at high frequency, based on the determined capacitor current i _ZK and the detected intermediate circuit voltage u _ZK an effective series resistance R _S of the intermediate circuit capacitor 15 is determined as a state variable and provided.

Provision can be made for a power loss P _Verl of the intermediate circuit capacitor 15 to be determined and provided as a state variable based on the determined capacitor effective current value i _ZK,eff .

Provision can be made for a temperature T _ZK of the intermediate circuit capacitor 15 to be determined and provided as a state variable, based on the determined effective series resistance R _S . This can be done, for example, in a module 3-1 of the digital signal processor 3, using a characteristic curve 25 generated empirically and/or by simulation, in which values of the effective series resistance R _S linked to values of the temperature T _ZK of the intermediate circuit capacitor 15 are stored . The values are then retrieved from characteristic curve 25 as required.

In the 1 an embodiment of the device 50 for operating an inverter 10 is also shown. The device 50 includes the device 1 for determining at least one state variable of an intermediate circuit capacitor 15 of an inverter 10. The control device 2 is also set up to an operating strategy of the inverter 10 taking into account to select and/or adapt a certain at least one state variable. This takes place, for example, in a module 4-3, in which an operating strategy is adapted on the basis of the determined at least one state variable, so that a modulation control of the inverter 10 provided by the module 4-1 is adapted.

Provision can be made for a switching frequency f ( 3 ) of the inverter 10 is selected taking into account the specific power loss P _Verl .

In particular, it can be provided that the switching frequency f ( 3 ) of the inverter 10 is selected such that a total power loss 32 from a switching power loss 30 of power semiconductors of the inverter 10 and the specific power loss P _Verl of the intermediate circuit capacitor 15 is minimized or is minimized.

This is shown schematically in the 3 clarified. Simplified curves of a switching power loss 30 of the power semiconductors and a power loss P _Verl of the intermediate circuit capacitor are shown. The losses of the intermediate circuit capacitor are, in particular, harmonic losses. The total power loss 32 can be determined from these curves 30, 31, by means of which that switching frequency f can be determined at which the total power loss 32 is minimized. This switching frequency f is used, for example, by the module 4-3 ( 1 ) identified and transferred to the module 4-1 for driving the inverter 10. The module 4-1 then controls the power semiconductors of the inverter 10 with the changed switching frequency f.

In the 4 a schematic flow chart is shown to clarify embodiments of the method for determining at least one state variable of an intermediate circuit capacitor of an inverter.

In a measure 100a, an input current in an intermediate circuit is detected at high frequency.

In a measure 100b, output currents at outputs of half bridges of the inverter are detected at high frequency.

In a measure 101, a capacitor current is determined and made available as a state variable of the intermediate circuit capacitor based on the detected input current and the detected output currents.

It can be provided that in a measure 102 based on the determined capacitor current of the intermediate circuit capacitor, a capacitor effective current value is determined and provided as a state variable.

Provision can also be made for an intermediate circuit voltage to be detected at high frequency in a measure 100c, with an effective series resistance of the intermediate circuit capacitor being determined and provided as a state variable in a measure 103 based on the determined capacitor current and the detected intermediate circuit voltage.

In a further development, provision can be made for a power loss of the intermediate circuit capacitor to be determined and provided as a state variable in a measure 104 based on the determined effective capacitor current value.

Likewise in a further development, provision can be made for a temperature of the intermediate circuit capacitor to be determined and provided as a state variable in a measure 105 based on the determined effective series resistance.

Provision can be made for an operating strategy of the inverter to be selected and/or adapted in a measure 106 taking into account the at least one state variable determined. This provides a method for operating an inverter.

It can be provided in measure 106 that a switching frequency of the inverter is selected for this, taking into account the determined power loss.

In a further development, measure 106 can provide for the switching frequency of the inverter to be selected in such a way that a total power loss from a switching power loss of switching elements of the inverter and the determined power loss of the intermediate circuit capacitor is or is minimized.

Provision can in particular be made for the method or methods to be carried out repeatedly, so that the at least one state variable is continuously determined and/or the operating strategy of the inverter is continuously selected and/or adapted taking into account the determined at least one state variable.

Reference List

1

contraption

2

control device

3

Digital signal processor

3-1

module

4

field-programmable gate array

4x

module

10

inverter

11-x

strand

12

sensors

12-x

current sensor

12-5

Analog to digital converter

15

intermediate circuit capacitor

20

electric machine

25

curve

30

Switching power loss of the power semiconductors

32

total power dissipation

50

Device (to operate the inverter)

100-106

Measures of the procedures

A, B, C

half bridge

CZK

intermediate circuit capacity

f

switching frequency

i0

input current

ia, ib, ic

output current

iZK

capacitor current

iZK,eff

Capacitor RMS Current Value

P

perfomance

Pexit

Power loss of the intermediate circuit capacitor

RS

series resistance

TZK

temperature (intermediate circuit capacitor)

uZK

intermediate circuit voltage

Claims (10)

Method for determining at least one state variable of an intermediate circuit capacitor (15) of an inverter (15), with an input current (i ₀ ) being detected at high frequency in an intermediate circuit, with output currents (i _a , _ib , _ic ) at outputs of half bridges (A, B, C) of the inverter (10) are detected at high frequency, with a capacitor current (i _ZK ) as a state variable of the intermediate circuit capacitor (15) based on the detected input current (i ₀ ) and the detected output currents (i _a , _ib , _ic ) determined and provided. procedure after claim 1 , characterized in that starting from the determined capacitor current (i _ZK ) of the intermediate circuit capacitor (15), a capacitor effective current value (i _ZK,eff ) is determined and provided as a state variable. procedure after claim 1 or 2 , characterized in that an intermediate circuit voltage (u _ZK ) is detected at high frequency, an effective series resistance (R _{S )} of the intermediate circuit capacitor (15) being determined and provided as a state variable based on the determined capacitor current (i _ZK ) and the detected intermediate circuit voltage (u ZK ). becomes. procedure after claim 2 or 3 , characterized in that , starting from the determined effective capacitor current value (i _ZK,eff ), a power loss (P _Verl ) of the intermediate circuit capacitor (15) is determined and provided as a state variable. procedure after claim 3 or 4 , characterized in that , starting from the determined effective series resistance (R _S ), a temperature (T _ZK ) of the intermediate circuit capacitor (15) is determined and provided as a state variable. A method for operating an inverter (10), wherein a method according to any one of Claims 1 until 5 is carried out, with an operating strategy of the inverter (10) being selected and/or adapted taking into account the at least one state variable determined. procedure after claim 6 , characterized in that for this purpose a switching frequency (f) of the inverter (10) is selected taking into account the specific power loss (P _Verl ). procedure after claim 7 , characterized in that the switching frequency (f) of the inverter (10) is selected in such a way that a total power loss (32) from a switching power loss (30) of power semiconductors of the inverter (10) and the determined power loss (P _Verl ) of the intermediate circuit capacitor (15 ) is or will be minimized. Device (1) for determining at least one state variable of an intermediate circuit capacitor (15) of an inverter (10), comprising a control device (2), the control device (2) being set up to receive an input current (i ₀ ) detected at high frequency in an intermediate circuit , high frequency to receive output currents (i _a , ib , ic ) detected at outputs of half-bridges (A, _B , _C ) of the inverter (10), and a capacitor current (i _ZK ) as a state variable of the intermediate circuit capacitor (15) based on the detected input current (i ₀ ) and the detected output currents ( _ia , _ib , _ic ) to determine and provide. Device (50) for operating an inverter (10), comprising a device (1) according to claim 9 , wherein the control device (2) is further set up to select and / or adapt an operating strategy of the inverter (10) taking into account the determined at least one state variable.

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