DE10046302B4 - Method of forming a deep trench capacitor - Google Patents

Abstract

A method of forming a deep trench capacitor (501) in a semiconductor substrate (303) and an active region (AA; 801) for semiconductor active devices, the method comprising:
Forming the deep trench capacitor (501) in the semiconductor substrate (303) having an edge oxide (903) on which a conductive polysilicon layer (907) is disposed,
Patterning and etching the active region formation device (AA; 801), wherein at least a portion of the active region (AA; 801) overlaps with the deep trench capacitor (501);
Wet etching of the deep trench capacitor (501) and the active region (AA; 801), such that remnants of the polysilicon layer (907) located above the edge oxide (903) are removed.

Description

Territory of invention

The The present invention relates to a method for compensating the Misalignment of a photolithography step in etching a active area over a deep trench capacitor in a memory array.

background the invention

Recently, dynamic random access memory (DRAM) has increased the density of DRAM integrated circuits. A DRAM cell typically consists of a storage capacity and an access transistor. One type of storage capacitor is the trench capacitor (compare, for example DE 40 38 115 A1 ), wherein a capacitor is formed in a trench etched in a silicon semiconductor substrate. Typically, the access transistor is formed adjacent to the trench memory capacitor. The access transistor is formed on an active region (AA).

In the US 5,874,758 A method for making DRAM cells of reduced size is disclosed.

The active areas in a DRAM array, such as from the US 5,874,758 are known, by oxide insulation, for example by shallow trench isolation (STI), separated. Since the size of the trench capacitors and the access transistors decreases due to the high integration, the adjustment of the active region relative to the deep trenches formed in the semiconductor substrate is critical. There inevitably occurs a certain amount of misalignment. The result of this misalignment can be found in the 1 and 2 to be viewed as. 1 Figure 4 shows both a top view and a cross-section of a correctly aligned active area over a deep trench capacitor. 2 indicates the problems when a misalignment occurs.

In particular, the upper area of the shows 1 a plan view of a DRAM memory array 101 , The storage array 101 includes trench capacitors 103 formed in the semiconductor substrate. Active areas 105a - 105c surround the trench capacitors 103 , Typically this is an active area 105 with two trench capacitors 103a - 103b connected. As in the lower part of the 1 can be seen, a cross section along the line 1-1 'is shown. The trench capacitor 103 extends down into the substrate and includes an edge oxide 107 , which serves for electrical isolation of the trench capacitor. Inside the trench capacitor 103 a polysilicon stack layer is formed, which comprises at least a first polysilicon layer, a dielectric layer and a second polysilicon layer. This forms the capacitor in the trench. Part of the active area 105a extends across the trench capacitor and is used to make contact with the upper node of the trench capacitor. Therefore, this is in the cross-sectional view 1 shown active area 105a constructed of polysilicon. In particular, it should be noted that the active areas 105b and 105c from the active area 105a through the oxide layer 107 are electrically isolated. Further isolation is provided by the shallow trench isolation structure that exists between the active areas 105a . 105b and 105c is formed.

2 shows a lateral misalignment of the active areas 205a - 205c relative to the position of the trench capacitors 203 , In particular, the upper area of the shows 2 in that the active areas are shifted to the left, thereby causing the active area 205c at least with some of the trench capacitors 203 overlaps. The cross-sectional view along the section line 2-2 'in 2 shows the effect of misalignment. Because of this misalignment is part of the active area 205c in electrical contact with the trench capacitors 203 , This electrical short circuit is in 2 as the area 207 shown. As can be easily understood, this is an electrical short between active areas 205a and trench capacitors 203 undesirable.

Of the The invention is therefore based on the object, this short circuit to avoid.

These The object is achieved by the method according to claim 1.

SHORT DESCRIPTION THE DRAWINGS

1 FIG. 10 is a plan view and cross-sectional view of a DRAM cell having suitably adjusted active areas and trench areas. FIG.

2 FIG. 10 is a plan view and a cross-sectional view of a DRAM cell having misaligned active regions and trench regions. FIG.

3 - 11 show the steps to compensate for lateral misalignment of the active areas over the trench areas according to the present invention.

12 Fig. 10 shows the increase of the buried stripe length for compensating for the wet etching step of the present invention.

DETAILED DESCRIPTION

In the 3 - 7 For example, there is shown a method of enhancing active area settling over a deep trench capacitor for a DRAM memory array. In particular, as in 3 you can see a deep ditch 301 in a semiconductor substrate 303 educated. For simplicity's sake, it's just a single trench 301 shown. However, those skilled in the art will readily recognize that typically millions of substantially equal trenches 301 in the substrate 303 during the manufacture of a DRAM memory array. The upper area of 3 shows a plan view of the trench 301 and the lower part of the 3 shows a cross-sectional view along the line 3-3 '.

Next will be in 4 a layer of arsenic-doped quartz glass (ASG) 401 along the inside of the trench 301 deposited. The deposition process of the ASG layer 401 can be carried out by chemical vapor deposition (CVD). Preferably, the thickness of the ASG layer is 401 300-500 Å.

Next is a layer of photoresist in the trench 301 and over the ASG layer 401 deposited. The photoresist is from the top of the trench 301 offset down to a desired height of the ASG layer 401 within the trench. The part of the ASG layer 401 which is not covered by the photoresist is removed. The result is an ASG layer 401 within the trench 301 However, they are not on the top of the trench 301 extends. Next, the photoresist is removed. The result can be in 5 to be viewed as.

Next will be in 6 a cover layer of tetraethyl orthosilicate oxide (TEOS) 551 formed and over the ASG layer 401 deposited. The purpose of the TEOS cover is to prevent the outdiffusion of the arsenic in the area not covered by ASG in the next baking step.

Subsequently, a baking step with the ASG layer 401 carried out to drive the arsenic in the substrate to a buried plate 553 to build. The buried plate 553 is used as the lower storage node of the trench capacitor. After the annealing step, the TEOS oxide 551 and the ASG layer 401 removed using a wet etch process. This will make the buried plate 553 exposed in the substrate.

Next will be in 7 a nitride layer (not shown) deposited over the buried plate and in the trench. Oxidation of the nitride is performed to form a nitride / oxide (NO) layer. The oxidation can be achieved using thermal oxidation. According to 7 the trench is then doped with polysilicon 753 filled. The species-doped polysilicon 753 is deposited using conventional CVD techniques.

Next, the polysilicon layer 753 and then polished using a chemical mechanical planarization (CMP) process to ensure that the polysilicon layer 753 just inside the trench. The nitride / oxide layer, not from the polysilicon layer 753 is then removed using conventional etching steps. The result can be in 8th to be viewed as.

Next will be in 9 a part of the polysilicon layer 753 ablated to a predetermined depth, and then a second layer of TEOS oxide 901 deposited an edge oxide 903 to build. The edge oxide 903 is then etched to remove the horizontal area for forming the final sidewall. It becomes a second polysilicon layer 905 deposited, followed by CMP treatment of the polysilicon layer. Part of the second polysilicon layer 905 is then removed to a predetermined depth, and the area of the Randoxids 903 not from the second polysilicon layer 905 is covered by immersion in BHF (buffer HF). It becomes a third polysilicon layer 907 deposited and then withdrawn by about 50 nm.

Next will be in 10 the active area etching performed. The active area etch is used to define those areas of the DRAM memory cell that will contain active semiconductor elements. In other words, those areas that are not protected during the active area etching will have isolation areas formed thereon. Thus, in the preferred embodiment, shallow trench isolations (STI) are formed between the active regions (AA). As in 10 can be seen exists due to misalignment between the mask pattern for the active area and the trenches 301 a polysilicon residue between the trench capacitor 501 and an adjacent active area. This rest is in area 601 marked. The in the 3 - 10 The process described is generally in accordance with the prior art and results in faulty components due to the short circuit in the field 601 ,

According to the present invention and as in 11 5, a wet etching step is performed for 5-20 minutes to remove the polysilicon residue in the region 601 to remove. The wet etching should be one have high selectivity between silicon and doped polysilicon. This results in the doped polysilicon within the trench capacitor 501 is removed while having a small effect on the silicon substrate of the wafer 303 in active areas. A suitable candidate is ethylene glycol. Alternatively, a solution of NH ₄ OH may be used as the etchant. The resulting structure is shown in cross section in 11 shown. Thus, the wet etch step eliminates the polysilicon residue resulting from misregistration with the deep trench capacitor in the active area etch.

It However, it has been found that the wet process has certain side effects has to be compensated. In particular, wet etching has one Loss of depth in the third polysilicon layer result. This however, can be easily compensated by adding additional third polysilicon material is deposited to the loss of the third Polysilicon material during the wet etching process to compensate. Another way of expressing this is that the third polysilicon layer adjusted in previous process steps Will that be a greater height than usual having. For example, could the recess of the third polysilicon layer to 30 nm instead be set by 50 nm.

Second, the wet process results in a constriction of the third polysilicon material, which can result in a narrowing of the "active region window". This can be compensated by changing the active area mask to include larger contact areas to the trench capacitor. Corresponding 12 In particular, it normally connects an active area 801 two trench capacitors 103 , However, due to the lateral removal of the third polysilicon material due to the additional wet etch step, to increase the active area process window, the mask that defines the active area 801 forms are expanded in the lateral direction. Therefore, the active area should be expansion areas 803 include.

Even though the preferred embodiment the invention has been described and described, it should be emphasized that various changes executed can be without departing from the spirit and scope of the invention.

Claims (5)

Method for forming a deep trench capacitor ( 501 ) in a semiconductor substrate ( 303 ) and an active area (AA; 801 ) for active semiconductor elements, the method comprising: forming the deep trench capacitor ( 501 ) in the semiconductor substrate ( 303 ), which is an edge oxide ( 903 ), on which a conductive polysilicon layer ( 907 ), structuring and etching the arrangement for forming the active region (AA; 801 ), wherein at least a part of the active area (AA; 801 ) with the deep trench capacitor ( 501 ) overlaps; Wet etching of the deep trench capacitor ( 501 ) and active area (AA; 801 ), such that over the edge oxide ( 903 ) residues of the polysilicon layer ( 907 ) are removed. The method of claim 1, wherein the wet etching with an etchant with a high selectivity between doped polysilicon and the semiconductor substrate is performed. Method according to one of the preceding claims, wherein the wet etching carried out with ethylene glycol becomes. Method according to one of claims 1 to 2, wherein the wet etching is carried out with NH ₄ OH. Method according to one of the preceding claims, wherein the wet etching For 5-20 minutes carried out becomes.