CN2720634Y - 铜制程焊垫结构 - Google Patents
铜制程焊垫结构 Download PDFInfo
- Publication number
- CN2720634Y CN2720634Y CN200420059308.5U CN200420059308U CN2720634Y CN 2720634 Y CN2720634 Y CN 2720634Y CN 200420059308 U CN200420059308 U CN 200420059308U CN 2720634 Y CN2720634 Y CN 2720634Y
- Authority
- CN
- China
- Prior art keywords
- copper
- protective layer
- sequential structure
- weld pad
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05006—Dual damascene structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01083—Bismuth [Bi]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
一种铜制程焊垫结构。此铜制程焊垫结构包含第一保护层、第二保护层以及多个焊垫。第一保护层与第二保护层覆盖于半导体基材的最上层铜金属内连线之上,且具有多个开口,使露出最上层铜金属内连线表面。而焊垫形成于第一保护层的开口上方,并与最上层铜金属内连线表面相互连接,且相邻的焊垫彼此之间由第二保护层所隔离。该铜制程焊垫结构可有效改善焊垫的隔离结构,使焊垫在打线制程中有效避免产生桥接的问题,提高集成电路的电路设计稳定性、电路产品可靠度和集成电路的焊垫密度,有效增加集成电路产品的输出/输入接口的数量和电路产品的功能。
Description
技术领域
本实用新型涉及一种铜制程焊垫结构,特别涉及一种集成电路制程中所使用的铜制程焊垫结构。
背景技术
随着集成电路的线宽尺寸的微小化趋势,特别是0.25微米,乃至于0.13微米以下,组件的运算速度明显受到金属导线所造成的电阻电容延迟时间(Resistance Capacitance Delay Time;RC Delay Time)的影响,以致于降低其运算速度。因此,面对目前集成度(Integration)更高的电路设计,除了必须采用具有更低电阻的金属材料,例如电阻值约为1.67微欧姆-公分的铜(Cu),来取代传统所采用的电阻值约为2.66微欧姆-公分的铝,更必须搭配低介电常数的介电材料来建构多层金属内连线,以改善RC延迟的现象。
由于铜具有低电阻的特性,因此以铜为内连线的组件可承受更密集的电路排列。于是,铜金属的使用不仅可大幅缩减金属层的数目,降低生产成本,更可提升组件的运算速度。铜具有较高的抗电致迁移(Electronmigration)的能力,因此,以铜为内连线的组件尚具有更长的寿命及较佳的稳定性等优点。
以铜金属作为内连线的组件,在完成其所需的功能的电路布置后,一般采用较容易制作的铝质金属来制作组件的焊垫,例如是铝铜合金等材料所构成的焊垫。参阅图1,图1为一公知铝铜焊垫的剖面示意图。如图中所示,铜金属内连线110为最上层的金属内连线,其上方的保护层(Passivation Layer)120则通过蚀刻等制程形成开口,然后再形成焊垫(Bond Pad)130。焊垫130为集成电路与外界电路相连接的接口,使用于集成电路后续的打线(WireBond)封装制程。
近年来,集成电路的设计随着功能增强、尺寸小型化以及大量的输出/输入接口的需求,以致于缩小焊垫尺寸以及其间距的设计俨然已成为集成电路发展的趋势。一般而言,在0.13微米制程中,间距14的宽度约为3微米(μm)。更由于铝铜合金的质地较软,因此,在打线制程中焊垫130很容易产生变形,进而导致桥接(Bridging)的情况,使组件产生短路,严重影响产品的可靠度与良率。
因此,如何能有效改善焊垫130的隔离结构,使焊垫的结构能有效地防止桥接问题的产生,不仅可以提高集成电路的线路稳定性,更可进一步提高集成电路的产品可靠度,为集成电路的使用者与制造者所殷殷企盼。
实用新型内容
鉴于上述实用新型背景中,由于焊垫之间的间距越来越小,使得在进行打线时,易造成相邻焊垫产生桥接的问题,不仅会造成集成电路的产品可靠度的降低,更造成集成电路焊垫的短路。因此,提高集成电路焊垫的结构可靠度,以避免短路的情况,才能进一步提高产品的可靠度。
本实用新型的目的之一是提供一种铜制程焊垫结构,可防止焊垫之间短路的情况。
本实用新型的另一目的是提供一种铜制程焊垫结构,以提高集成电路产品的可靠度。
根据以上所述的目的,本实用新型提供一种铜制程焊垫结构。此铜制程焊垫结构包含第一保护层,第二保护层,以及多个焊垫。其中第一保护层,覆盖于半导体基材的最上层金属内连线之上。且第一保护层具有多个第一开口,使露出最上层金属内连线的多个区域。第二保护层,形成于第一保护层之上,具有多个第二开口,且分别对应于第一开口,露出第一开口。上述的焊垫形成于第一开口之上,并位于第二开口之中,并与最上层金属内连线所露出的区域相互电性连接,且上述的焊垫经由第二保护层彼此之间相互隔离。
其中上述的最上层金属内连线为铜金属内连线。第一保护层包含二氧化硅(SiO2)所构成的保护层,其厚度约为4000埃(Angstrom),第二保护层则包含氮化硅(SiN)所构成的保护层,其厚度约为6000埃,且介于焊垫之间的第二保护层宽度约为3微米(μm)。而上述焊垫则为铝铜合金、铝硅铜合金或铝所构成的金属焊垫。
本实用新型的铜制程焊垫结构不仅可以有效改善焊垫的隔离结构,使焊垫在打线制程中有效避免产生桥接的问题,一方面可以提高集成电路的电路设计稳定性,另一方面可进一步提高集成电路的产品可靠度,同时本实用新型还可提高集成电路的焊垫密度,以有效增加集成电路产品的输出/输入接口的数量,增强集成电路产品的功能。
附图说明
为让本实用新型的上述和其它目的、特征和优点能更明显易懂,特举较佳实施例,并配合附图做更详细说明,其中:
图1为一公知铝铜焊垫的剖面示意图;
图2为本实用新型的铜制程焊垫结构的示意图;以及
图3A至图3D为本实用新型的铜制程焊垫制造方法的流程示意图。
110铜金属内连线 120保护层
130焊垫 140间距
210铜金属内连线 220第一保护层
230焊垫 240第二保护层
250宽度 310铜金属内连线
320第一保护层 330第二保护层
332第一开口 340第二开口
360金属层 370焊垫
380宽度
具体实施方式
本实用新型提供一种铜制程焊垫结构,具有改善焊垫的隔离结构,使焊垫能有效防止短路问题的发生,不仅改善集成电路的电器特性,还可进一步提高集成电路产品的可靠度。以下将以附图及详细说明清楚地说明本实用新型的精神,如熟悉此技术的人员在了解本实用新型的较佳实施例后,当可由本实用新型所教示的技术,加以改变及修饰,其并不脱离本实用新型的精神与范围。
参阅图2,为本实用新型的铜制程焊垫结构的示意图。如图中所示,将本实用新型的铜制程焊垫结构详述如下。本实用新型的铜制程焊垫结构包含铜金属内连线210,第一保护层220,以及焊垫230。铜金属内连线210为此集成电路的最上层的金属内连线。第一保护层220则覆盖于铜金属内连线210之上,并露出部分铜金属内连线210。焊垫230与露出的部分铜金属内连线210电性连接。而每一相邻的焊垫230之间还具有第二保护层240,以确保在打线制程中,虽然焊垫230产生变形,但却能为第二保护层240所阻隔,而不会产生桥接现象,以致于有效阻止短路的情形发生。
其中,第一保护层220包含二氧化硅(SiO2)所构成的保护层,其厚度约为4000埃(Angstrom),而第二保护层240包含由氮化硅(SiN)所构成的保护层,其厚度约为6000埃。且第二保护层240的宽度250仅需与公知的焊垫间距相当即可,例如是3微米(μm)。
因此,本实用新型的铜制程焊垫结构,可在无需变更任何设计条件的情况下,使用于集成电路的焊垫设计,不仅可避免焊垫桥接所产生的短路的问题,还可以有效电性隔离焊垫,以提高集成电路的产品的可靠度。其中焊垫使用铝铜合金、铝硅铜合金或铝所构成的金属焊垫,用来与集成电路外部接脚电性耦合,以提供集成电路输出/输入的接口。
由于本实用新型的铜制程焊垫结构,利用第二保护层240,以有效地隔离相邻的焊垫230。因此,使用本实用新型的铜制程焊垫结构的集成电路,可进一步缩小焊垫之间的间距,以提高焊垫的数量,进而增加集成电路产品的输出/输入接口的数量。
本实用新型的铜制程焊垫结构,合适于使用在任何需要打线的焊垫隔离设计上。当使用于0.13微米制程中,第二保护层240的宽度250约仅为3微米,在其它更细微的制程中或需要更多的输出输入焊垫的设计中,本实用新型可有效改变第二保护层240的宽度250的设计,以达到上述的保护功能,均不脱离本实用新型的精神与范围。
参阅图3A至图3D,本实用新型的铜制程焊垫制造方法的流程说明如下。首先,如图3A图中所示,在集成电路的最上层铜金属内连线310上,依序形成第一保护层320与第二保护层330,并图案化第二保护层330,以在预定的位置形成第一开口332。
参阅图3B,如图中所示,接下来图案化第一保护层320,以形成第二开口340于第一保护层320之中,使其露出上述的最上层铜金属内连线310的部分区域。参阅图3C,如图中所示,接着再形成金属层360于上述的第一保护层320、第二保护层330、第一开口332与第二开口340之上。例如使用金属溅镀(Sputtering)、蒸镀(Evaporation)或者是化学气相沉积(ChemicalVapor Deposition)等方法,以形成此金属层360。
如图3D中所示,进行金属层360的图案化,以形成所需的焊垫370。而在图案化金属层360之时,第一保护层320还具有提供蚀刻终止层的功能。由于相邻的焊垫370之间,均被第二保护层330所分隔,因此焊垫370被有效的加以隔离,使焊垫370在后续的打线制程中,可避免产生桥接的问题。
一般而言,在0.13微米制程中,第二保护层330的宽度380约仅为3微米。而上述的金属层360为一铝质金属层,比如铝、铝铜合金或者铝硅铜合金等。而金属层360可使用如微影与蚀刻制程,以进行图案化。
本实用新型的铜制程焊垫结构能有效地隔离相邻的焊垫,以避免在打线制程中,相邻的焊垫产生桥接的问题。不仅可以提高集成电路产品的可靠度,还可以避免焊垫短路的问题,且还可进一步提高焊垫的密度,以增加输出/输入端子的数量,提高集成电路产品的功能。
如熟悉此技术的人员所了解的,以上所述仅为本实用新型的较佳实施例而已,并非用以限定本实用新型的权利要求。凡其它未脱离本实用新型所揭示的精神下所完成的等效改变或修饰,均应包含在所附权利要求的范围内。
Claims (8)
1.一种铜制程焊垫结构,其特征在于包含:
一第一保护层,覆盖于一半导体基材的一最上层金属内连线之上,其中该第一保护层具有多个第一开口,且所述第一开口露出该最上层金属内连线的多个区域;
一第二保护层,形成于该第一保护层之上,具有多个第二开口,且分别对应于所述第一开口,以露出所述第一开口;以及
多个焊垫,形成于所述第一开口之上,并位于所述第二开口之中,且所述焊垫与该最上层金属内连线所露出的所述区域电性连接。
2.如权利要求1所述的铜制程焊垫结构,其特征在于,上述最上层金属内连线为一铜金属内连线。
3.如权利要求1所述的铜制程焊垫结构,其特征在于,上述第一保护层包含一二氧化硅保护层。
4.如权利要求3所述的铜制程焊垫结构,其特征在于,上述二氧化硅保护层的厚度为4000埃。
5.如权利要求1所述的铜制程焊垫结构,其特征在于,上述第二保护层包含一氮化硅保护层。
6.如权利要求5所述的铜制程焊垫结构,其特征在于,上述氮化硅保护层的厚度为6000埃。
7.如权利要求1所述的铜制程焊垫结构,其特征在于,上述第二保护层介于所述焊垫之间的宽度为3微米。
8.如权利要求1所述的铜制程焊垫结构,其特征在于,上述焊垫为铝铜合金所构成的焊垫。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/444,229 | 2003-05-23 | ||
US10/444,229 US6844626B2 (en) | 2003-05-23 | 2003-05-23 | Bond pad scheme for Cu process |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2720634Y true CN2720634Y (zh) | 2005-08-24 |
Family
ID=33450603
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200310120177.7A Expired - Fee Related CN1574321B (zh) | 2003-05-23 | 2003-12-10 | 铜工艺焊垫结构及其制造方法 |
CN200420059308.5U Expired - Lifetime CN2720634Y (zh) | 2003-05-23 | 2004-05-17 | 铜制程焊垫结构 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200310120177.7A Expired - Fee Related CN1574321B (zh) | 2003-05-23 | 2003-12-10 | 铜工艺焊垫结构及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6844626B2 (zh) |
CN (2) | CN1574321B (zh) |
SG (1) | SG115593A1 (zh) |
TW (1) | TWI222710B (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10337569B4 (de) * | 2003-08-14 | 2008-12-11 | Infineon Technologies Ag | Integrierte Anschlussanordnung und Herstellungsverfahren |
KR100675275B1 (ko) * | 2004-12-16 | 2007-01-26 | 삼성전자주식회사 | 반도체 장치 및 이 장치의 패드 배치방법 |
CN100377627C (zh) * | 2006-02-28 | 2008-03-26 | 友达光电股份有限公司 | 可防止相邻焊垫短路的电路板 |
KR100791080B1 (ko) * | 2007-01-23 | 2008-01-03 | 삼성전자주식회사 | 금속 패드 구조체를 갖는 전자 장치 및 그 제조방법 |
US7888257B2 (en) * | 2007-10-10 | 2011-02-15 | Agere Systems Inc. | Integrated circuit package including wire bonds |
US8183698B2 (en) * | 2007-10-31 | 2012-05-22 | Agere Systems Inc. | Bond pad support structure for semiconductor device |
KR101383002B1 (ko) | 2012-05-25 | 2014-04-08 | 엘지이노텍 주식회사 | 반도체 패키지 기판, 이를 이용한 패키지 시스템 및 이의 제조 방법 |
KR101350989B1 (ko) | 2012-06-13 | 2014-01-15 | 도시바삼성스토리지테크놀러지코리아 주식회사 | 대물렌즈 구동 유니트 및, 이를 적용하는 광 픽업 장치 및 광 디스크 드라이브 |
US11424204B2 (en) * | 2019-08-15 | 2022-08-23 | Mediatek Inc. | Semiconductor component and manufacturing method thereof |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6187680B1 (en) * | 1998-10-07 | 2001-02-13 | International Business Machines Corporation | Method/structure for creating aluminum wirebound pad on copper BEOL |
TWI249548B (en) * | 1998-12-08 | 2006-02-21 | Toyo Boseki | Void-containing polyester-based film |
US6197681B1 (en) * | 1999-12-31 | 2001-03-06 | United Microelectronics Corp. | Forming copper interconnects in dielectric materials with low constant dielectrics |
US6709965B1 (en) * | 2002-10-02 | 2004-03-23 | Taiwan Semiconductor Manufacturing Company | Aluminum-copper bond pad design and method of fabrication |
-
2003
- 2003-05-23 US US10/444,229 patent/US6844626B2/en not_active Expired - Lifetime
- 2003-11-03 TW TW092130619A patent/TWI222710B/zh not_active IP Right Cessation
- 2003-12-04 SG SG200307202A patent/SG115593A1/en unknown
- 2003-12-10 CN CN200310120177.7A patent/CN1574321B/zh not_active Expired - Fee Related
-
2004
- 2004-05-17 CN CN200420059308.5U patent/CN2720634Y/zh not_active Expired - Lifetime
- 2004-11-29 US US10/999,464 patent/US7015129B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1574321B (zh) | 2010-04-28 |
TW200426987A (en) | 2004-12-01 |
SG115593A1 (en) | 2005-10-28 |
US20050095836A1 (en) | 2005-05-05 |
CN1574321A (zh) | 2005-02-02 |
US7015129B2 (en) | 2006-03-21 |
TWI222710B (en) | 2004-10-21 |
US20040235223A1 (en) | 2004-11-25 |
US6844626B2 (en) | 2005-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
USRE43674E1 (en) | Post passivation metal scheme for high-performance integrated circuit devices | |
CN1235287C (zh) | 用于铜/低介电常数材料后段制程的接合垫结构 | |
KR100275099B1 (ko) | 집적 회로의 금속층간의 저저항 콘택트 및그 형성 방법 | |
CN1225780C (zh) | 制作热熔丝的方法 | |
CN1728370A (zh) | 制备集成电路芯片的方法及所形成的晶片和芯片 | |
JP2001267323A (ja) | 半導体装置及びその製造方法 | |
US6864578B2 (en) | Internally reinforced bond pads | |
DE112015007068T5 (de) | Alternative oberflächen für leitende kontaktinselschichten von siliziumbrücken für halbleitergehäuse | |
CN1967845A (zh) | 半导体器件及其制造方法 | |
CN2720634Y (zh) | 铜制程焊垫结构 | |
CN1905175A (zh) | 半导体装置及其制造方法 | |
CN1947247A (zh) | 通用互连芯片 | |
WO2006103620A2 (en) | Carbon nanotube bond pad srtucture and manufacturing method thereof | |
CN2731711Y (zh) | 铜金属镶嵌结构 | |
EP2264757B1 (en) | Active area bonding compatible high current structures | |
US7495335B2 (en) | Method of reducing process steps in metal line protective structure formation | |
CN1265452C (zh) | 一种集成电路的金属焊垫及其制作方法 | |
CN1707769A (zh) | 半导体装置的制造方法 | |
US8946912B2 (en) | Active area bonding compatible high current structures | |
CN1790694A (zh) | 突出检查区的外形结构 | |
EP1544914A2 (en) | Semiconductor device and method of manufacturing thereof | |
CN1226787C (zh) | 金属垫与接合垫区的结构 | |
CN1438701A (zh) | 半导体基底上的接合垫结构 | |
CN1879208A (zh) | 用于探针测试和布线接合的i/o位置 | |
KR100482364B1 (ko) | 반도체소자의다층패드및그제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CX01 | Expiry of patent term |
Expiration termination date: 20140517 Granted publication date: 20050824 |