CN220473287U - QCM binary channels vibrate collection system - Google Patents
QCM binary channels vibrate collection system Download PDFInfo
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- CN220473287U CN220473287U CN202321598181.3U CN202321598181U CN220473287U CN 220473287 U CN220473287 U CN 220473287U CN 202321598181 U CN202321598181 U CN 202321598181U CN 220473287 U CN220473287 U CN 220473287U
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- 230000010355 oscillation Effects 0.000 claims description 20
- 101000701286 Pseudomonas aeruginosa (strain ATCC 15692 / DSM 22644 / CIP 104116 / JCM 14847 / LMG 12228 / 1C / PRS 101 / PAO1) Alkanesulfonate monooxygenase Proteins 0.000 claims description 4
- 101000983349 Solanum commersonii Osmotin-like protein OSML13 Proteins 0.000 claims description 4
- 238000003380 quartz crystal microbalance Methods 0.000 description 76
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- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
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- 208000037265 diseases, disorders, signs and symptoms Diseases 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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Abstract
The utility model provides a QCM (QCM) double-channel vibration acquisition device, which relates to the technical field of vibration acquisition systems, and comprises a main control chip, a QCM double-channel detection module, a power supply circuit and a multi-device interaction module, wherein the power supply circuit is connected with the main control chip for supplying power, the main control chip is connected with the QCM double-channel detection module for detecting QCM signals and is used for acquiring the QCM signals, and the main control chip is also connected with the multi-device interaction module.
Description
Technical Field
The utility model relates to the technical field of vibration acquisition systems, in particular to a QCM double-channel vibration acquisition device.
Background
Quartz Crystal Microbalance (QCM) is a precise mass sensor, and is widely used in immunosensor technology, and has important significance for the research of biological molecules due to the characteristics of simplicity, convenience, low cost, quick response in real time and the like.
Currently, in many applications of QCM as immunosensor, oscillator circuits are of paramount importance, as they are capable of converting small mass changes on QCM sensors into electrical signals, thereby detecting small amounts of environmental pollutants or disease markers, but the oscillator circuits of these devices have the following problems: the sampling frequency is low, and the high-frequency signal acquisition is unstable; the modulation of the high-frequency waveform is imperfect, and the data is unstable; the data output mode is single, only the connection of the computer is supported, and the external equipment is difficult to interact; the utility model discloses a crystal starting circuit that only supports defects such as single channel collection, like prior art discloses a be applied to on QCM circuit, the oscillator circuit is based on the oscillating chip, the 3 rd foot and the 4 th foot of oscillating chip are connected to the output and the input of AT cutting crystal oscillator respectively, the 6 th foot output of oscillating chip is connected to the 1 st foot of multistage inverter, the 7 th foot of multistage inverter outputs the frequency signal, be connected with filter capacitor and filter resistor to ground on the connecting wire between oscillating chip and the multistage inverter, as previously mentioned, the oscillating circuit design of QCM is crucial to immunosensor's application, therefore, how to design an oscillating circuit that gathers data high efficiency stability and support multi-device interaction is extremely important technical problem to be solved.
Disclosure of Invention
In order to solve the problem of how to design an oscillation circuit for efficiently and stably collecting data and supporting multi-equipment interaction at present, the utility model provides a QCM double-channel oscillation collecting device, which provides efficient and stable data collection, supports multi-equipment interaction, ensures various data output modes and is convenient for users to detect QCM signals of various conditions.
In order to achieve the technical effects, the technical scheme of the utility model is as follows:
the utility model provides a QCM binary channels vibrate collection system, the device includes main control chip, QCM binary channels detection module, power supply circuit and the mutual module of many devices, power supply circuit is connected with main control chip and is used for supplying power, main control chip is connected with the QCM binary channels detection module that is used for detecting the QCM signal, main control chip still is connected with the mutual module of many devices.
Preferably, the QCM dual-channel detection module comprises a first QCM probe, a first QCM detection circuit, a second QCM probe and a second QCM detection circuit, wherein the output end of the first QCM probe is connected with the input end of the first QCM detection circuit, the output end of the first QCM detection circuit is connected with the input end of the main control chip, the output end of the second QCM probe is connected with the input end of the second QCM detection circuit, the output end of the second QCM detection circuit is connected with the input end of the main control chip, and the model of the main control chip is STM32F407zGT6.
Preferably, the first QCM detection circuit includes a first detection chip, a first capacitor C1, a first resistor R1, a second resistor R2, a second resistor C2 and a type-a interface, where the type of the first detection chip is SN74LVC1GX04DBVR, the GND pin of the first detection chip is grounded, the X1 pin of the first detection chip is connected to one end of the first capacitor C1, one end of the first resistor R1 and a D-network pin of the type-a interface, the other end of the first capacitor C1 is grounded, the d+ network pin of the type-a interface is connected to one end of the second resistor R2 and one end of the second capacitor C2, the other end of the second resistor C2 is grounded, the other end of the second resistor R2 is connected to the other end of the first resistor R1 and the X2 pin of the first detection chip, the Y pin of the first detection chip is connected to the PA5 pin of the master control chip, and the first probe includes two pins, the two QCM pins are connected to the two QCM pins and the two QCM-d+ network pins of the type-a interface;
the second QCM detection circuit comprises a second detection chip, a third capacitor C3, a third resistor R3, a fourth resistor R4, a fourth capacitor C4 and a type-A interface, the second detection chip is the same as the first detection chip in type, the GND pin of the second detection chip is grounded, the X1 pin of the second detection chip is respectively connected with one end of the third capacitor C3, one end of the third resistor R3 and the D-network pin of the type-A interface, the other end of the third capacitor C3 is grounded, the D+ network pin of the type-A interface is respectively connected with one end of the fourth resistor R4 and one end of the fourth capacitor C4, the other end of the fourth resistor R4 is grounded, the other end of the fourth resistor R4 is respectively connected with the other end of the third resistor R3 and the X2 pin of the second detection chip, the Y pin of the second detection chip is connected with the power circuit, the Y pin of the second detection chip is connected with the PE0 pin of the master control chip, the second QCM probe comprises two pins, and the two QCM probes are respectively connected with the D+ network pin of the type-A interface and the D+ network pin of the second QCM probe.
Preferably, the power supply circuit includes a first power supply chip with the model AMS1117, a fifth capacitor C5, a sixth capacitor C6, an LED diode and a fifth resistor R5, where the VIN pin of the first power supply chip is connected to one end of the input power supply and the fifth capacitor C5, the other end of the fifth capacitor C5 is grounded, the VOUT pin of the first power supply chip is connected to the TAB pin of the first power supply chip, one end of the sixth capacitor C6 and the input end of the LED diode, the TAB pin of the first power supply chip is connected to the VCC pin of the first detection chip and the VCC pin of the second detection chip, the other end of the sixth capacitor C6 is connected to the ADJ pin of the first power supply chip and then grounded together, the output end of the LED diode is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded.
Preferably, the multi-device interaction module comprises an SPI interface circuit, a USART interface circuit, an IIC interface circuit and a USB-CDC interface circuit which are connected in parallel, and the SPI interface circuit, the USART interface circuit, the IIC interface circuit and the USB-CDC interface circuit are connected with the main control chip in a bidirectional mode.
Preferably, the SPI interface circuit comprises an SPI interface with the model of KH-0.5-H3.25-6PIN, wherein the 1 st PIN of the SPI interface is grounded, the 2 nd PIN of the SPI interface is connected with the PC12 PIN of the main control chip, the 3 rd PIN of the SPI interface is connected with the PC11 PIN of the main control chip, the 4 th PIN of the SPI interface is connected with the PC10 PIN of the main control chip, the 5 th PIN of the SPI interface is connected with the PA4 PIN of the main control chip, and the 6 th PIN of the SPI interface is connected with the TAB PIN of the first power supply chip;
the USART interface circuit comprises a USART interface with the model number of AFA07-S04ECA-00, wherein the 1 st pin of the USART interface is grounded, the 2 nd pin of the USART interface is connected with the PA10 pin of the main control chip, the 3 rd pin of the USART interface is connected with the PA9 pin of the main control chip, and the 4 th pin of the USART interface is connected with an input power supply;
the IIC interface circuit comprises an IIC interface with the model of AFA07-S04ECA-00, wherein a1 st pin of the IIC interface is connected with a TAB pin of a first power chip, a 2 nd pin of the IIC interface is connected with a PB 6pin of a main control chip, a 3 rd pin of the IIC interface is connected with a PB7 pin of the main control chip, and a4 th pin of the IIC interface is grounded;
the USB-CDC interface circuit comprises a USB-CDC interface chip with the model number of CH340C, a merco USB interface with the model number of 10103594-0001LF and a ninth capacitor C9,
the GND pin of the USB-CDC interface chip is grounded, the TXD pin of the USB-CDC interface chip is connected with the PA9 pin of the main control chip, the RXD pin of the USB-CDC interface chip is connected with the PA10 pin of the main control chip, the V3 pin of the USB-CDC interface chip is connected with the TAB pin of the first power supply chip, the VCC pin of the USB-CDC interface chip is respectively connected with one end of the ninth capacitor C9 and an input power supply, the other end of the ninth capacitor C9 is grounded,
the VCC pin of the merco USB interface is connected with an input power supply, the D+ network pin of the merco USB interface is connected with the D+ network pin of the USB-CDC interface chip, the D-network pin of the merco USB interface is connected with the D-network pin of the USB-CDC interface chip, and the GND pin of the merco USB interface and the EP pin of the merco USB interface are connected and then grounded together.
Preferably, the input power is input through a TYPE-C interface circuit or a USB-CDC interface circuit, the YPE-C interface circuit comprises a TYPE-C interface with the model of YPE-C-31-M-33, GND pins of the TYPE-C interface are grounded, 4 EH pins of the TYPE-C interface are commonly connected and then grounded, and VBUS pins of the TYPE-C interface are connected with the input power.
Preferably, the system comprises a system support module, wherein the system support module comprises a first filter circuit, a SWDIO interface circuit, a crystal oscillator circuit, a resistor pull-up circuit, a resistor pull-down circuit and a second filter circuit which are parallel;
the first filter circuit comprises a plurality of first filter capacitors connected in parallel, each first filter capacitor C 1.1 One end of the first filter capacitor C is respectively connected with the VDD pin, the VBAT pin and the VDDA pin of the main control chip and then is commonly connected with the TAB pin of the first power supply chip 1.1 The other end of the pin is respectively connected with the VREF+ pin, the VSS pin and the VSSA pin of the main control chip and then commonly grounded;
the SWDIO interface circuit comprises an SWDIO interface with the model number of AFA07-S04ECA-00, wherein the 1 st pin of the SWDIO interface is connected with the TAB pin of the first power chip, the 2 nd pin of the SWDIO interface is connected with the PA14 pin of the main control chip, the 3 rd pin of the SWDIO interface is connected with the PA13 pin of the main control chip, and the 4 th pin of the SWDIO interface is grounded;
the crystal oscillator circuit comprises a crystal oscillator, a seventh capacitor C7 and an eighth capacitor C8, wherein a1 st pin of the crystal oscillator is respectively connected with one end of the seventh capacitor C7 and a PH0 pin of the main control chip, the other end of the seventh capacitor C7 is connected with a 2 nd pin of the crystal oscillator and then commonly grounded, a 3 rd pin of the crystal oscillator is respectively connected with a PH1 pin of the main control chip and one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is connected with a4 th pin of the crystal oscillator and then commonly grounded;
the resistor pull-up circuit comprises a pull-up resistor RA, one end of the pull-up resistor RA is connected with a BOOT0 pin of the main control chip, and the other end of the pull-up resistor RA is grounded;
the resistor pull-down circuit comprises a pull-down resistor RB, one end of the pull-down resistor RB is connected with a PDR_ON pin of the main control chip, and the other end of the pull-down resistor RB is connected with a TAB pin of the first power supply chip;
the second filter circuit comprises a second filter capacitor C 2.2 And a third filter capacitor C 3.3 The second filter capacitor C 2.2 One end of the first chip is connected with the VCAP_1 pin of the main control chipTwo filter capacitors C 2.2 And the other end of the third filter capacitor C 3.3 One end of the third filter capacitor C is connected to the common ground 3.3 The other end of the pin is connected with the VCAP_2 pin of the master control chip.
Preferably, the power-down reset circuit further comprises a power-down reset key, an 8 th resistor, a10 th capacitor and a first anti-static diode, wherein one end of the power-down reset key is respectively connected with an NRST pin of a main control chip, one end of the 8 th resistor, one end of the 10 th capacitor and one end of the first anti-static diode, the other end of the 8 th resistor is connected with a TAB pin of the first power chip, and the other end of the power-down reset key is respectively connected with the other end of the 10 th capacitor and the other end of the first anti-static diode and then is grounded together.
Preferably, the program reset circuit further comprises a program reset key, a sixth resistor R6, a seventh resistor R7, a second anti-static diode and a ninth capacitor C9, wherein one end of the program reset key is respectively connected with one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the second anti-static diode and one end of the ninth capacitor C9, the other end of the sixth resistor R6 is connected with a PA0 pin of the main control chip, the other end of the seventh resistor R7 is connected with the other end of the second anti-static diode together and then grounded, and the other end of the ninth capacitor C9 is connected with the other end of the program reset key and then grounded.
Compared with the prior art, the technical scheme of the utility model has the beneficial effects that:
the utility model provides a QCM double-channel oscillation acquisition device, which aims to solve the problems that the current QCM oscillation circuit is low in data acquisition efficiency and unstable and cannot support multi-device interaction, and adopts the combination of a main control chip and a QCM double-channel detection module to realize the double-channel stable acquisition of high-frequency QCM signals, so that the data output mode is various, different user requirements can be met, and the system is also provided with a multi-device interaction module, so that data acquired by the main control chip can be communicated with external devices, thereby meeting the requirements of different use scenes, and improving the universality and convenience of system application.
Drawings
Fig. 1 shows a schematic diagram of a QCM dual-channel oscillation acquisition device according to an embodiment of the present utility model;
FIG. 2 shows a schematic diagram of a master control chip;
FIG. 3 shows a schematic diagram of a first QCM detection circuit;
fig. 4 shows a schematic diagram of a first QCM probe and a second QCM probe;
fig. 5 shows a schematic diagram of a second QCM detection circuit;
FIG. 6 shows a schematic diagram of a power supply circuit;
FIG. 7 shows a schematic diagram of an SPI interface circuit;
FIG. 8 shows a schematic diagram of a USART interface circuit;
FIG. 9 shows a schematic diagram of an IIC interface circuit;
FIG. 10 shows a schematic diagram of a USB-CDC interface circuit;
FIG. 11 shows a schematic diagram of a TYPE-C interface circuit;
FIG. 12 shows a schematic diagram of a first filter circuit;
FIG. 13 shows a schematic diagram of a SWDIO interface circuit;
FIG. 14 shows a schematic diagram of a crystal oscillator circuit;
FIG. 15 shows a schematic diagram of a resistor pull-up circuit;
FIG. 16 shows a schematic diagram of a resistor pull-down circuit;
FIG. 17 shows a schematic diagram of a second filter circuit;
FIG. 18 shows a schematic diagram of a power down reset circuit;
FIG. 19 shows a schematic diagram of a program reset circuit;
1. a main control chip; qcm dual channel detection module; 21. a first QCM probe; 22. a first QCM detection circuit; 23. a second QCM probe; 24. a second QCM detection circuit; 3. a power supply circuit; 4. a multi-device interaction module; 5. a system support module; 6. a power-down reset circuit; 7. a program reset circuit.
Detailed Description
The drawings are for illustrative purposes only and are not to be construed as limiting the present patent;
for better illustrating the present embodiment, some parts of the drawings may be omitted, enlarged or reduced, and do not represent actual dimensions, and the description of the directions of the parts such as "up" and "down" is not limiting of the present patent;
it will be appreciated by those skilled in the art that some well known descriptions in the figures may be omitted;
the positional relationship depicted in the drawings is for illustrative purposes only and is not to be construed as limiting the present patent;
the technical scheme of the utility model is further described below with reference to the accompanying drawings and examples.
Example 1
As shown in fig. 1, this embodiment provides a QCM binary channels vibration collection system, the device includes main control chip 1, QCM binary channels detection module 2, power supply circuit 3 and multi-device interaction module 4, the model of main control chip 1 is STM32F407ZGT6, power supply circuit 3 is connected with main control chip 1 and is used for supplying power, main control chip 1 is connected with QCM binary channels detection module 2 that is used for detecting QCM signal for gather the QCM signal, main control chip 1 still is connected with multi-device interaction module 4.
Referring to fig. 2, the STM32F407ZGT6 main control chip 1 includes pins VBAT, VSS, VDD, PH0, PH1, NRST, VSSA, VREF +, VDDA, PA0, PA4, PA5, vcap_1, pdr_on, PE0, BOOT0, PB7, PB6, PC12, PC11, PC10, PA14, vcap_2, PA13, PA10, PA9, etc., and it should be specifically noted that, since the pins of the STM32F407ZGT6 main control chip 1 are too many, the drawing cannot clearly show each pin, the pins of the STM32F407ZGT6 main control chip 1 illustrated in fig. 2 are only partial pins, but not all pins of the STM32F407ZGT6 main control chip 1.
Referring to fig. 1, the QCM dual-channel detection module 2 includes a first QCM probe 21, a first QCM detection circuit 22, a second QCM probe 23 and a second QCM detection circuit 24, where an output end of the first QCM probe 21 is connected to an input end of the first QCM detection circuit 22, an output end of the first QCM detection circuit 22 is connected to an input end of the main control chip 1, an output end of the second QCM probe 23 is connected to an input end of the second QCM detection circuit 24, and an output end of the second QCM detection circuit 24 is connected to an input end of the main control chip 1.
Referring to fig. 3, the first QCM detection circuit 22 includes a first detection chip, 100pf first capacitors C1, 2.2mΩ first resistors R1, 1kΩ second resistors R2, 100pf second capacitors C2 and type-a interfaces, the first detection chip is SN74LVC1GX04DBVR, the type-a interface is 292303-1, the GND pin of the first detection chip is grounded, the X1 pin of the first detection chip is connected to one end of the first capacitor C1, one end of the first resistor R1 and the D-network pin of the type-a interface respectively, the other end of the first capacitor C1 is grounded, the d+ network pin of the type-a interface is connected to one end of the second resistor R2 and one end of the second capacitor C2 respectively, the other end of the second resistor R2 is connected to the other end of the first resistor R1 and the X2 pin of the first detection chip respectively, the VCC pin of the first detection chip is connected to the VCC pin of the first detection chip, the first probe 3 and the two D-PA pins of the first detection chip are connected to the two 3, and the two D-PA pins of the first probe 21 and the first probe 21 are connected to the two network pins of the first PA-PA interface respectively;
in the first QCM detection circuit 22, the X1 pin and the X2 pin of the first detection chip are connected to a first resistor R1 of 2.2mΩ, and the X1 pin and the X2 pin are respectively connected to a first capacitor C1 of 100pf and a second capacitor C2 of 100pf in bypass for filtering, the X2 pin of the first detection chip is connected in series to a second resistor R2 of 1kΩ, and the X1 pin and the X2 pin are connected to a d+ network pin and a D-network pin of the type-a interface, so that the first QCM detection circuit 22 is connected to the first QCM probe conveniently.
Referring to fig. 5, the second QCM detection circuit 24 includes a second detection chip, a 100pF third capacitor C3, a third resistor R3 of 2.2mΩ, a fourth resistor R4 of 1kΩ, a fourth resistor C4 of 100pF, and a type-a interface, the second detection chip is the same as the first detection chip in model, the type-a interface and the type-a interface in model, the GND pin of the second detection chip is grounded, the X1 pin of the second detection chip is connected to one end of the third capacitor C3, one end of the third resistor R3 and the D-network pin of the type-a interface respectively, the other end of the third capacitor C3 is grounded, the d+ network pin of the type-a interface is connected to one end of the fourth resistor R4 and one end of the fourth capacitor C4 respectively, the other end of the fourth resistor R4 is connected to the other end of the third resistor R3 and the X2 pin of the second detection chip respectively, the VCC pin of the second detection chip is connected to one end of the power supply circuit 3, the Y pin of the second detection chip is connected to the Y pin of the second detection chip and the second probe 23, and the two QCM pins of the second probe 23 are connected to the two network pins, see fig. 23 and the two QCM-23 are connected to the two network pins.
The QCM double-channel oscillation acquisition device provided by the embodiment aims to solve the problems that the current QCM oscillation circuit is low in data acquisition efficiency, unstable and incapable of supporting multi-equipment interaction, and adopts the combination of a main control chip with the model of STM32F407ZGT6 and a QCM double-channel detection module to realize the double-channel stable acquisition of high-frequency QCM signals, and the main control chip has a main frequency of 168Mhz, so that the stable acquisition of 15.106Mhz is supported by the highest sampling frequency, and the signal acquisition of the current main flow 1M to 14M can be completely supported; optimizing the layout of the acquisition circuit to ensure perfect modulation of each frequency waveform, thereby ensuring the stability of data; the QCM dual-channel oscillation acquisition device has the advantages of high efficiency and stability in data acquisition, multi-device interaction support, multiple data output modes and the like, and is convenient for users to detect QCM signals in various conditions, thereby having practical application value.
Example 2
Referring to fig. 6, the power circuit 3 includes a first power chip with the model AMS1117, a 100nF fifth capacitor C5, a 100nF sixth capacitor C6, an LED diode, and a 1kΩ fifth resistor R5, where a VIN pin of the first power chip is connected to a 5V input power supply and one end of the fifth capacitor C5, another end of the fifth capacitor C5 is grounded, a VOUT pin of the first power chip is connected to a TAB pin of the first power chip, one end of the sixth capacitor C6, and an input end of the LED diode, a TAB pin of the first power chip is connected to a VCC pin of the first detection chip and a VCC pin of the second detection chip, another end of the sixth capacitor C6 is connected to an ADJ pin of the first power chip and then commonly grounded, an output end of the LED diode is connected to one end of the fifth resistor R5, and another end of the fifth resistor R5 is grounded; the 5V input power is converted into 3.3V through the first detection chip, 3.3V is output from the TAB pin of the first power chip, the LED diode and the fifth resistor R5 are connected to the output position of the 3.3V to be used as power supply indication, and the user is indicated whether the main control chip 1 is powered or not to operate while the main control chip 1 is ensured to be powered stably.
Referring to fig. 1, the multi-device interaction module 4 includes a parallel SPI interface circuit, a USART interface circuit, an IIC interface circuit, and a USB-CDC interface circuit, which are bi-directionally connected to the main control chip 1.
Referring to fig. 7, the SPI interface circuit includes an SPI interface having a type KH-0.5-H3.25-6PIN, a1 st PIN of the SPI interface is grounded, a 2 nd PIN of the SPI interface is connected to a PC12 PIN of the main control chip 1, a 3 rd PIN of the SPI interface is connected to a PC11 PIN of the main control chip 1, a4 th PIN of the SPI interface is connected to a PC10 PIN of the main control chip 1, a5 th PIN of the SPI interface is connected to a PA4 PIN of the main control chip 1, and a 6 th PIN of the SPI interface is connected to a TAB PIN of the first power supply chip;
referring to fig. 8, the USART interface circuit includes a USART interface with a model number of AFA07-S04ECA-00, a1 st pin of the USART interface is grounded, a 2 nd pin of the USART interface is connected with a PA10 pin of the main control chip 1, a 3 rd pin of the USART interface is connected with a PA9 pin of the main control chip 1, and a4 th pin of the USART interface is connected with a 5V input power supply;
referring to fig. 9, the IIC interface circuit includes an IIC interface with a model AFA07-S04ECA-00, a1 st pin of the IIC interface is connected to a TAB pin of the first power chip, a 2 nd pin of the IIC interface is connected to a PB 6pin of the main control chip 1, a 3 rd pin of the IIC interface is connected to a PB7 pin of the main control chip 1, and a4 th pin of the IIC interface is grounded;
referring to fig. 10, the USB-CDC interface circuit includes a USB-CDC interface chip with a model CH340C, a merco USB interface with a model 10103594-0001LF, and a ninth capacitor C9 with 100nF, where a GND pin of the USB-CDC interface chip is grounded, a TXD pin of the USB-CDC interface chip is connected to a PA9 pin of the master control chip 1, a RXD pin of the USB-CDC interface chip is connected to a PA10 pin of the master control chip 1, a V3 pin of the USB-CDC interface chip is connected to a TAB pin of the first power supply chip, a VCC pin of the USB-CDC interface chip is connected to one end of the ninth capacitor C9 and a 5V input power supply, and the other end of the ninth capacitor C9 is grounded, where the ninth capacitor C9 is used to filter a power signal input to the USB-CDC interface chip, so as to ensure that the USB-CDC interface chip can work normally; the VCC pin of the merco USB interface is connected with a 5V input power supply, the D+ network pin of the merco USB interface is connected with the D+ network pin of the USB-CDC interface chip, and the D-network pin of the merco USB interface is connected with the D-network pin of the USB-CDC interface chip, so that a computer can acquire information in the main control chip 1; the GND pin of the merco USB interface is connected with the EP pin of the merco USB interface and then is grounded together.
Referring to fig. 10 and 11, the 5V input power is input through a TYPE-C interface circuit or a USB-CDC interface circuit, the TYPE-C interface circuit includes a TYPE-C interface of TYPE-C-31-M-33, GND pins of the TYPE-C interface are grounded, and 4 EH pins of the TYPE-C interface are commonly connected and then grounded, and VBUS pins of the TYPE-C interface are connected with the 5V input power.
Example 3
Referring to fig. 1, the QCM dual-channel oscillation acquisition device provided in this embodiment further includes a system support module 5, where the system support module 5 includes a first filter circuit, a SWDIO interface circuit, a crystal oscillator circuit, a resistor pull-up circuit, a resistor pull-down circuit, and a second filter circuit in parallel;
referring to FIG. 12, the first filter circuit includes 12 first filter capacitors connected in parallel, the 12 first filter capacitors having a size of 100nf, each first filter capacitor C 1.1 One end of the first power chip is respectively connected with the VDD pin, the VBAT pin and the VDDA pin of the main control chip 1 and then is commonly connected with the TAB pin of the first power chip, each firstFilter capacitor C 1.1 The other end of the first filter circuit is connected with VREF+ pin, VSS pin and VSSA pin of the main control chip 1 respectively and then commonly grounded, and the first filter circuit is used for filtering power signals input into VDD pin, VBAT pin, VDDA pin, VREF+ pin, VSS pin and VSSA pin of the main control chip 1, so that the main control chip 1 can work normally.
Referring to fig. 13, the SWDIO interface circuit includes a SWDIO interface with a model AFA07-S04ECA-00, a1 st pin of the SWDIO interface is connected to a TAB pin of the first power chip, a 2 nd pin of the SWDIO interface is connected to a PA14 pin of the main control chip 1, a 3 rd pin of the SWDIO interface is connected to a PA13 pin of the main control chip 1, and a4 th pin of the SWDIO interface is grounded;
referring to fig. 14, the crystal oscillator circuit includes a crystal oscillator with a frequency of 25Mhz, a seventh capacitor C7 with 22pF and an eighth capacitor C8 with 22pF, where the seventh capacitor C7 and the eighth capacitor C8 are both 22pF, the 1 st pin of the crystal oscillator is connected to one end of the seventh capacitor C7 and the PH0 pin of the main control chip 1 respectively, the other end of the seventh capacitor C7 is connected to the 2 nd pin of the crystal oscillator and then grounded together, the 3 rd pin of the crystal oscillator is connected to the PH1 pin of the main control chip 1 and one end of the eighth capacitor C8 respectively, and the other end of the eighth capacitor C8 is connected to the 4 th pin of the crystal oscillator and then grounded together, so as to form a pierce oscillation circuit for maintaining the 168Mhz main frequency stability of the main control chip 1 and reducing the program error of the main control chip 1.
Referring to fig. 15, the resistor pull-up circuit includes a10 kΩ pull-up resistor RA, one end of the pull-up resistor RA is connected to a BOOT0 pin of the main control chip 1, and the other end is grounded;
referring to fig. 16, the resistor pull-down circuit includes a10 kΩ pull-down resistor RB, one end of the pull-down resistor RB is connected to the pdr_on pin of the main control chip 1, and the other end is connected to the TAB pin of the first power chip;
referring to FIG. 17, the second filter circuit includes a second filter capacitor C of 2.2uf 2.2 And a third filter capacitor C of 2.2uf 3.3 The second filter capacitor C 2.2 One end of the second filter capacitor C is connected with the VCAP_1 pin of the main control chip 1 2.2 And the other end of the third filter capacitor C 3.3 Is connected with one end of the jointGround, third filter capacitor C 3.3 The other end of the filter capacitor C is connected with the VCAP_2 pin of the main control chip 1 2.2 Filtering the VCAP_1 pin of the main control chip 1 and utilizing a third filter capacitor C 3.3 The VCAP_2 pin of the main control chip 1 is filtered, so that the main control chip 1 can work stably and normally.
The QCM dual-channel oscillation acquisition device provided by the embodiment further comprises a power-down reset circuit 6, referring to fig. 18, the power-down reset circuit 6 comprises a power-down reset key, an 8 th resistor of 1kΩ, a 100nf 10 th capacitor and a first antistatic diode, one end of the power-down reset key is respectively connected with an NRST pin of the main control chip 1, one end of the 8 th resistor, one end of the 10 th capacitor and one end of the first antistatic diode, the other end of the 8 th resistor is connected with a TAB pin of the first power supply chip, and the other end of the power-down reset key is respectively connected with the other end of the 10 th capacitor and the other end of the first antistatic diode and then commonly grounded; in the power-down reset circuit 6, one end of a power-down reset key is connected into an NRST pin of the main control chip 1, and is connected with an 8 th resistor of 1KΩ and 3.3V voltage in parallel for pulling up, two ends of the power-down reset key are connected with a10 th capacitor of 100nf for eliminating jitter, two ends of the 10 th capacitor are connected with a first anti-static diode, the other end of the power-down reset key is grounded, and the power-down reset circuit 6 is used for carrying out power restoration when the main control chip 1 is powered down.
The QCM dual-channel oscillation acquisition device provided in this embodiment further includes a program reset circuit 7, see fig. 19, where the program reset circuit 7 includes a program reset key, a sixth resistor R6 with 1kΩ, a seventh resistor R7 with 10kΩ, a second anti-static diode, and a ninth capacitor C9 with 100nf, one end of the program reset key is connected to one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the second anti-static diode, and one end of the ninth capacitor C9, the other end of the sixth resistor R6 is connected to the PA0 pin of the main control chip 1, the other end of the seventh resistor R7 is connected to the other end of the second anti-static diode together and then grounded, and the other end of the ninth capacitor C9 is connected to the other end of the program reset key and then grounded; in the program reset circuit 7, one end of a program reset key is connected in series with a sixth resistor R6 of 1KΩ and then is connected to a PA0 pin of the main control chip 1, the same end of the program reset key is connected with a seventh resistor R7 of 10KΩ in a pull-down mode and is grounded, two ends of the seventh resistor R7 of 10KΩ are connected with a second anti-static diode, two ends of the program reset key are connected with a ninth capacitor C9 of 100nf for eliminating jitter, the other end of the program reset key is connected with the ground, and the program reset circuit 7 is used for program reset in the main control chip 1.
It is to be understood that the above examples of the present utility model are provided by way of illustration only and are not intended to limit the scope of the utility model. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are desired to be protected by the following claims.
Claims (10)
1. The utility model provides a QCM binary channels vibrate collection system, its characterized in that, the device includes main control chip (1), QCM binary channels detection module (2), power supply circuit (3) and multi-device interaction module (4), power supply circuit (3) are connected with main control chip (1) and are used for supplying power, main control chip (1) are connected with QCM binary channels detection module (2) that are used for detecting the QCM signal, main control chip (1) still is connected with multi-device interaction module (4).
2. The QCM dual-channel oscillation acquisition device according to claim 1, wherein the QCM dual-channel detection module (2) comprises a first QCM probe (21), a first QCM detection circuit (22), a second QCM probe (23) and a second QCM detection circuit (24), the output end of the first QCM probe (21) is connected with the input end of the first QCM detection circuit (22), the output end of the first QCM detection circuit (22) is connected with the input end of the main control chip (1), the output end of the second QCM probe (23) is connected with the input end of the second QCM detection circuit (24), the output end of the second QCM detection circuit (24) is connected with the input end of the main control chip (1), and the model of the main control chip (1) is STM32F407ZGT6.
3. The QCM dual-channel oscillation acquisition device according to claim 2, wherein the first QCM detection circuit (22) includes a first detection chip, a first capacitor C1, a first resistor R1, a second resistor R2, a second capacitor C2 and a type-a interface, the model of the first detection chip is SN74LVC1GX04DBVR, the GND pin of the first detection chip is grounded, the X1 pin of the first detection chip is connected to one end of the first capacitor C1, one end of the first resistor R1 and the D-network pin of the type-a interface respectively, the other end of the first capacitor C1 is grounded, the d+ network pin of the type-a interface is connected to one end of the second resistor R2 and one end of the second capacitor C2 respectively, the other end of the second resistor R2 is grounded, the other end of the second resistor R2 is connected to the other end of the first resistor R1 and the X2 pin of the first detection chip respectively, the VCC power supply circuit (3) of the first detection chip is connected to the Y pin of the first detection chip and the first probe (5 pin of the first detection chip) is connected to the first probe (21-PA) and the two probe pins are connected to the first network pins (21-PA and the two probe interfaces respectively);
the second QCM detection circuit (24) comprises a second detection chip, a third capacitor C3, a third resistor R3, a fourth resistor R4, a fourth resistor C4 and a type-A interface, the second detection chip is the same as the first detection chip in type, GND pins of the second detection chip are grounded, X1 pins of the second detection chip are respectively connected with one end of the third capacitor C3, one end of the third resistor R3 and a D-network pin of the type-A interface, the other end of the third capacitor C3 is grounded, D+ network pins of the type-A interface are respectively connected with one end of the fourth resistor R4 and one end of the fourth resistor C4, the other end of the fourth resistor R4 is grounded, the other end of the fourth resistor R4 is respectively connected with the other end of the third resistor R3 and the X2 pins of the second detection chip, the VCC pins of the second detection chip are connected with the power circuit (3), Y pins of the second detection chip are connected with PE0 pins of the main control chip, and the second M probe (23) comprises two pins, and the two QCM probe (23) are respectively connected with the two network pins of the type-A interface.
4. The QCM dual-channel oscillation acquisition device according to claim 3, wherein the power supply circuit (3) comprises a first power supply chip with the model AMS1117, a fifth capacitor C5, a sixth capacitor C6, an LED diode and a fifth resistor R5, the VIN pin of the first power supply chip is connected to one end of the input power supply and the fifth capacitor C5 respectively, the other end of the fifth capacitor C5 is grounded, the VOUT pin of the first power supply chip is connected to the TAB pin of the first power supply chip, one end of the sixth capacitor C6 and the input end of the LED diode respectively, the TAB pin of the first power supply chip is connected to the VCC pin of the first detection chip and the VCC pin of the second detection chip respectively, the other end of the sixth capacitor C6 is commonly grounded after being connected to the ADJ pin of the first power supply chip, the output end of the LED diode is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded.
5. The QCM dual-channel oscillation acquisition device according to claim 4, wherein the multi-device interaction module (4) comprises an SPI interface circuit, a USART interface circuit, an IIC interface circuit, and a USB-CDC interface circuit in parallel, and the SPI interface circuit, USART interface circuit, IIC interface circuit, and USB-CDC interface circuit are bi-directionally connected with the main control chip (1).
6. The QCM dual-channel oscillation acquisition device according to claim 5, wherein the SPI interface circuit comprises an SPI interface with the model of KH-0.5-H3.25-6PIN, the 1 st PIN of the SPI interface is grounded, the 2 nd PIN of the SPI interface is connected with the PC12 PIN of the main control chip (1), the 3 rd PIN of the SPI interface is connected with the PC11 PIN of the main control chip (1), the 4 th PIN of the SPI interface is connected with the PC10 PIN of the main control chip (1), the 5 th PIN of the SPI interface is connected with the PA4 PIN of the main control chip (1), and the 6 th PIN of the SPI interface is connected with the TAB PIN of the first power supply chip;
the USART interface circuit comprises a USART interface with the model number of AFA07-S04ECA-00, wherein the 1 st pin of the USART interface is grounded, the 2 nd pin of the USART interface is connected with the PA10 pin of the main control chip (1), the 3 rd pin of the USART interface is connected with the PA9 pin of the main control chip (1), and the 4 th pin of the USART interface is connected with an input power supply;
the IIC interface circuit comprises an IIC interface with the model of AFA07-S04ECA-00, wherein the 1 st pin of the IIC interface is connected with the TAB pin of the first power supply chip, the 2 nd pin of the IIC interface is connected with the PB 6pin of the main control chip (1), the 3 rd pin of the IIC interface is connected with the PB7 pin of the main control chip (1), and the 4 th pin of the IIC interface is grounded;
the USB-CDC interface circuit comprises a USB-CDC interface chip with the model number of CH340C, a merco USB interface with the model number of 10103594-0001LF and a ninth capacitor C9,
the GND pin of the USB-CDC interface chip is grounded, the TXD pin of the USB-CDC interface chip is connected with the PA9 pin of the main control chip (1), the RXD pin of the USB-CDC interface chip is connected with the PA10 pin of the main control chip (1), the V3 pin of the USB-CDC interface chip is connected with the TAB pin of the first power supply chip, the VCC pin of the USB-CDC interface chip is respectively connected with one end of the ninth capacitor C9 and an input power supply, the other end of the ninth capacitor C9 is grounded,
the VCC pin of the merco USB interface is connected with an input power supply, the D+ network pin of the merco USB interface is connected with the D+ network pin of the USB-CDC interface chip, the D-network pin of the merco USB interface is connected with the D-network pin of the USB-CDC interface chip, and the GND pin of the merco USB interface and the EP pin of the merco USB interface are connected and then grounded together.
7. The QCM dual-channel vibration acquisition device according to claim 6, wherein the input power is input through a TYPE-C interface circuit or a USB-CDC interface circuit, the YPE-C interface circuit comprises a TYPE-C interface with a model of YPE-C-31-M-33, a GND pin of the TYPE-C interface is grounded, 4 EH pins of the TYPE-C interface are commonly connected and then grounded, and a VBUS pin of the TYPE-C interface is connected with the input power.
8. The QCM dual-channel oscillation acquisition device according to claim 7, further comprising a system support module (5), wherein the system support module (5) comprises a first filter circuit, a SWDIO interface circuit, a crystal oscillator circuit, a resistor pull-up circuit, a resistor pull-down circuit and a second filter circuit in parallel;
the first filter circuit comprises a plurality of first filter capacitors connected in parallel, each first filter capacitor C 1.1 One end of (2)The first filter capacitor C is respectively connected with the VDD pin, the VBAT pin and the VDDA pin of the main control chip (1) and then is commonly connected with the TAB pin of the first power supply chip 1.1 The other end of the pin is respectively connected with the VREF+ pin, the VSS pin and the VSSA pin of the main control chip (1) and then commonly grounded;
the SWDIO interface circuit comprises an SWDIO interface with the model number of AFA07-S04ECA-00, wherein the 1 st pin of the SWDIO interface is connected with the TAB pin of the first power supply chip, the 2 nd pin of the SWDIO interface is connected with the PA14 pin of the main control chip (1), the 3 rd pin of the SWDIO interface is connected with the PA13 pin of the main control chip (1), and the 4 th pin of the SWDIO interface is grounded;
the crystal oscillator circuit comprises a crystal oscillator, a seventh capacitor C7 and an eighth capacitor C8, wherein the 1 st pin of the crystal oscillator is respectively connected with one end of the seventh capacitor C7 and the PH0 pin of the main control chip (1), the other end of the seventh capacitor C7 is connected with the 2 nd pin of the crystal oscillator and then is grounded together, the 3 rd pin of the crystal oscillator is respectively connected with the PH1 pin of the main control chip (1) and one end of the eighth capacitor C8, and the other end of the eighth capacitor C8 is connected with the 4 th pin of the crystal oscillator and then is grounded together;
the resistor pull-up circuit comprises a pull-up resistor RA, one end of the pull-up resistor RA is connected with a BOOT0 pin of the main control chip (1), and the other end of the pull-up resistor RA is grounded;
the resistor pull-down circuit comprises a pull-down resistor RB, one end of the pull-down resistor RB is connected with a PDR_ON pin of the main control chip (1), and the other end of the pull-down resistor RB is connected with a TAB pin of the first power supply chip;
the second filter circuit comprises a second filter capacitor C 2.2 And a third filter capacitor C 3.3 The second filter capacitor C 2.2 One end of the second filter capacitor C is connected with the VCAP_1 pin of the main control chip (1) 2.2 And the other end of the third filter capacitor C 3.3 One end of the third filter capacitor C is connected to the common ground 3.3 The other end of the (C) is connected with the VCAP_2 pin of the main control chip (1).
9. The QCM dual-channel oscillation acquisition device according to claim 8, further comprising a power-down reset circuit (6), wherein the power-down reset circuit (6) comprises a power-down reset key, an 8 th resistor, a10 th capacitor and a first anti-static diode, one end of the power-down reset key is respectively connected with an NRST pin of the main control chip (1), one end of the 8 th resistor, one end of the 10 th capacitor and one end of the first anti-static diode, the other end of the 8 th resistor is connected with a TAB pin of the first power chip, and the other end of the power-down reset key is respectively connected with the other end of the 10 th capacitor and the other end of the first anti-static diode and then commonly grounded.
10. The QCM dual-channel oscillation acquisition device according to any one of claims 1 to 9, further comprising a program reset circuit (7), wherein the program reset circuit (7) comprises a program reset key, a sixth resistor R6, a seventh resistor R7, a second anti-static diode and a ninth capacitor C9, one end of the program reset key is respectively connected with one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the second anti-static diode and one end of the ninth capacitor C9, the other end of the sixth resistor R6 is connected with a PA0 pin of the main control chip (1), the other end of the seventh resistor R7 is commonly connected with the other end of the second anti-static diode and then grounded, and the other end of the ninth capacitor C9 is connected with the other end of the program reset key and then grounded.
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