CN202041493U - Humidity digital sensor circuit for I2C (Inter-Integrated Circuit) interface - Google Patents
Humidity digital sensor circuit for I2C (Inter-Integrated Circuit) interface Download PDFInfo
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- CN202041493U CN202041493U CN2011201077093U CN201120107709U CN202041493U CN 202041493 U CN202041493 U CN 202041493U CN 2011201077093 U CN2011201077093 U CN 2011201077093U CN 201120107709 U CN201120107709 U CN 201120107709U CN 202041493 U CN202041493 U CN 202041493U
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Abstract
The utility model discloses a humidity digital sensor circuit for an I2C (Inter-Integrated Circuit) interface, comprising an oscillating unit, a counting unit and an I2C interface unit, wherein the oscillating unit converts the electric capacity of a capacitive humidity sensor Cx into a frequency signal f; the counting unit counts the frequency signal f and latches binary count values B; the I2C interface unit collects the count values B and realizes an I2C bus interface; the output end of the oscillating unit is connected with the input end of the counting unit; and the output end of the counting unit is connected with the input end of the I2C interface unit. In the utility model, the digital devices such as a crystal oscillator, a frequency divider and a counter are adopted so that the measurement error is mainly from the stability of oscillating circuit and the measurement accuracy of the circuit is high without using a CPU (Central Processing Unit); and the circuit performance is stable and reliable. The humidity digital sensor circuit for the I2C interface is widely applied to industrial control field.
Description
Technical field
The utility model relates to a kind of sensor circuit, particularly a kind of condenser type humidity digital sensor circuit of I2C interface.Specifically be meant and after metering circuit conditioning and digitizing, adopt the I2C bus standard to carry out numeral output humidity sensor, realize the digitizing of sensor signal.
Background technology
I2C (Inter-Integrated Circuit) bus is a kind of twin wire universal serial bus by the exploitation of PHILIPS company, is used to connect microcontroller and peripherals thereof.The topmost advantage of I2C bus is its simplicity and validity.Because interface is directly on assembly, so I2C bus occupation space is very little, has reduced the space of circuit board and the quantity of chip pin, has reduced interconnected cost, the I2C device directly can be inserted on the I2C bus easily and form digital network.
Humidity sensor is the measuring unit of humidity parameter, present humidity sensor generally is with the original physical quantity of its sensor such as electric capacity, resistance output, or the employing standard becomes feed signals output as 1～5V output (above-mentioned general designation simulation output transducer), the sensor of simulation output must connect front end circuit in use, then also needs digitizer when inserting digital display circuit (as the computer management measuring system); Humidity sensor is also arranged or export with frequency, or with self-defining numeral output as similar but not exclusively compatible I2C two-wire system numeral output (above-mentioned title digital output sensors), but these digital output sensors are still restricted in use, can not simply be applied to digital display circuit.
The utility model content
In order to solve above-mentioned technical matters, the purpose of this utility model provide a kind of practicality, reliable, accurately, the humidity digital sensor circuit of I2C interface that cost performance is high.
The technical scheme that its technical matters that solves the utility model adopts is:
A kind of humidity digital sensor circuit of I2C interface comprises:
Oscillating unit, oscillating unit is converted to frequency signal f to the electric capacity of capacitance type humidity sensor Cx;
Counting unit, counting unit is counted frequency signal f, and B latchs with the binary counting value;
I2C interface unit, I2C interface unit gather and realize the I2C bus interface to count value B;
The output terminal of oscillating unit is connected with the input end of counting unit, and the output terminal of counting unit is connected with the input end of I2C interface unit.
Be further used as preferred embodiment, described oscillating unit comprises operational amplifier, resistance, electric capacity, the parallel circuit that the positive power source terminal of described operational amplifier U11 is formed by resistance R 21 and capacitor C 21 successively, be connected with ground behind the parallel circuit of resistance R 22 and capacitor C 22 compositions, the tie point of described resistance R 21 and resistance R 22 is by capacitor C 20, resistance R 2 is connected with the inverting input of operational amplifier U11, tie point also is connected with the in-phase input end of operational amplifier U11 by the parallel circuit that resistance R 4 and capacitor C 4 are formed, the output terminal of operational amplifier U11 is connected with its inverting input by resistance R 1, and the output terminal of operational amplifier U11 is by capacitor C x, resistance R 3 is connected with its in-phase input end.
Be further used as preferred embodiment, the power input of described operational amplifier U11 connects the output terminal of reference voltage chip U12, is the power supply of single supply type.
Be further used as preferred embodiment, described resistance R 3 is the resistance of low-temperature coefficient.
Be further used as preferred embodiment, described I2C interface unit is the GPIO device U31 that possesses the I2C interface, and its input end is connected with the output terminal of counting unit.
Be further used as preferred embodiment, described counting unit comprises n level frequency divider, counter and latch, one input end of described counter is connected with the output terminal of n level frequency divider, another input end is connected with survey frequency f, the output terminal of described counter is connected with the input end of latch, and the input end of n level frequency divider is connected with reference frequency f0.
Be further used as preferred embodiment, described counting unit comprises n level frequency divider, counter and latch, one input end of described counter is connected with the output terminal of n level frequency divider, another input end is connected with reference frequency f0, the output terminal of described counter is connected with the input end of latch, and the input end of n level frequency divider is connected with survey frequency f.
Be further used as preferred embodiment, described counting unit comprise n level frequency divider U21, counter U22, latch U23, active crystal oscillator U24, with a door U25, the input end of n level frequency divider U21 is connected with the output terminal of active crystal oscillator U24,2 of n level frequency divider U21
n The input end of clock CLK of frequency division end and latch U23 be connected 2 of n level frequency divider U21 with the input end of door U25
N-1 The frequency division end be connected with another input end of door U25, be connected with the RESET input RST of counter U22 with the output terminal of door U25, the input end of clock of counter U22 is connected with the output terminal of operational amplifier U11.
Be further used as preferred embodiment, described counting unit comprise n level frequency divider U21, counter U22, latch U23, active crystal oscillator U24, with a door U25, the input end of n level frequency divider U21 is connected with the output terminal of operational amplifier U11,2 of n level frequency divider U21
n The input end of clock CLK of frequency division end and latch U23 be connected 2 of n level frequency divider U21 with the input end of door U25
N-1 The frequency division end be connected with another input end of door U25, be connected with the RESET input RST of counter U22 with the output terminal of door U25, the input end of clock of counter U22 is connected with the output terminal of active crystal oscillator U24.
The beneficial effects of the utility model are: the utility model has used digital devices such as crystal oscillator, frequency divider sum counter, make measuring error be mainly derived from the stability of oscillatory circuit, the accuracy of measurement height of circuit, and do not need CPU, circuit performance is stable, reliable.
The utility model adopts the Wien bridge circuit oscillatory circuit of single power supply, directly uses the power supply in the I2C bus, does not need extra power supply, uses simple, convenient.
Adopt the power supply of reference voltage source, ensured the stability of oscillation frequency, improved accuracy of measurement as operational amplifier in the Wien bridge circuit oscillatory circuit.
In the Wien bridge circuit oscillatory circuit in the RC connection in series-parallel frequency selection network resistance in series adopted the resistance of low-temperature coefficient, ensured the temperature stability of oscillation frequency, improved accuracy of measurement.
The embodiment of two kinds of counting units is applicable to different surge frequency ranges respectively, can cover the needs of dissimilar capacitance type humidity sensors, and application is strong.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples.
Fig. 1 is a circuit structure block diagram of the present utility model;
Fig. 2 is the circuit theory diagrams of oscillating unit;
Fig. 3 is the theory diagram scheme one of counting unit;
Fig. 4 is the theory diagram scheme two of counting unit;
Fig. 5 is the circuit theory diagrams scheme one of counting unit;
Fig. 6 is the circuit theory diagrams scheme two of counting unit;
Fig. 7 is the circuit theory diagrams of I2C interface unit.
Embodiment
A kind of humidity digital sensor circuit of I2C interface, its circuit structure block diagram comprise oscillator unit (1), counting unit (2), I2C interface unit (3) as shown in Figure 1.Oscillating unit is that the capacitance signal relevant with humidity with capacitance type humidity sensor Cx is converted to correspondent frequency signal f, counting unit is aforementioned frequency signal f to be carried out count measurement obtain binary count value B and latch, the I2C interface unit is to adopt the GPIO device of I2C interface to sample and realize the digitizing of I2C bus realizing the measurement of humidity value aforementioned binary counting value B.
The utility model provides further refinement circuit, and oscillating unit is made up of Wien bridge circuit oscillatory circuit, reference voltage chip, and the electric capacity of capacitance type humidity sensor Cx is converted to frequency signal f; The circuit theory diagrams of oscillating unit as shown in Figure 2, by resistance R 1, R2, R21, R22, R4, low-temperature coefficient resistance R 3, electrochemical capacitor C21, C22, capacitor C 20, C4, reference voltage chip U12 and capacitance type humidity sensor Cx form.Wherein resistance R 3, R4, capacitor C 4 and capacitance type humidity sensor Cx constitute the RC connection in series-parallel frequency selection network of Wien bridge circuit oscillatory circuit, the output terminal of the outer termination operational amplifier U11 of RC series circuit R3, the Cx of frequency selection network, the mid point of frequency selection network connects the in-phase input end of operational amplifier U11, the mid point of the bleeder circuit that the outer termination of RC parallel circuit R4, the C4 of frequency selection network is made up of resistance R 21, R22 and electrochemical capacitor C21, C22, these bleeder circuit two ends connect power end and the ground of operational amplifier U11 respectively; Resistance R 1 connects inverting input and the output terminal of operational amplifier U11; Resistance R 2 connects the inverting input of operational amplifier U11, and the other end connects the mid point of bleeder circuit by capacitor C 20; For guaranteeing the stability of oscillator oscillation frequency under different temperatures, resistance R 3 is used 10ppm/ ℃ low-temperature coefficient resistance.Operational amplifier U11 is the single supply type, its power supply is provided by reference voltage chip U12, electric power thus supplied based on the I2C bus, the reference voltage of reference voltage chip U12 is 3.3V or 4.096V, operational amplifier U11 is the single supply device, by R21, C21 and R22, C22 power supply is carried out dividing potential drop, as the floating ground of oscillator; The design oscillation frequency of oscillator need be considered the parameter of capacitance type humidity sensor Cx, wherein the capacitance of capacitor C 4 is got the capacitance of the pairing humidity sensor Cx of intermediate value humidity that can measure humidity range, with the HS1101 humidity sensor is example, and capacitor C 4 is got 180pF.
Counting unit has two kinds of implementations: scheme one is to produce a standard-frequency signal f0 by the standard-frequency signal generator as shown in Figure 3, and standard-frequency signal f0 is carried out 2
n Obtain a standard sample cycle that is fit to behind the frequency division, the frequency signal f that in this cycle oscillating unit is produced counts to get binary count value B.Scheme two is that the frequency signal f that oscillating unit produces is carried out 2 as shown in Figure 4
n Obtain a sampling period that is fit to behind the frequency division, in this cycle, the standard-frequency signal f0 that is produced by the standard-frequency signal generator is counted to get binary count value B.
Counting unit is made up of standard-frequency signal generator, n level frequency divider, counter, latch and logic control circuit, and this unit is output as the binary counting value B after latching.The standard-frequency signal generator produces standard-frequency signal f0; N level frequency divider is used for frequency signal f or standard-frequency signal f0 that oscillating unit produces are carried out 2
n Frequency division is to produce a suitable sampling time T=2
N-1 / f or T=2
N-1 / f0 is used to count the control in sampling period; Counter is standard-frequency signal f0 or the frequency signal f relevant with sensor to be counted in the sampling period at the counting of aforementioned generation, and presses scale-of-two output count value; Latch is used for the latching of final count value B of above-mentioned generation, and logic control circuit is used to produce latch control signal sum counter reset signal.Counting unit is by n level frequency divider U21, counter U22 during specific implementation, D-latch U23, and active crystal oscillator U24 forms with door U25.
According to different accuracies of measurement, counter U22, latch U23 may need a plurality of requirements that could satisfy the binary counting figure place.Is example to require the moisture measurement accuracy for ± 1%, considers the distribution of error source, and the circuit measuring accuracy requirement is ± 0.2%.With the HS1101 humidity sensor is example, the capacitance of its humidity full scale (100%RH) is 205pF, effectively the capacitance in the moisture measurement scope is 160～205pF, for guaranteeing that the circuit measuring accuracy requirement is ± 0.2%, the capacitance measurement accuracy requirement of circuit need be at least ± and 0.04%, promptly 1/2500, then require count value to be at least 2500, be 12 binary counting values, so counter U22, latch U23 is at least 12, as the binary counter of 1 12 of needs and 26 D-latch, the frequency range of the also essential consideration oscillatory circuit of concrete figure place and the frequency division value of n level frequency divider U21.
Embodiment one its circuit theory diagrams as shown in Figure 5, the clock end of n level frequency divider U21 is connected to the frequency signal output terminal of source crystal oscillator U24,2 of n level frequency divider U21
n The clock end of frequency division termination latch U23 also meets the input end with door U25,2 of n level frequency divider U21 simultaneously
N-1 Another input end of frequency division termination and door U25 is with (zero clearing) end that resets of the output termination counter U22 of door U25; The output terminal of the clock termination operational amplifier U11 of counter U22, each output terminal correspondence of counter U22 connects each input end of latch U23.
Its technical scheme is: with n level frequency divider U21 the standard-frequency signal f0 that active crystal oscillator U24 produces is carried out 2
n Frequency division, and produce one 2 simultaneously
n-1
Fractional frequency signal, 2
n The clock end that fractional frequency signal meets D-latch U23 is used for latching of count value, 2
n-1
Fractional frequency signal and 2
n Fractional frequency signal is used for resetting of counter as producing (zero clearing) end that resets that a logical signal meets counter U22 with the input end of door U25; The clock end that the frequency signal f that oscillating unit produces meets counter U22 is used for counting; The count value of counter U22 connects the input end of D-latch U23; The output terminal of D-latch U23 is the binary counting value B after latching.
Connect example, the oscillating unit that is 50kHz with minimum design oscillation frequency is an example, and the frequency of active crystal oscillator U24 is got 32.768kHz, be to realize at least 2500 count values to 50kHz oscillation frequency f, then 2
n The frequency division post-sampling time can not be shorter than 50ms, and then the frequency division frequency n is at least 12, makes T=2
N-1 / f0=2
12-1 / 32.768kHz=62.5ms.This scheme, oscillation frequency f is high more, and then the frequency division frequency n is more little, and it is easy more that n level frequency divider U21 selects; Oscillation frequency f is low more, and then the frequency division frequency n is big more, and n level frequency divider U21 selects difficult more.
Embodiment two its circuit theory diagrams as shown in Figure 6, the output terminal of the clock termination operational amplifier U11 of n level frequency divider U21,2 of n level frequency divider U21
n The clock end of frequency division termination latch U23 also meets the input end with door U25,2 of n level frequency divider U21 simultaneously
N-1 Another input end of frequency division termination and door U25 is with (zero clearing) end that resets of the output termination counter U22 of door U25; The clock end of counter U22 is connected to the frequency signal output terminal of source crystal oscillator U24, and each output terminal correspondence of counter U22 connects each input end of latch U23.
Its technical scheme is: with n level frequency divider U21 the frequency signal f that oscillating unit produces is carried out 2
n Frequency division, and produce one 2 simultaneously
n-1
Fractional frequency signal, 2
n The clock end that fractional frequency signal meets D-latch U23 is used for latching of count value, 2
n-1
Fractional frequency signal and 2
n Fractional frequency signal is used for resetting of counter as producing (zero clearing) end that resets that a logical signal meets counter U22 with the input end of door U25; The clock end that the standard-frequency signal f0 that active crystal oscillator produces meets counter U22 is used for counting; The count value of counter U22 connects the input end of D-latch U23; The output terminal of D-latch U23 is the binary counting value B after latching.
Connect example, the oscillating unit that is 5kHz with the highest design oscillation frequency is an example, and the frequency of active crystal oscillator U24 is got 1MHz, be to realize at least 2500 count values to 1MHz standard-frequency signal f0, then 2
n The frequency division post-sampling time can not be shorter than 2.5ms, and then the frequency division frequency n is at least 5, makes T=2
N-1 / f=2
5-1 / 5kHz=3.2ms.This scheme, oscillation frequency f is high more, and then the frequency division frequency n is high more, and n level frequency divider U21 selects difficult more; Oscillation frequency f is low more, and then the frequency division frequency n is more little, and it is easy more that n level frequency divider U21 selects.
Its circuit theory diagrams of I2C interface unit are made up of the I/O extender of I2C interface as shown in Figure 7, realize that the binary counting value B that counting unit is produced is a digital signal by the I2C interface conversion.The I2C interface unit is made up of the GPIO device U31 of I2C interface, its figure place is consistent with the figure place of latch U23, therefore may need a plurality ofly, it respectively imports each output terminal of D-latch U23 in the termination counting unit, realizes the digitizing of I2C bus by the I2C bus port of U31.
The power supply of circuit only need use the power supply that provides in the I2C bus.
More than be that preferable enforcement of the present utility model is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of the utility model spirit, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.
Claims (9)
1. the humidity digital sensor circuit of an I2C interface is characterized in that: comprising:
Oscillating unit (1), oscillating unit is converted to frequency signal f to the electric capacity of capacitance type humidity sensor Cx;
Counting unit (2), counting unit is counted frequency signal f, and B latchs with the binary counting value;
I2C interface unit (3), I2C interface unit gather and realize the I2C bus interface to count value B;
The output terminal of oscillating unit (1) is connected with the input end of counting unit (2), and the output terminal of counting unit (2) is connected with the input end of I2C interface unit (3).
2. the humidity digital sensor circuit of a kind of I2C interface according to claim 1, it is characterized in that: described oscillating unit (1) comprises operational amplifier (U11), resistance (R1-R4, R21, R22), electric capacity (Cx, C4, C20, C21, C22), the parallel circuit that the positive power source terminal of described operational amplifier U11 is formed by resistance R 21 and capacitor C 21 successively, be connected with ground behind the parallel circuit of resistance R 22 and capacitor C 22 compositions, the tie point of described resistance R 21 and resistance R 22 is by capacitor C 20, resistance R 2 is connected with the inverting input of operational amplifier U11, tie point also is connected with the in-phase input end of operational amplifier U11 by the parallel circuit that resistance R 4 and capacitor C 4 are formed, the output terminal of operational amplifier U11 is connected with its inverting input by resistance R 1, and the output terminal of operational amplifier U11 is by capacitor C x, resistance R 3 is connected with its in-phase input end.
3. the humidity digital sensor circuit of a kind of I2C interface according to claim 2 is characterized in that: the power input of described operational amplifier U11 connects the output terminal of reference voltage chip U12, is the power supply of single supply type.
4. the humidity digital sensor circuit of a kind of I2C interface according to claim 2 is characterized in that: described resistance R 3 is the resistance of low-temperature coefficient.
5. the humidity digital sensor circuit of a kind of I2C interface according to claim 1 is characterized in that: described I2C interface unit (3) is for possessing the GPIO device U31 of I2C interface, and its input end is connected with the output terminal of counting unit (2).
6. the humidity digital sensor circuit of a kind of I2C interface according to claim 2, it is characterized in that: described counting unit (2) comprises n level frequency divider, counter and latch, one input end of described counter is connected with the output terminal of n level frequency divider, another input end is connected with survey frequency f, the output terminal of described counter is connected with the input end of latch, and the input end of n level frequency divider is connected with reference frequency f0.
7. the humidity digital sensor circuit of a kind of I2C interface according to claim 2, it is characterized in that: described counting unit (2) comprises n level frequency divider, counter and latch, one input end of described counter is connected with the output terminal of n level frequency divider, another input end is connected with reference frequency f0, the output terminal of described counter is connected with the input end of latch, and the input end of n level frequency divider is connected with survey frequency f.
8. the humidity digital sensor circuit of a kind of I2C interface according to claim 6, it is characterized in that: described counting unit (2) comprise n level frequency divider U21, counter U22, latch U23, active crystal oscillator U24, with a door U25, the input end of n level frequency divider U21 is connected with the output terminal of active crystal oscillator U24,2 of n level frequency divider U21
n The input end of clock CLK of frequency division end and latch U23 be connected 2 of n level frequency divider U21 with the input end of door U25
N-1 The frequency division end be connected with another input end of door U25, be connected with the RESET input RST of counter U22 with the output terminal of door U25, the input end of clock of counter U22 is connected with the output terminal of operational amplifier U11.
9. the humidity digital sensor circuit of a kind of I2C interface according to claim 7, it is characterized in that: described counting unit (2) comprise n level frequency divider U21, counter U22, latch U23, active crystal oscillator U24, with a door U25, the input end of n level frequency divider U21 is connected with the output terminal of operational amplifier U11,2 of n level frequency divider U21
n The input end of clock CLK of frequency division end and latch U23 be connected 2 of n level frequency divider U21 with the input end of door U25
N-1 The frequency division end be connected with another input end of door U25, be connected with the RESET input RST of counter U22 with the output terminal of door U25, the input end of clock of counter U22 is connected with the output terminal of active crystal oscillator U24.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201077093U CN202041493U (en) | 2011-04-13 | 2011-04-13 | Humidity digital sensor circuit for I2C (Inter-Integrated Circuit) interface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011201077093U CN202041493U (en) | 2011-04-13 | 2011-04-13 | Humidity digital sensor circuit for I2C (Inter-Integrated Circuit) interface |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016112720A1 (en) * | 2015-01-13 | 2016-07-21 | 合肥工业大学 | Low-power-consumption capacitive sensor interface circuit |
| CN114325091A (en) * | 2022-01-06 | 2022-04-12 | 南京海兴电网技术有限公司 | Binary output power grid frequency measuring circuit and method |
-
2011
- 2011-04-13 CN CN2011201077093U patent/CN202041493U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016112720A1 (en) * | 2015-01-13 | 2016-07-21 | 合肥工业大学 | Low-power-consumption capacitive sensor interface circuit |
| CN114325091A (en) * | 2022-01-06 | 2022-04-12 | 南京海兴电网技术有限公司 | Binary output power grid frequency measuring circuit and method |
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Granted publication date: 20111116 |