CN211150512U - Fan-out type three-dimensional packaging structure - Google Patents
Fan-out type three-dimensional packaging structure Download PDFInfo
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- CN211150512U CN211150512U CN201922334454.3U CN201922334454U CN211150512U CN 211150512 U CN211150512 U CN 211150512U CN 201922334454 U CN201922334454 U CN 201922334454U CN 211150512 U CN211150512 U CN 211150512U
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- 238000004806 packaging method and process Methods 0.000 title abstract description 49
- 239000004033 plastic Substances 0.000 claims abstract description 67
- 239000000463 material Substances 0.000 claims abstract description 65
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000002390 adhesive tape Substances 0.000 claims abstract description 19
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229920006335 epoxy glue Polymers 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 122
- 239000003292 glue Substances 0.000 description 14
- 239000010949 copper Substances 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000000227 grinding Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000005553 drilling Methods 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000010944 silver (metal) Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- 230000002452 interceptive effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses a fan-out type three-dimensional packaging structure, which comprises an embedded material, wherein a first through hole and a second through hole which penetrate through the embedded material along the thickness direction of the embedded material are arranged on the embedded material at intervals; the first chip and the conductive column are packaged in the first plastic package layer, and the front surface of the first chip faces the first plastic package layer; the second plastic package layer and the second chip are positioned on one side of the embedded material, the back surface of the second chip is bonded with the back surface of the first chip through a double-sided adhesive tape, an I/O interface of the second chip is connected with the conductive column through a lead, and the second chip is packaged in the second plastic package layer; and the metal bump is connected with the I/O interface and the conductive column of the first chip through the electric connection structure. The utility model discloses effectively reduced three-dimensional packaging structure's of fan-out type encapsulation height and manufacturing cost.
Description
Technical Field
The utility model relates to a fan-out type encapsulation technical field, concretely relates to fan-out type packaging structure's preparation method and adopt the three-dimensional packaging structure of fan-out type that this method made.
Background
In recent years, advanced packaging technology has been developed in the IC manufacturing industry, for example, multi-chip module (MCM) packages a plurality of IC chips according to functional combinations, and especially three-dimensional (3D) packages break through the concept of conventional planar packaging with an assembly efficiency as high as 200%. Firstly, a plurality of chips can be stacked in a single package body, so that the multiplication of storage capacity is realized, and the package is called as a stacked 3D package in the industry; secondly, the chips are directly interconnected, the length of an interconnecting wire is obviously shortened, the signal transmission is faster, and the interference is smaller; moreover, a plurality of chips with different functions are stacked together, so that a single packaging body realizes more functions, thereby forming a new idea of packaging the system chip; finally, the chip adopting the 3D packaging has the advantages of low power consumption, high speed and the like. In summary, three-dimensional packaging can reduce the size and weight of electronic information products by tens of times.
However, in the three-dimensional stacking and packaging technology, the chip is often placed on the film substrate during stacking, then the film substrate is stacked, the packaging height is high, and meanwhile, in the interconnection aspect of I/O interfaces, the cost for establishing an RD L layer is high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a fan-out type packaging structure that encapsulation height and encapsulation cost all reduced.
To achieve the purpose, the utility model adopts the following technical proposal:
provided is a fan-out type three-dimensional packaging structure, including:
the embedded material is provided with a first through hole and a second through hole which penetrate through the embedded material along the thickness direction of the embedded material at intervals;
the first chip and the conductive column are packaged in the first plastic package layer, and the front surface of the first chip faces the first plastic package layer;
the back surface of the second chip is bonded with the back surface of the first chip through a double-sided adhesive tape, an I/O interface of the second chip is connected with the conductive post through a lead, and the second chip is packaged in the second plastic package layer;
and the metal bump is connected with the I/O interface of the first chip and the conductive column through an electric connection structure.
As a preferable scheme of the fan-out three-dimensional package structure, the first plastic package layer is provided with a blind hole through which the I/O interface of the first chip and one end of the conductive post are exposed, the electrical connection structure includes a seed layer located in the blind hole and on the first plastic package layer and a redistribution layer located on the seed layer, and the metal bump is welded to the pad region of the redistribution layer.
As a preferable scheme of the fan-out three-dimensional packaging structure, the seed layer and the rewiring layer are provided with graphical holes for exposing part of the first plastic packaging layer;
the dielectric layer is attached to the non-pad area of the redistribution layer and the patterned hole.
As a preferable scheme of the fan-out type three-dimensional packaging structure, the dielectric layer is ABF or PI material.
As a preferable scheme of the fan-out three-dimensional packaging structure, the conductive posts are made of any one of Cu, Ag, or Au.
As a preferable scheme of the fan-out three-dimensional packaging structure, the double-sided adhesive tape is DAF or epoxy resin glue.
As a preferable scheme of the fan-out type three-dimensional packaging structure, the embedded material is FR4, FR5 or BT material.
The utility model has the advantages that: the utility model discloses bond two kinds of chips back to back, pile up and encapsulate, reduced the three-dimensional packaging structure's of fan-out type encapsulation height effectively, adopt the mode of beating the lead wire to carry out the interconnection to the higher chip of IO interface density simultaneously, reduced the three-dimensional packaging structure's of fan-out type manufacturing cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a flowchart of a manufacturing method of a fan-out three-dimensional package structure according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a specific step of step S7 according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of the buried material after being perforated according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view of the embedding material attached to the carrier tape according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view of the embedded material after the first chip is mounted and the conductive post is implanted.
Fig. 6 is a cross-sectional view of the embedded material after the first plastic sealing layer is formed thereon according to an embodiment of the present invention.
Fig. 7 is a cross-sectional view of the embedded material with a second chip attached and a lead wire bonded thereon according to an embodiment of the present invention.
Fig. 8 is a cross-sectional view of the embedded material after a second plastic sealing layer is formed thereon according to an embodiment of the present invention.
Fig. 9 is a cross-sectional view of a buried material with a seed layer and a redistribution layer formed thereon according to an embodiment of the present invention.
Fig. 10 is a cross-sectional view of a dielectric layer after a metal bump is implanted according to an embodiment of the invention.
Fig. 11 is a cross-sectional view of a fan-out three-dimensional package structure according to an embodiment of the invention.
In the figure:
1. a buried material; 1-1, a first through hole; 1-2, a second through hole; 2. a first chip; 3. a conductive post; 4. a first plastic packaging layer; 5. a second chip; 6. a lead wire; 7. a second plastic packaging layer; 8. an electrical connection structure; 9. a metal bump; 10. a first carrier gel; 11. a dielectric layer; 12. a second carrier glue; 13. and a third bearing glue.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments with reference to the accompanying drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; for a better understanding of the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are used only for illustrative purposes and are not to be construed as limiting the present patent, and the specific meaning of the terms will be understood by those skilled in the art according to the specific circumstances.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being either a fixed connection, a detachable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1, the embodiment provides a method for manufacturing a fan-out three-dimensional package structure, including the following steps:
s1, providing an embedding material 1, forming a first through hole 1-1 and a second through hole 1-2 penetrating the embedding material 1 along the thickness direction on the embedding material 1, wherein the embedded material 1 after being formed with the holes is shown in fig. 3; then, a first carrier paste 10 is attached to one side of the embedded material 1 along the thickness direction thereof, as shown in fig. 4, so as to preliminarily fix the first chip 2 in the first through hole 1-1 and implant the conductive pillar 3. Optionally, the buried material 1 is FR4, FR5 or BT material; specifically, a first through hole 1-1 is formed in the embedded material 1 according to the size of a first chip 2 to be packaged, and then a second through hole 1-2 is formed according to the implantation position of the conductive post 3;
s2, providing a first chip 2, mounting the first chip 2 in the first through hole 1-1, and implanting a conductive pillar 3 in the second through hole 1-2, as shown in fig. 5; the first chip 2 can be preliminarily fixed in the first through hole 1-1 through the first bearing glue 10, and the conductive column 3 is inserted into the second through hole 1-2 and preliminarily fixed through the first bearing glue 10; optionally, the material of the conductive column 3 is copper, silver, gold or nichrome;
s3, performing plastic encapsulation on the side of the embedded material 1 close to the front surface of the first chip 2 by using a plastic encapsulation material, and forming a first plastic encapsulation layer 4 covering the embedded material 1, the first chip 2, and the conductive pillars 3, as shown in fig. 6; specifically, the first molding compound layer 4 covers the first chip 2, the conductive pillars 3, and all surfaces of the buried material 1 away from the back surface of the first chip 2.
S4, removing the first bearing glue 10, overturning the first plastic package layer 4, and fixing the overturned first plastic package layer 4; specifically, the first plastic package layer 4 is fixed on the bearing platform through the second bearing glue 12;
s5, providing a second chip 5, attaching the second chip 5 to the back surface of the first chip 2, making the front surface of the second chip 5 face the side away from the first chip 2, and connecting the I/O interface of the second chip 5 and the conductive pillar 3 by using the lead 6, as shown in fig. 7;
s6, performing plastic package on the side of the embedding material 1 away from the first plastic package layer 4 by using a plastic package material, and forming a second plastic package layer 7 covering the embedding material 1, the second chip 5 and the leads 6, as shown in fig. 8; the second molding compound 7 is located on one side of the embedding material 1 close to the back side of the first chip 2 and covers the second chip 5 and the leads 6.
S7, forming a seed layer and a redistribution layer on the first molding compound layer 4, and implanting a metal bump 9 in the pad region of the redistribution layer, as shown in fig. 9 and 10. Optionally, the metal bump 9 is a solder, a silver solder or a gold-tin alloy solder, and in this embodiment, a solder ball made of a solder is preferred, and the solder ball is solder-implanted in the pad region of the redistribution layer to electrically lead out the first chip 2 and the second chip 5; specifically, before the seed layer is manufactured, the package after the secondary plastic package needs to be turned over again, and the package is mounted and fixed on the carrying platform through the third carrying glue 13, as shown in fig. 9, one side of the second plastic package layer 7, which is far away from the first plastic package layer 4, is mounted and fixed on the carrying platform through the third carrying glue 13.
After the third carrier paste 13 is removed, the fan-out three-dimensional package structure shown in fig. 11 is obtained.
Optionally, the material of the package material includes polyimide, silicone, and EMC (Epoxy Molding Compound), and the EMC is preferred in this embodiment, which can improve the stability of the package structure of the first chip 2 and the second chip 5, and play a role in protecting the chips.
In the present embodiment, unless otherwise specified, the term "cover" refers to an outer surface that surrounds a component without contacting other components.
In the embodiment, the first through hole 1-1 and the second through hole 1-2 are formed in the embedded material 1, the first chip 2 is installed in the first through hole 1-1, the conductive column 3 is implanted in the second through hole 1-2, and the first chip 2 is packaged by adopting a plastic package material, so that the packaging height of the first chip 2 is reduced, then the second chip 5 is attached to the back surface of the first chip 2 in a back-to-back manner, and the I/O interface of the second chip 5 and the conductive column 3 are electrically connected by adopting a lead bonding mode for packaging, so that the electroplating time is saved; and finally, leading out the electric signals of the first chip 2 and the second chip 5 through the metal bumps 9. Compared with the prior art, the packaging height and the production cost of the fan-out type three-dimensional packaging structure are effectively reduced.
In step S2 of the present embodiment, the first chip 2 is a thinned chip, and the back surface of the first chip has a double-sided adhesive tape, the first carrier tape 10 is removed after the first plastic package layer 4 is formed by plastic package, and then the second chip 5 in step S5 is attached to the back surface of the first chip 2 by the double-sided adhesive tape.
Specifically, the first chip 2 in step S2 is subjected to thinning processing by the following steps:
providing a wafer, attaching a grinding adhesive tape to the front side of the wafer, and then grinding and thinning the back side of the wafer;
and removing the grinding adhesive tape, attaching a double-sided adhesive tape for scribing on the back surface of the wafer, and scribing the thinned wafer by using wafer scribing equipment.
When the laser scribing equipment is adopted to scribe the wafer, the wafer needs to be subjected to wafer expansion.
As shown in fig. 2, step S7 specifically includes the following steps:
s71, respectively forming blind holes in the first plastic package layer 4 at positions corresponding to the I/O interface of the first chip 2 and the conductive posts 3 by using laser drilling equipment, so that the I/O interface of the first chip 2 and the conductive posts 3 are exposed;
s72, forming a seed layer on one side of the first plastic package layer 4 far away from the second plastic package layer 7 and the blind holes by adopting vacuum sputtering treatment; specifically, the seed layer comprises a titanium metal layer located on the surfaces of the first plastic package layer 4 and the blind holes and a copper metal layer located on the titanium metal layer and filling the blind holes. The titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the first plastic package layer 4 through the titanium metal layer. Of course, the seed layer in this embodiment is not limited to a two-layer structure (titanium metal layer, copper metal layer), and may have a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The material of the seed layer is not limited to the stacking combination of two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer can be stably attached to the package structure, and details are not repeated.
S73, manufacturing a rewiring layer on the seed layer;
s74, attaching the dielectric layer 11 on the redistribution layer and the surface of the first plastic package layer 4 exposed out of the seed layer and the redistribution layer, and opening the dielectric layer 11 to expose the pad area of the redistribution layer; optionally, the dielectric layer 11 is made of ABF (Ajinomoto Build-up Film) or PI (polyimide), and is attached to the first molding compound layer 4 and the non-pad area of the redistribution layer, so as to perform the insulating and protecting functions.
And S75, providing the metal bump 9, and welding and implanting the metal bump 9 into the pad area of the redistribution layer.
Wherein, step S63 specifically includes: and sequentially carrying out electroplating, dry film pasting, exposure, development and flash etching treatment on the first plastic sealing layer 4 to obtain a rewiring layer.
More specifically, step S63 includes the steps of:
s63a, manufacturing a copper plating layer on the seed layer through electroplating treatment;
s63b, providing a dry film, and attaching the dry film to the copper plating layer;
s63c, carrying out exposure and development treatment on the dry film to form a patterned hole exposing part of the copper plating layer;
and S63d, carrying out flash etching treatment on the copper plating layer exposed out of the patterned holes and the seed layer below the copper plating layer to obtain a rewiring layer, namely an RD L layer.
More specifically, the preparation method of the fan-out three-dimensional packaging structure of the embodiment includes the following steps:
s10, providing an embedded material 1, and forming a first through hole 1-1 and a second through hole 1-2 in the embedded material 1;
s20, attaching a first carrier tape 10 to a carrier platform of a placement machine, then attaching the embedding material 1 to the first carrier tape 10,
s30, providing a wafer, attaching a grinding adhesive tape on the front surface of the wafer, and then grinding and thinning the back surface of the wafer; removing the grinding adhesive tape, attaching a double-sided adhesive tape for scribing on the back surface of the wafer, and scribing the thinned wafer by using wafer scribing equipment to obtain a thinned first chip 2; the first chip 2 is attached in the first through hole 1-1, and the conductive column 3 is electroplated and implanted in the second through hole 1-2;
s40, plastic packaging is carried out on one side, close to the front side of the first chip 2, of the embedded material 1 by adopting a plastic packaging material to form a first plastic packaging layer 4 covering the embedded material 1, the first chip 2 and the conductive column 3, and a primary plastic packaging part is manufactured;
s50, removing the first bearing glue, turning over the primary plastic package piece, attaching a second bearing glue 12 to a bearing platform of the chip mounter, and attaching the primary plastic package piece to the second bearing glue 12;
s60, providing a second chip 5, attaching the second chip 5 to the back surface of the first chip 2, making the front surface of the second chip 5 face the side away from the first chip 2, and connecting the I/O interface of the second chip 5 and the conductive pillar 3 by using a lead 6;
s60, plastic packaging is carried out on one side, far away from the first plastic packaging layer 4, of the embedded material 1 by adopting a plastic packaging material to form a second plastic packaging layer 7 covering the embedded material 1, the second chip 5 and the lead 6, and a secondary plastic packaging part is manufactured;
s70, overturning the secondary plastic package, pasting a third bearing glue 13 on a bearing platform of the chip mounter, pasting the secondary plastic package on the third bearing glue 13, and drilling blind holes on the first plastic package layer 4 by adopting laser drilling equipment to expose the I/O interface and the conductive column 3 of the first chip 2; then carrying out vacuum sputtering on the surfaces of the blind holes and the first plastic packaging layer 4 to prepare a seed layer; sequentially pasting a dry film, exposing, developing and flashing to manufacture a rewiring layer;
and S80, attaching the dielectric layer 11, performing laser punching processing on the dielectric layer 11 to expose the conductive posts 3 and the I/O interface of the first chip 2, and implanting solder balls into the pad area of the redistribution layer to complete the preparation of the fan-out three-dimensional packaging structure.
The embodiment also provides a fan-out three-dimensional packaging structure manufactured by the manufacturing method of the embodiment, which includes:
the embedded material 1 is provided with a first through hole 1-1 and a second through hole 1-2 which penetrate through the embedded material 1 along the thickness direction of the embedded material 1 at intervals;
the chip packaging structure comprises a first plastic packaging layer 4, a first chip 2 positioned in a first through hole 1-1 and a conductive column 3 positioned in a second through hole 1-2, wherein the first chip 2 and the conductive column 3 are packaged in the first plastic packaging layer 4, and the front surface of the first chip 2 faces the first plastic packaging layer 4; specifically, the first plastic package layer 4 covers the first chip 2, the conductive pillars 3, and all surfaces of the embedded material 1 away from the back surface of the first chip 2;
the second plastic package layer 7 and the second chip 5 are positioned on one side of the embedded material 1, the back surface of the second chip 5 is bonded with the back surface of the first chip 2 through a double-sided adhesive tape, an I/O interface of the second chip 5 is connected with the conductive column 3 through a lead 6, and the second chip 5 is packaged in the second plastic package layer 7; specifically, the second molding compound layer 7 is positioned on one surface of the embedding material 1 close to the back surface of the first chip 2 and covers the second chip 5 and the leads 6;
and the metal bump 9 is connected with the I/O interface of the first chip 2 and the conductive column 3 through the electric connection structure 8.
In this embodiment, the I/O interface of the second chip 5 is connected to the conductive post 3 embedded in the second through hole 1-2 of the material 1 through the lead 6, so as to avoid separately electroplating the second chip 5 to fabricate the electrical connection structure 8, reduce the time for fabricating the circuit layer by electroplating, and reduce the production cost, and the I/O interface of the conductive post 3 and the first chip 2 embedded in the first through hole 1-1 of the material 1 is connected to the metal bump 9 through the electrical connection structure 8, thereby realizing the leading-out of the electrical signals of the first chip 2 and the second chip 5 stacked in back-to-back three-dimensional manner, and effectively reducing the packaging height of the fan-out three-dimensional packaging structure.
In this embodiment, the first chip 4 is a thinned chip, the back surface of the first chip is provided with a double-sided adhesive tape, and after the first carrier tape 10 is removed, the second chip 7 can be quickly attached to the back surface of the first chip 4 through the double-sided adhesive tape provided on the back surface of the first chip 4.
In this embodiment, the first plastic package layer 4 is provided with a blind hole through which the I/O interface of the first chip 2 and one end of the conductive post 3 are exposed, the electrical connection structure 8 includes a seed layer located in the blind hole and on the first plastic package layer 4 and a redistribution layer located on the seed layer, and the metal bump 9 is welded to the pad region of the redistribution layer. Specifically, the seed layer is located on the surface of the blind hole and the surface of the first plastic package layer 4, and the rewiring layer is located on the surface of the seed layer and fills the whole blind hole.
The seed layer and the rewiring layer are provided with graphical holes for exposing part of the first plastic packaging layer 4;
the fan-out three-dimensional package structure of the embodiment further includes a dielectric layer 11, and the dielectric layer 11 is attached to the non-pad area and the patterned hole of the redistribution layer. The dielectric layer 11 fills the patterned holes and serves to insulate and protect the non-pad areas of the redistribution layer.
Alternatively, the conductive pillar 3 is made of any one of Cu, Ag, or Au, but not limited thereto, and may be conductive.
Optionally, the double-sided adhesive tape is daf (die Attach film) or an epoxy glue. The double-sided adhesive tape is a scribing adhesive tape with the thinned back surface of the first chip 2, the thinned first chip 2 is adopted, the packaging height is reduced, the second chip 5 is convenient to mount on the back surface of the first chip 2, and the packaging efficiency of the fan-out type three-dimensional packaging structure is improved.
Optionally, the dielectric layer 11 is ABF or PI material, but is not limited thereto.
Alternatively, the buried material is FR4, FR5, or bt (bimoleimide) material, but not limited thereto, the opening process may be facilitated to embed the first chip 2 and the conductive pillars 3 in the holes.
It should be understood that the above-described embodiments are merely illustrative of the preferred embodiments of the present invention and the technical principles thereof. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, these modifications are within the scope of the present invention as long as they do not depart from the spirit of the present invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.
Claims (7)
1. A fan-out three-dimensional package structure, comprising:
the embedded material is provided with a first through hole and a second through hole which penetrate through the embedded material along the thickness direction of the embedded material at intervals;
the first chip and the conductive column are packaged in the first plastic package layer, and the front surface of the first chip faces the first plastic package layer;
the back surface of the second chip is bonded with the back surface of the first chip through a double-sided adhesive tape, an I/O interface of the second chip is connected with the conductive post through a lead, and the second chip is packaged in the second plastic package layer;
and the metal bump is connected with the I/O interface of the first chip and the conductive column through an electric connection structure.
2. The fan-out three-dimensional package structure of claim 1, wherein the first plastic package layer is provided with a blind hole through which an I/O interface of the first chip and one end of the conductive post are exposed, the electrical connection structure comprises a seed layer located in the blind hole and on the first plastic package layer, and a redistribution layer located on the seed layer, and the metal bump is welded to the pad region of the redistribution layer.
3. The fan-out three-dimensional package structure of claim 2, wherein the seed layer and the redistribution layer have patterned holes exposing portions of the first molding compound layer;
the dielectric layer is attached to the non-pad area of the redistribution layer and the patterned hole.
4. The fan-out three-dimensional package structure of claim 3, wherein the dielectric layer is an ABF or PI material.
5. The fan-out three-dimensional package structure of claim 1, wherein the conductive posts are any one of Cu, Ag, or Au.
6. The fan-out three-dimensional package structure of claim 1, wherein the double-sided adhesive tape is DAF or epoxy glue.
7. The fan-out three-dimensional package structure of claim 1, wherein the buried material is FR4, FR5, or BT material.
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| CN114649286A (en) * | 2022-05-19 | 2022-06-21 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
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| CN114649286A (en) * | 2022-05-19 | 2022-06-21 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
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