CN105845585A - Chip packaging method and chip packaging structure - Google Patents
Chip packaging method and chip packaging structure Download PDFInfo
- Publication number
- CN105845585A CN105845585A CN201610292628.2A CN201610292628A CN105845585A CN 105845585 A CN105845585 A CN 105845585A CN 201610292628 A CN201610292628 A CN 201610292628A CN 105845585 A CN105845585 A CN 105845585A
- Authority
- CN
- China
- Prior art keywords
- chip
- metal
- layer
- metal layer
- electric conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 63
- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 125
- 239000002184 metal Substances 0.000 claims abstract description 125
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 230000008878 coupling Effects 0.000 claims description 32
- 238000010168 coupling process Methods 0.000 claims description 32
- 238000005859 coupling reaction Methods 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000012856 packing Methods 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000005022 packaging material Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004899 motility Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging method and a chip packaging structure. A first metal layer is formed on a packaging carrier firstly; then metal convex blocks are formed on the first metal layer; a first welding layer is formed on the metal convex blocks; then chips are electrically connected on the first welding layer through electric conductors in a way that the active surfaces face the first welding layer, wherein the electric conductors are electrically connected on welding discs directly; and finally the first metal surface is enabled to be exposed by plastic packaging bodies through plastic packaging so as to provide external electrical connection. Therefore, the chip packaging method does not need to use a complex UBM technology or a preformed lead frame so that the yield rate of chip packaging and the flexible design can be enhanced, and the chip packaging structure according to the chip packaging method has high packaging integration and reliability.
Description
Technical field
The present invention relates to chip encapsulation technology field, particularly relate to a kind of chip packaging method and chip package knot
Structure.
Background technology
Manufacture integrated circuit time, chip generally with other electronic assemblies integrated before packed.Early
Phase applies wide chip package process to be wire bond package technique, i.e. by by the electrode tip on chip
Son is bonded on lead frame by metal lead wire, the then packaged type of plastic packaging.But pass through wire bonding
The area of the encapsulating structure that packaging technology is formed is relatively big, and encapsulation performance receives metal lead wire resistance and parasitism electricity
Hold impact and can not effectively improve.Therefore, flip-chip packaged technique is arisen at the historic moment subsequently, is sealed by upside-down mounting
The flip-chip packaged structure that dress technique is formed is little due to package dimension, and encapsulation performance is high and receives much concern.
Existing flip-chip packaged technique is: first make projection on chip, then by chip by described convex
Block back-off on the lead frame of preforming, last plastic packaging, make the exposed surface at plastic-sealed body of lead frame,
To provide external electrical connections.
In existing this flip-chip packaged technique, chip makes the complex process of projection, need first at core
Make UBM layer (Underbump metallization layer) on the electrode pad of sheet, utilize solder on UBM layer the most again
Backflow forms soldered ball, or plating forms copper billet on UBM layer.But make the complex process of UBM layer,
Repeatedly photoetching process used by needs, and cost is high, and the processing step owing to operating on the active face of chip is many,
Easily cause the damage of chip.Additionally, this flip-chip packaged technique also needs to lead frame set in advance,
It is unfavorable for the agile kernel model of encapsulation.
Summary of the invention
In view of this, the invention provides a kind of chip packaging method and chip-packaging structure, to improve chip
The yield of encapsulation, reliability, integrated level and reduction chip package cost.
A kind of chip packaging method, it is characterised in that including:
The first metal layer of patterning is formed on the surface of package carrier；
The first surface of described the first metal layer is formed multiple metal coupling；
The first weld layer is formed at described metal lug surface；
By the active face of chip towards described first weld layer, and electrically connected with described weld layer by electric conductor,
Described electric conductor is positioned on the pad of described active face.
Carry out plastic package process, make capsulation material fill the space between described chip and package carrier and covering
Described chip, to form plastic-sealed body；
Removing described package carrier, the second surface making described the first metal layer is exposed by described plastic-sealed body, uses
In providing external connection, described first surface is relative with second surface.
Preferably, described chip packaging method also includes: by described chip by electric conductor and described the
Before one weld layer electrical connection, on described pad, form described electric conductor by salient point routing technique.
Preferably, described electric conductor is copper ball.
Preferably, described package carrier includes mechanical support substrate and be positioned on described mechanical support substrate the
Two metal levels, described the first metal layer is formed on described second metal level.
Preferably, using described the first metal layer as Seed Layer, utilize electroplating technology at described the first metal layer
First surface on form described metal coupling.
Preferably, described the first metal layer is formed by multiple pin arrangements, multiple described metal couplings position respectively
On multiple described pins, and each described pin area of section in the horizontal direction is thereon more than being positioned at
Described metal coupling sectional area in the horizontal direction.
Preferably, the step forming described the first metal layer includes:
Using described second metal level as Seed Layer, electroplating technology is utilized to form institute on described second metal level
State the first metal layer.
Preferably, described chip packaging method also includes: removing after described package carrier, described the
The second surface of one metal level forms the second weld layer, the chip package formed according to described chip packaging method
Structure is welded to connect with external circuit by described second weld layer.
A kind of chip-packaging structure, it is characterised in that including:
Chip, has active face, described active face is provided with pad,
Electric conductor, is positioned on described pad,
The first metal layer of patterning, has relative first surface and second surface,
Metal coupling, is positioned on the first surface of described the first metal layer,
And it is positioned at the first weld layer of described metal lug surface,
Described active face is towards described first weld layer and electric with described first weld layer by described electric conductor
Connect,
Plastic-sealed body, is used for encapsulating described chip, electric conductor, the first weld layer, metal coupling and described
One metal level, and the first surface of described the first metal layer is exposed by described plastic-sealed body, is used for providing outside to connect
Connect.
Preferably, described electric conductor is copper ball.
Preferably, described metal coupling is copper billet.
Preferably, described the first metal layer is formed by multiple pin arrangements, multiple described metal couplings position respectively
On multiple described pins, and each described pin area of section in the horizontal direction is thereon more than being positioned at
Described metal coupling sectional area in the horizontal direction.
Preferably, described chip-packaging structure also includes being positioned on the second surface of described the first metal layer
Second weld layer, is welded to connect with external circuit by described second weld layer according to described chip-packaging structure.
Therefore, in the chip packaging method that the present invention provides, first on package carrier, form the first gold medal
Belong to layer, then on described the first metal layer formed metal coupling, and on metal coupling on formed first weldering
Connect layer, then by pad directly electrical connection electric conductor chip with active face towards described first weld layer
Mode, is connected electrically on the first weld layer by described electric conductor, eventually passes plastic packaging, makes described first gold medal
Metal surface is exposed by plastic-sealed body, to provide external electrical connections.Therefore, described chip packaging method is without using
Complicated UBM technique and the lead frame of preforming, the yield and the motility that improve chip package set
Meter, and according to the chip-packaging structure of present invention offer, there is higher encapsulation integrated level and reliability.
Accompanying drawing explanation
By description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the present invention,
Feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 a to Fig. 1 f is to form structure according to each processing step in the chip packaging method of the embodiment of the present invention
Generalized section.
Detailed description of the invention
It is more fully described the present invention hereinafter with reference to accompanying drawing.In various figures, identical ingredient
Similar reference is used to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn to paint
System.Furthermore, it is possible to not shown part known to some.For brevity, can be described in the width figure
The structure obtained after several steps.Describe hereinafter the many specific details of the present invention, such as
The structure of each ingredient, material, size, process technique and technology, in order to be more clearly understood that this
Bright.Additionally, in this application, chip refers both to semiconductor bare chip.But as those skilled in the art's energy
As enough understanding, the present invention can not be realized according to these specific details.
Fig. 1 a to Fig. 1 e is to form structure according to each processing step in the chip packaging method of the embodiment of the present invention
Generalized section.Below in conjunction with Fig. 1 a to Fig. 1 e be specifically described the present invention provide chip packaging method and
Chip-packaging structure.
The chip packaging method that the present invention provides mainly comprises the steps:
Step 1: form the first metal layer of patterning on package carrier.
As shown in Figure 1a, package carrier 1 primarily serves the effect of mechanical support during chip package,
In the present embodiment, package carrier 1 includes mechanical support substrate 11 (such as insulated substrate etc.) and is positioned at absolutely
The second metal level 12 on edge substrate.
In the present embodiment, the concrete steps forming described the first metal layer 2 can be: with the second metal level
12 as Seed Layer, utilizes electroplating technology to form the first metal layer 2 on the second metal level 12.In plating
During, select suitable electroplating mask plate so that the multiple patterned arrangement of electroplating metal material electrodeposited coating
Pin, multiple described pin arrangements constitute described the first metal layer.The first metal layer 2 and the second metal level
12 can be all layers of copper.The first metal layer 2 has relative first surface and second surface, its two surface with
Package carrier 1 contacts.
Step 2: form multiple metal coupling on the first surface of described the first metal layer.
In the present embodiment, as shown in Figure 1 b, using the first metal layer 2 as Seed Layer, electroplating technology is utilized
The first metal layer 2 is formed multiple metal coupling 3.Electroplating technology is utilized to form gold on the first metal layer 1
Belong to concretely comprising the following steps of projection 3: first electroplating mask plate is set on the first metal layer 2, this electroplating mask plate
Expose part the first metal layer 2, then electroplating metal material on exposed the first metal layer 2, with
Forming metal coupling 3 one by one on one metal level 2, concrete, each described metal coupling 3 is positioned at composition
On a pin in multiple pins of described the first metal layer 2.Metal coupling 3 can be copper billet.Metal
Projection 3 can be the projection of the shape such as cuboid or cylinder.
Step 3: form weld layer at metal lug surface.
As shown in Figure 1 b, forming the first weld layer 4 on metal coupling 3, the first weld layer 4 can be stannum
Layer, is welded to connect for the electric conductor on follow-up chip.
Step 4: by the active face of chip towards the first weld layer 4, and by electric conductor and the first weld layer 4
Electrical connection, described electric conductor is positioned on the pad of described active face.
As illustrated in figure 1 c, before chip 5 is electrically connected with the first weld layer 4, in addition it is also necessary at chip 5
Forming electric conductor 6 in the pad (not shown) of active face, electric conductor 6 is formed directly on pad, i.e. conducts electricity
Body 6 directly contacts with the pad of chip 5, does not has therebetween metal level.For example, it is possible to beaten by salient point
Wiring technology forms electric conductor 6.The concrete steps utilizing salient point routing technique to form electric conductor 6 include: first with
Capillary (salient point routing technique apparatus) forms soldered ball, is then implanted in by described soldered ball on the pad of chip 5,
Then the metal wire on pinch off soldered ball, thus on the pad of chip 5, define electric conductor 6.In this enforcement
In example, electric conductor 6 is copper ball.
Step 5: carry out plastic package process, make space that capsulation material fills between described chip and package carrier with
And cover described chip, to form plastic-sealed body.
As shown in Figure 1 d, described plastic packaging material can be chosen as epoxy-plastic packaging material, the encapsulation that will be formed in step 4
Assembly is placed in plastic package die, then injects epoxy-plastic packaging material, so that epoxy is moulded in plastic package die
Envelope material is filled in the space between chip 5 and package carrier 1, the most also covers on chip 5, thus shape
Become the plastic-sealed body 7 of encapsulating chip 5, to protect chip so that it is be not easily susceptible to the impact of extraneous factor and damage.
Step 6: remove described package carrier, the second surface making described the first metal layer is naked by described plastic-sealed body
Dew, is used for providing external connection.
As shown in fig. le, after forming plastic-sealed body 7, need to remove the encapsulation as mechanical support effect and carry
Body 1, so that the exposed surface at plastic-sealed body 7 of the second surface of the first metal layer 2, using as chip 5
Outer pin, is used for providing external connection.When by the chip-packaging structure shown in Fig. 1 e and external circuit or printing
During circuit board electrical connection, the second surface of the first metal layer 2 contacts also with external circuit or printed circuit board (PCB)
Electrical connection.
As shown in fig. le, in the chip-packaging structure that the present invention provides, chip 5 has active face, chip
Being provided with pad (not shown) on the active face of 5, described pad refers to contact with the silicon materials forming chip 5
Metal level, usually aluminum pad.Electric conductor 6 is arranged on pad, directly to contact with pad and to be electrically connected
Connect.Concrete electric conductor 6 can be copper ball, and described copper ball is formed by salient point routing technique.In addition Fig. 1 e institute
The chip-packaging structure shown also includes having relative first surface and the first metal layer 2 of second surface, metal
Projection 3, the first weld layer 4 being positioned on metal coupling and plastic-sealed body 7.The active face of chip 5 is towards
One weld layer 4, and electrically connected with the first weld layer 4 by electric conductor 6.Plastic-sealed body 7 be used for encapsulating chip 5,
Electric conductor the 6, first weld layer 4, metal coupling 3 and the first metal layer 2, and the of the first metal layer 2
Two surfaces are exposed by plastic-sealed body 7, using the outer pin as the chip-packaging structure shown in Fig. 1 e, are used for providing
External connection.
Additionally, in the chip packaging method of foundation embodiment of the present invention offer, after completing step 6, also
It is included on the second surface of the first metal layer 2 and forms the second metal level 8, as shown in Figure 1 f, the then present invention
The chip-packaging structure provided also includes the second weld layer 8 being positioned on the second surface of the first metal layer 2.Figure
Chip-packaging structure shown in 1f is welded to connect with external circuit by the second weld layer 8.
In order to be suitable for the chip package of highly dense pitch pad, in the chip packaging method that the present invention provides, use
Size in the metal coupling 3 electrically connected with chip 5 typically require be made smaller, as directly the most convex at metal
The lower surface of block 3 directly forms the second weld layer 8 welded with external circuit, then due to chip-packaging structure with
It is difficult between external circuit be soldered (because welding region is the least).Therefore, the chip envelope provided in the present invention
In dress method, the sectional area of the horizontal direction constituting each pin of the first metal layer 2 is both needed to be designed to greatly
Sectional area in the horizontal direction being positioned at metal coupling 3 thereon.Wherein, described horizontal direction is and first
The direction that metal level 2 is vertical with metal coupling 3 stacking direction.
Therefore, in the chip packaging method that the present invention provides, first on package carrier, form the first gold medal
Belong to layer, then on described the first metal layer formed metal coupling, and on metal coupling on formed first weldering
Connect layer, then by pad directly electrical connection electric conductor chip with active face towards described first weld layer
Mode, is connected electrically on the first weld layer by described electric conductor, eventually passes plastic packaging, makes described first gold medal
Metal surface is exposed by plastic-sealed body, to provide external electrical connections.Therefore, described chip packaging method is without using
Complicated UBM technique and the lead frame of preforming, the yield and the motility that improve chip package set
Meter, and according to the chip-packaging structure of present invention offer, there is higher encapsulation integrated level and reliability.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe,
Also the specific embodiment that this invention is only described it is not intended to.Obviously, as described above, a lot of repairing can be made
Change and change.These embodiments are chosen and specifically described to this specification, in order to preferably explain the present invention
Principle and actual application, so that skilled artisan can utilize the present invention and well at this
Amendment on the basis of invention uses.The present invention is only limited by claims and four corner thereof and equivalent.
Claims (13)
1. a chip packaging method, it is characterised in that including:
The first metal layer of patterning is formed on the surface of package carrier；
The first surface of described the first metal layer is formed multiple metal coupling；
The first weld layer is formed at described metal lug surface；
By the active face of chip towards described first weld layer, and electrically connected with described weld layer by electric conductor,
Described electric conductor is positioned on the pad of described active face.
Carry out plastic package process, make capsulation material fill the space between described chip and package carrier and covering
Described chip, to form plastic-sealed body；
Removing described package carrier, the second surface making described the first metal layer is exposed by described plastic-sealed body, uses
In providing external connection, described first surface is relative with second surface.
Chip packaging method the most according to claim 1, it is characterised in that also include: by described
Before chip is electrically connected with described first weld layer by electric conductor, by salient point routing technique at described pad
The described electric conductor of upper formation.
Chip packaging method the most according to claim 2, it is characterised in that described electric conductor is copper
Ball.
Chip packaging method the most according to claim 1, it is characterised in that described package carrier bag
Include mechanical support substrate and the second metal level being positioned on described mechanical support substrate, described the first metal layer shape
On second metal level described in Cheng Yu.
Chip packaging method the most according to claim 4, it is characterised in that with described first metal
Layer, as Seed Layer, utilizes electroplating technology to form described metal on the first surface of described the first metal layer convex
Block.
Chip packaging method the most according to claim 1, it is characterised in that described the first metal layer
Being formed by multiple pin arrangements, multiple described metal couplings lay respectively on multiple described pin, and each
Described pin area of section in the horizontal direction more than be positioned at described metal coupling thereon in the horizontal direction cut
Face area.
Chip packaging method the most according to claim 4, it is characterised in that form described first metal
The step of layer includes:
Using described second metal level as Seed Layer, electroplating technology is utilized to form institute on described second metal level
State the first metal layer.
Chip packaging method the most according to claim 1, it is characterised in that also include: removing institute
After stating package carrier, the second surface at described the first metal layer forms the second weld layer, according to described chip
The chip-packaging structure that method for packing is formed is welded to connect with external circuit by described second weld layer.
9. a chip-packaging structure, it is characterised in that including:
Chip, has active face, described active face is provided with pad,
Electric conductor, is positioned on described pad,
The first metal layer of patterning, has relative first surface and second surface,
Metal coupling, is positioned on the first surface of described the first metal layer,
And it is positioned at the first weld layer of described metal lug surface,
Described active face is towards described first weld layer and electric with described first weld layer by described electric conductor
Connect,
Plastic-sealed body, is used for encapsulating described chip, electric conductor, the first weld layer, metal coupling and described
One metal level, and the first surface of described the first metal layer is exposed by described plastic-sealed body, is used for providing outside to connect
Connect.
Chip-packaging structure the most according to claim 9, it is characterised in that described electric conductor is copper
Ball.
11. chip-packaging structures according to claim 10, it is characterised in that described metal coupling is
Copper billet.
12. chip-packaging structures according to claim 9, it is characterised in that described the first metal layer
Being formed by multiple pin arrangements, multiple described metal couplings lay respectively on multiple described pin, and each
Described pin area of section in the horizontal direction more than be positioned at described metal coupling thereon in the horizontal direction cut
Area.
13. chip-packaging structures according to claim 9, it is characterised in that also include being positioned at described
The second weld layer on the second surface of the first metal layer, according to described chip-packaging structure by described second
Weld layer is welded to connect with external circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292628.2A CN105845585A (en) | 2016-04-28 | 2016-04-28 | Chip packaging method and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610292628.2A CN105845585A (en) | 2016-04-28 | 2016-04-28 | Chip packaging method and chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105845585A true CN105845585A (en) | 2016-08-10 |
Family
ID=56591276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610292628.2A Pending CN105845585A (en) | 2016-04-28 | 2016-04-28 | Chip packaging method and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105845585A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807325A (en) * | 2017-05-04 | 2018-11-13 | 无锡天芯互联科技有限公司 | A kind of novel chip-packaging structure and preparation method thereof |
| CN110323141A (en) * | 2019-04-15 | 2019-10-11 | 矽力杰半导体技术(杭州)有限公司 | Lead frame structure, chip-packaging structure and its manufacturing method |
| CN110828318A (en) * | 2019-11-20 | 2020-02-21 | 江苏上达电子有限公司 | High-precision sealing process for bare chip without convex points |
| CN111354702A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Embedded chip and preparation method thereof |
| CN118471940A (en) * | 2024-07-10 | 2024-08-09 | 青岛泰睿思微电子有限公司 | Panel-level chip packaging structure and method based on steel plate platform |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311492A (en) * | 2006-05-17 | 2007-11-29 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| US20080105973A1 (en) * | 2006-11-06 | 2008-05-08 | Broadcom Corporation | Semiconductor assembly with one metal layer after base metal removal |
| CN101989593A (en) * | 2009-07-30 | 2011-03-23 | 全懋精密科技股份有限公司 | Packaging substrate as well as manufacturing method and packaging structure thereof |
| CN103367180A (en) * | 2012-03-27 | 2013-10-23 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN103943600A (en) * | 2013-06-07 | 2014-07-23 | 珠海越亚封装基板技术股份有限公司 | Novel Butt Joint And Connection Between Chip And Substrate |
| CN104124180A (en) * | 2013-04-25 | 2014-10-29 | 南茂科技股份有限公司 | Manufacturing method of chip packaging structure |
| CN105097571A (en) * | 2015-06-11 | 2015-11-25 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging method and packaging assembly |
-
2016
- 2016-04-28 CN CN201610292628.2A patent/CN105845585A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007311492A (en) * | 2006-05-17 | 2007-11-29 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| US20080105973A1 (en) * | 2006-11-06 | 2008-05-08 | Broadcom Corporation | Semiconductor assembly with one metal layer after base metal removal |
| CN101989593A (en) * | 2009-07-30 | 2011-03-23 | 全懋精密科技股份有限公司 | Packaging substrate as well as manufacturing method and packaging structure thereof |
| CN103367180A (en) * | 2012-03-27 | 2013-10-23 | 南茂科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN104124180A (en) * | 2013-04-25 | 2014-10-29 | 南茂科技股份有限公司 | Manufacturing method of chip packaging structure |
| CN103943600A (en) * | 2013-06-07 | 2014-07-23 | 珠海越亚封装基板技术股份有限公司 | Novel Butt Joint And Connection Between Chip And Substrate |
| CN105097571A (en) * | 2015-06-11 | 2015-11-25 | 矽力杰半导体技术(杭州)有限公司 | Chip packaging method and packaging assembly |
Non-Patent Citations (1)
| Title |
|---|
| 中国电子学会生产技术学分会丛书编委会: "《微电子封装技术》", 30 April 2003, 中国科学技术大学出版社 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807325A (en) * | 2017-05-04 | 2018-11-13 | 无锡天芯互联科技有限公司 | A kind of novel chip-packaging structure and preparation method thereof |
| CN111354702A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Embedded chip and preparation method thereof |
| CN110323141A (en) * | 2019-04-15 | 2019-10-11 | 矽力杰半导体技术(杭州)有限公司 | Lead frame structure, chip-packaging structure and its manufacturing method |
| CN110828318A (en) * | 2019-11-20 | 2020-02-21 | 江苏上达电子有限公司 | High-precision sealing process for bare chip without convex points |
| CN118471940A (en) * | 2024-07-10 | 2024-08-09 | 青岛泰睿思微电子有限公司 | Panel-level chip packaging structure and method based on steel plate platform |
| CN118471940B (en) * | 2024-07-10 | 2024-11-05 | 青岛泰睿思微电子有限公司 | Panel-level chip packaging structure and method based on steel plate platform |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103715166B (en) | Device and method for component package | |
| CN103515362B (en) | Stacked package device and the method for encapsulation semiconductor element | |
| CN104064551B (en) | A kind of chip stack package structure and electronic equipment | |
| CN101252096B (en) | Chip package structure and preparation method thereof | |
| US7245008B2 (en) | Ball grid array package, stacked semiconductor package and method for manufacturing the same | |
| CN102456677B (en) | Packaging structure for ball grid array and manufacturing method for same | |
| CN104882417B (en) | Integrating passive Flip-Chip Using | |
| CN103745931B (en) | Lead frame and packaging structure forming methods | |
| US9064718B1 (en) | Pre-formed via array for integrated circuit package | |
| CN103794587B (en) | Embedded type rewiring line packaging structure of chip with good heat dissipation performance and manufacturing method thereof | |
| CN105845585A (en) | Chip packaging method and chip packaging structure | |
| CN105621345A (en) | MEMS (Micro Electro Mechanical Systems) chip integrated packaging structure and packaging method | |
| CN103887256B (en) | High-cooling-performance chip-embedded type electromagnetic shielding encapsulating structure and manufacturing method thereof | |
| CN108010889A (en) | Chip-packaging structure and method for packing | |
| US9461009B1 (en) | Method and apparatus for assembling a semiconductor package | |
| CN110211946A (en) | A kind of chip-packaging structure and its manufacturing method | |
| US9153530B2 (en) | Thermal enhanced high density flip chip package | |
| CN107946282A (en) | Three-dimensional fan-out package structure and its manufacture method | |
| CN113410215A (en) | Semiconductor packaging structure and preparation method thereof | |
| CN105977233A (en) | Chip packaging structure and manufacturing method thereof | |
| CN110211954A (en) | A kind of multichip packaging structure and its manufacturing method | |
| CN103915397B (en) | More bare crystallines, high current wafer-level packaging | |
| CN105428507A (en) | Chip packaging structure and method | |
| CN203787410U (en) | High radiating chip embedded electromagnetic shielding packaging structure | |
| CN213401181U (en) | Chip structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160810 |
|
| RJ01 | Rejection of invention patent application after publication |