CN217719655U

CN217719655U - Perovskite/crystalline silicon tandem cell structure

Info

Publication number: CN217719655U
Application number: CN202221325113.5U
Authority: CN
Inventors: 杨少飞
Original assignee: Suzhou Maxwell Technologies Co Ltd
Current assignee: Suzhou Maxwell Technologies Co Ltd
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2022-11-01
Anticipated expiration: 2032-05-30

Abstract

The invention discloses a perovskite/crystalline silicon laminated cell structure, which is provided with a perovskite top cell, p-type and n-type metal oxide tunneling junctions and a crystalline silicon bottom cell from the front side to the back side; compared with a silicon thin film tunneling junction or an ITO composite layer which replaces the traditional scheme, the p-type and n-type metal oxide tunneling junctions have wide band gaps and high transparency, so that less light is absorbed in the laminated cell, more light can enter a cell power generation layer, and higher photocurrent is obtained.

Description

Perovskite/crystalline silicon tandem cell structure

Technical Field

The utility model relates to a solar cell technical field, more specifically say, relate to a perovskite/crystalline silicon tandem cell structure.

Background

The perovskite solar cell has the outstanding advantages of high photoelectric conversion efficiency, low cost, simple manufacture and the like. And thus become the most promising solar cell and the focus of research. The cell efficiency of the perovskite solar cell reaches 25.8 percent at present. The perovskite absorption layer with wide band gap is very favorable for forming a double-junction cell with a crystalline Silicon (SHJ) solar cell, and the photoelectric conversion efficiency of the current double-junction solar cell formed by perovskite and crystalline silicon reaches 29.5%, and meanwhile, the stability of the double-junction solar cell is superior to that of a perovskite single-junction cell. At present, the efficiency of the perovskite/crystalline silicon tandem cell still has a larger difference with the theoretical efficiency of 42%, the cell structure is further optimized, and the design of devices is optimized, which is one of the working key points for improving the efficiency of the solar cell in the future.

The stack requires the efficient series connection of the perovskite and SHJ cells using suitable interlayers. The intermediate layer of the perovskite/SHJ laminated cell currently researched generally adopts two modes, namely a silicon thin film tunneling junction or a Transparent Conductive Oxide (TCO) thin film. By adopting a silicon thin film tunneling junction, a hole transport layer (or an electron transport layer) of the perovskite solar cell needs to be deposited on the silicon thin film tunneling junction, and the problems that the silicon thin film tunneling junction is not ideal in composite effect, insufficient in transparency, large in optical absorption and capable of influencing the performance of the laminated cell easily exist;

the use of Transparent Conductive Oxide (TCO) films presents a current leakage problem. The transparent conductive oxide film has high transverse conductivity, so that the perovskite layer leaks electricity, and the voltage and the filling factor of the laminated cell are influenced.

Disclosure of Invention

1. Problems to be solved

Based on the above, the invention provides a perovskite/crystalline silicon laminated cell structure.

2. Technical scheme

In order to solve the problems, the technical scheme adopted by the invention is as follows:

a perovskite/crystalline silicon stacked cell structure, which is provided with from the front side to the back side:

a perovskite roof battery;

a tunneling junction; and the number of the first and second groups,

a crystalline silicon bottom cell;

in the direction from the front surface to the back surface,

the perovskite top battery comprises a conductive layer a, an electron transport layer a, an absorption layer a and a hole transport layer a;

the tunneling junction comprises a p-type semiconductor layer and an n-type semiconductor layer;

the crystalline silicon bottom cell comprises an electron transport layer b, a passivation layer b, an absorption layer b, a passivation layer c, a hole transport layer b and a conducting layer b;

the tunneling junction comprises a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer.

Further, the perovskite top battery also comprises a conductive grid line a stacked on the conductive layer a;

the crystalline silicon bottom cell also comprises a conductive grid line b stacked on the conductive layer b;

the conductive grid lines a and b are silver grids generally and can be manufactured by adopting screen printing.

Further, the conductive layer a has a thickness of 0.01 to 50 μm; preferably having a thickness of 0.08 to 50 μm; further preferably has a thickness of 80 to 1000nm, still further preferably has a thickness of 80 to 110 nm; most preferably 80nm;

the electron transmission layer a has a thickness of 0.1nm to 1000 nm; preferably having a thickness of 1 to 100nm, more preferably having a thickness of 20nm;

the absorption layer a has a thickness of 50nm to 3000 nm; preferably 700 nm;

the hole transport layer a has a thickness of 0.1nm to 1000 nm; preferably having a thickness of 1 to 100nm; further preferably has a thickness of 1 to 50 nm; more preferably 20nm thick.

Further, the electron transport layer b has a thickness of 1nm to 200 nm; preferably having a thickness of 1nm to 100nm; more preferably 10nm;

the passivation layer b has a thickness of 1nm to 100nm; preferably, the passivation layer b has a thickness of 1 to 20nm, and more preferably, the passivation layer b has a thickness of 10nm;

the absorption layer b has a thickness of 50 to 500 μm; preferably having a thickness of 150 μm;

the passivation layer c has a thickness of 1nm to 100nm; preferably, the passivation layer c has a thickness of 1 to 20nm, and more preferably, the passivation layer c has a thickness of 10nm;

the hole transport layer b has a thickness of 0.001 to 250 μm, preferably 1nm to 100nm; more preferably 10nm;

the conductive layer b has a thickness of 0.08 to 250 μm; preferably, the conductive layer b has a thickness of 0.08 to 50 μm; more preferably 80nm thick.

The tunnel junction has a junction 10⁴Ω·cm～10^-3Ω · cm resistivity; preferably, the tunnel junction has a value of 10²Ω·cm～10^-1Resistivity of Ω · cm.

Further, the tunneling junction further comprises carriers; the carriers include holes and electrons; the p-type semiconductor layer includes holes and the n-type semiconductor layer includes electrons.

Further, the tunneling junction comprises a p-type metal oxide semiconductor layer and an n-type metal oxide semiconductor layer;

the p-type semiconductor layer has a thickness of 1 to 200 nm;

the n-type semiconductor layer has a thickness of 1 to 200nm.

It should be noted here that the resistivity of the conventional stacked cell using only the Transparent Conductive Oxide (TCO) film is basically two orders of magnitude higher than that of the tunnel junction in the present scheme.

Further, the thickness of the p-type semiconductor layer is 1 nm-200 nm, and the carrier concentration is 1 x 10¹⁴cm^-3～1×10²²cm^-3Mobility of 1X 10^-8cm²/V·s～1×10^-2cm²V.s; the preferred thickness is 1nm to 100nm; more preferably 10nm in thickness and 5X 10 in carrier concentration¹⁶cm^-3Mobility of 3X 10^-4cm²/V·s。

The n-type semiconductor layer has a thickness of 1nm to 200nm and a carrier concentration of 1 × 10¹⁵cm^-3～1×10²⁰cm^-3Mobility of 1X 10^-8cm²/V·s～1×10^-2cm²V.s. The preferred thickness is 1nm to 100nm; more preferably 10nm in thickness and 4X 10 in carrier concentration¹⁷cm^-3Mobility of 2X 10^-3cm²/V·s。

the p-type metal oxide layer is used as a p-type metal oxide semiconductor layer and mainly takes holes as carriers to conduct charges; the p-type metal oxide layer is a layer of a compound formed by bonding only a metal element and an oxygen element; and/or a layer of a compound formed by combining a metal element, an oxygen element, and a doping element; wherein the metal element in the p-type metal oxide layer comprises at least one of nickel, vanadium and copper; the mixed element comprises one or two of boron and gallium; illustrative conventional p-type metal oxide semiconductors such as vanadium oxide and its dopant, nickel oxide and its dopant, molybdenum oxide and its dopant;

the n-type metal oxide layer is used as an n-type metal oxide semiconductor layer and mainly takes electrons as carriers to conduct charges; a layer which is a compound formed by bonding only a metal element and an oxygen element; and/or a layer of a compound formed by combining a metal element, an oxygen element, and a doping element; wherein the metal element in the n-type metal oxide layer comprises at least one of tin, indium and zinc; the hetero element comprises one or two of phosphorus and arsenic; illustrative examples of the conventional n-type metal oxide semiconductor include tin oxide and a dopant thereof, zinc oxide and a dopant thereof, and titanium oxide and a dopant thereof;

the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer can be realized through a coating process.

Further, the conductive layer a is an indium tin oxide film;

the electron transport layer a is a tin oxide layer or a titanium oxide layer or a zinc oxide layer;

the absorption layer a is a perovskite thin film;

the hole transferThe input layer a is a nickel oxide layer (NiO)_xLayers).

Further, the tunnel junction further comprises carriers;

wherein the carriers comprise holes and electrons; the p-type semiconductor layer includes holes and the n-type semiconductor layer includes electrons.

Furthermore, the electron transmission layer b is an N-type amorphous silicon film;

the passivation layer b is an I-type amorphous silicon film;

the absorption layer b is a crystal silicon wafer;

the passivation layer c is an I-type amorphous silicon film;

the hole transport layer b is a P-type amorphous silicon film;

the conductive layer b is an indium tin oxide film.

It should be noted here that the indium tin oxide thin film described above can be manufactured by magnetron sputtering deposition;

the electron transport layers as described above are typically fabricated by Atomic Layer Deposition (ALD);

the perovskite thin film material of the absorption layer a is FA_1-xCs_xPbI₃Typically 0.1 therein<x is less than or equal to 1. Of course, the perovskite thin film material of the present invention is not limited thereto, and may be other existing perovskite materials.

The absorption layer b is a crystalline silicon wafer, and an N-type crystalline silicon wafer or a P-type crystalline silicon wafer can be selected according to the situation;

the nickel oxide layer is NiO_xLayer, x is 1-1.5;

the I-type amorphous silicon thin film or the P-type amorphous silicon thin film as described above may be fabricated by, for example, plasma Enhanced Chemical Vapor Deposition (PECVD).

3. Advantageous effects

Compared with the prior art, the invention has the beneficial effects that:

the utility model provides a perovskite/crystalline silicon tandem cell structure, including perovskite top battery, P type, N type metallic oxide tunnel junction and crystalline silicon bottom battery that stack gradually;

compared with a silicon thin film tunneling junction or an ITO composite layer which replaces the traditional scheme, the P-type and N-type metal oxide tunneling junctions have wide band gaps and high transparency, so that less light is absorbed in the laminated cell, more light can enter a cell power generation layer, and higher photocurrent is obtained;

the tunneling junction composed of the n-type metal oxide and the p-type metal oxide is adopted, and the conduction band energy level of the n-type metal oxide is close to the valence band energy level of the p-type metal oxide, so that good composite efficiency can be realized, the series resistance of the laminated battery is reduced, and the FF of the battery is improved.

Drawings

Fig. 1 is a schematic structural diagram of a stacked cell according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a stacked cell according to an embodiment of the present invention;

in the figure:

100. a perovskite roof battery; 110. a conductive grid line a; 120. a conductive layer a; 130. an electron transport layer a; 140. an absorption layer a; 150. a hole transport layer a;

200. a tunneling junction; 210. a p-type semiconductor layer; 220. an n-type semiconductor layer;

300. a crystalline silicon bottom cell; 310. an electron transport layer b; 320. a passivation layer b; 330. an absorption layer b; 340. a passivation layer c; 350. a hole transport layer b; 360. a conductive layer b; 370. and a conductive gate line b.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be embodied in many other forms different from those described herein and similar modifications may be made by those skilled in the art without departing from the spirit and scope of the invention and, therefore, the invention is not to be limited to the specific embodiments disclosed below.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It is to be understood that in the description of the present invention, the terms "central," "longitudinal," "lateral," "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings only for the convenience of description and simplicity of description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting.

Furthermore, "a", "b", "c", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "a," "b," "c," etc. may explicitly or implicitly include one or more of that feature.

It should be noted that, unless otherwise explicitly stated or limited, the terms "stacked on" and "stacked" in the description of the present invention are to be understood in a broad sense, and for example, the combination of "layer" and "layer" may be performed by Plasma Enhanced Chemical Vapor Deposition (PECVD), or the combination of "layer" and "layer" may be performed by magnetron sputtering deposition. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

Referring to fig. 1, the perovskite/crystalline silicon tandem cell provided by the present invention includes a perovskite top cell 100, a tunneling junction 200, and a crystalline silicon bottom cell 300 stacked in sequence from front to back;

referring to fig. 2, the perovskite top cell 100 includes a conductive gate line a 110, a conductive layer a120, an electron transport layer a 130, an absorption layer a 140, and a hole transport layer a 150, which are sequentially stacked in a front-to-back direction; the tunneling junction 200 comprises a p-type semiconductor layer 210 and an n-type semiconductor layer 220; the crystalline silicon bottom cell 300 comprises an electron transport layer b 310, a passivation layer b 320, an absorption layer b 330, a passivation layer c 340, a hole transport layer b 350, a conductive layer b 360 and a conductive grid line b 370 which are sequentially stacked.

For the conductive layer, an indium tin oxide film may be selected. It should be further noted that the thickness of the conductive layer a120 needs to be controlled within a range of 0.01 μm to 50 μm, and is preferably controlled within a range of 80nm to 110nm, so that good conductivity can be ensured and good antireflection effect can be ensured. Similarly, the thickness of the conductive layer b 360 needs to be controlled within the range of 0.08 μm to 250 μm, preferably 80 to 110nm, so as to ensure good conductivity and good antireflection effect

A tin oxide layer or a titanium oxide layer or a zinc oxide layer may be selected for the electron transport layer a 130; it should be further noted that the thickness of the electron transport layer a 130 is controlled to be in the range of 0.1nm to 1000nm, and it is of course preferable that the thickness is controlled to be in the range of 1 to 30nm. Thus, not only can the bombardment to perovskite when the conductive layer a120 is subjected to magnetron sputtering be reduced, but also high electron extraction efficiency can be ensured.

The perovskite thin film material selected for the absorption layer a 140 is FA1-xCSxPbI3, wherein 0.1 is formed by the layers of cloth with x less than or equal to 1. Of course, the perovskite thin film material of the present invention is not limited thereto, and may be other existing perovskite materials. It should be further noted that the thickness of the absorption layer a 140 needs to be controlled within a range of 50 to 3000nm, and preferably, the thickness needs to be controlled around 700 nm. Therefore, short-wave sunlight can be fully absorbed, and a photon-generated carrier can be ensured to be absorbed by the charge transport layer;

a nickel oxide layer (NiO) may be selected for the hole transport layer a 150_xA layer); it should be further noted that the thickness of the hole transport layer a 150 is controlled to be 0.1nm to 1000nm, but it is of course preferable that the thickness is controlled to be 1In the range of about 50 nm. Therefore, the film forming quality can be ensured, the internal series resistance can be ensured to be lower, and the improvement of the battery performance is facilitated.

Selecting an N-type amorphous silicon thin film for the electron transport layer b 310; it should be further noted that the thickness of the electron transport layer b 310 is required to be controlled within a range of 1 to 200nm, and it is of course preferable that the thickness is required to be controlled within a range of 1 to 100nm. Thus, not only can enough electron extraction efficiency be ensured, but also excessive parasitic absorption can be avoided;

the passivation layer b 320 or the passivation layer c 340 may be an I-type amorphous silicon thin film, and the thickness thereof needs to be controlled within a range of 1 to 100nm, and a more preferable thickness thereof needs to be controlled within a range of 1 to 20nm. Therefore, not only can the sufficient passivation effect be ensured, but also the overlarge series resistance of the battery can be avoided.

For the absorption layer b 330, a P-type or N-type crystalline silicon wafer can be selected, and it should be noted that the thickness thereof needs to be controlled within a range of 50-500 μm; of course, the preferred thickness is controlled to be within the range of 150 μm. Thus, not only can enough sunlight be absorbed by the cell, but also high utilization rate of raw materials can be ensured.

For the hole transport layer b 350, a P-type amorphous silicon film can be selected, and it should be noted that the thickness of the hole transport layer b 350 needs to be controlled within the range of 0.001 to 250 μm; of course, the preferred thickness is controlled to be in the range of 1 to 100nm. Therefore, not only can the sufficient hole extraction efficiency be ensured, but also excessive parasitic absorption can be avoided;

the perovskite top battery also comprises a conductive grid line a which is overlapped on the conductive layer a; or the crystalline silicon bottom cell further comprises a conductive grid line b 110 stacked on the conductive layer b 120. Typically a silver grid, is made by screen printing.

The tunneling junction comprises a p-type semiconductor layer 210 and an n-type semiconductor layer 220, and the tunneling junction has a thickness of 10⁴Ω·cm～10^-3Resistivity of Ω · cm; preferably, the tunnel junction has a value of 10²Ω·cm～10^-1Resistivity in the range of Ω · cm.

The P-type semiconductor layer 210 is a P-type metal oxide semiconductor, which mainly uses holes as carriers to conduct charges, and may be a conventional P-type metal oxide semiconductor such as vanadium oxide and its dopant, nickel oxide and its dopant, molybdenum oxide and its dopant, etc.; the n-type semiconductor layer 220 is formed by the n-type metal oxide semiconductor, mainly using electrons as carriers to conduct charges, and may be a conventional n-type metal oxide semiconductor such as tin oxide and its dopant, zinc oxide and its dopant, titanium oxide and its dopant, and the like. Compared with a silicon thin film tunneling junction or an ITO composite layer which replaces the traditional scheme, the tunneling junction formed by the n-type metal oxide and the p-type metal oxide has wide band gap and high transparency, so that less light is absorbed in the laminated cell, more light can enter a cell power generation layer, and higher photocurrent is obtained; and the conduction band energy level of the n-type metal oxide is close to the valence band energy level of the p-type metal oxide, so that good recombination efficiency can be realized, the series resistance of the laminated cell is reduced, and the FF of the cell is improved.

Example 1

As shown in fig. 1 and fig. 2, the perovskite/crystalline silicon stacked cell structure provided by the present invention has a perovskite top cell 100, a tunneling junction 200, and a crystalline silicon bottom cell 300 stacked in sequence from the front to the back; the tunneling junction 200 has a.6.5 × 10^-1Resistivity of Ω · cm.

Also in the front-to-back direction, the perovskite top battery 100 includes a conductive grid line a 110, a conductive layer a120, an electron transport layer a 130, an absorption layer a 140, and a hole transport layer a 150, which are sequentially stacked; the tunneling junction 200 comprises a p-type semiconductor layer 210 and an n-type semiconductor layer 220; the crystalline silicon bottom cell 300 comprises an electron transport layer b 310, a passivation layer b 320, an absorption layer b 330, a passivation layer c 340, a hole transport layer b 350, a conductive layer b 360 and a conductive grid line b 370 which are sequentially stacked.

The conductive grid line a 110 is a silver grid and is manufactured by adopting screen printing; the conducting layer a120 is an indium tin oxide film and is made by magnetron sputtering, and the thickness is 80nm; the electron transport layer a 130 is SnO₂A layer fabricated by Atomic Layer Deposition (ALD) having a thickness of 20nm; the absorption isLayer a 140 is made of a perovskite thin film material FA_1-xCs_xPbI₃Wherein 0.1<x is less than or equal to 1, and the thickness of the film is 700 nm. The hole transport layer a 150 is a nickel oxide layer (NiO)_xLayer) thickness of 20nm;

the p-type semiconductor layer 210 is a vanadium oxide semiconductor with a thickness of 10nm and a carrier concentration of 5 × 10¹⁶cm^-3Mobility of 3X 10^-4cm²/V·s；

The n-type semiconductor layer 220 is a tin oxide semiconductor with a thickness of 10nm and a carrier concentration of 4 × 10¹⁷cm^-3Mobility of 2X 10^-3cm²/V·s。

The conductive grid line b 370 is a silver grid and is manufactured by adopting screen printing; the conducting layer b 360 is an indium tin oxide film and is made by magnetron sputtering, and the thickness is 80nm; the electron transmission layer b 310 is made of an N-type amorphous silicon film through Plasma Enhanced Chemical Vapor Deposition (PECVD), and the thickness of the N-type amorphous silicon film is 10nm; selecting an I-type amorphous silicon film aiming at the passivation layer b 320 or the passivation layer c 340, and manufacturing the I-type amorphous silicon film through Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the thickness of the I-type amorphous silicon film is 10nm; the crystal silicon wafer is selected for the absorption layer b 330, and the thickness of the crystal silicon wafer is 150 μm; the hole transport layer b 350 is made of a P-type amorphous silicon film by Plasma Enhanced Chemical Vapor Deposition (PECVD), and the thickness of the hole transport layer b is 10nm.

Example 2

To the utility model provides a perovskite crystalline silica stromatolite battery structure gives a schematic preparation method, specifically as follows:

respectively plating a passivation layer (a passivation layer b 320 and a passivation layer c 340) on the two surfaces of the cleaned and textured absorption layer b 330 by plasma enhanced chemical vapor deposition;

a hole transport layer b 350 is then deposited on the passivation layer c 340. An electron transport layer b 310 is deposited on the passivation layer b 320.

A conductive layer b 360 was prepared on the hole transport layer b 350 by magnetron sputtering.

An n-type semiconductor layer 220 of a tunnel junction is prepared on the electron transport layer b 310, and a p-type semiconductor layer 210 of a tunnel junction is prepared on the n-type semiconductor layer 220 of the tunnel junction.

The hole transport layer a 150 is then prepared on the p-type semiconductor layer 210.

An absorber layer a 140 is then deposited on the hole transport layer a 150. The deposition method was vacuum co-evaporation. The evaporation raw materials are FAI, MAI and PbI2 respectively; FAI evaporation temperature is 200 ℃, MAI evaporation temperature is 120 ℃, pbI₂The evaporation temperature was 400 ℃. The temperature of the substrate material was 30 ℃.

Depositing an electron transport layer a 130 on the deposited absorption layer a 140; the deposition method was Atomic Layer Deposition (ALD) with a film thickness of 30nm.

And depositing a conductive layer a120 on the deposited electron transport layer a 130 by Reactive Plasma Deposition (RPD).

And preparing a conductive grid line on the deposited conductive layer a120 by screen printing.

And preparing a conductive grid line on the deposited conductive layer b 360 through screen printing.

And (3) completing the preparation of the whole laminated cell, wherein the conductive grid line a 110 on one side of the perovskite solar cell is the cathode of the cell, and the conductive grid line b 370 on one side of the SHJ cell is the anode of the cell.

Example 3

And respectively plating a passivation layer (a passivation layer b 320 and a passivation layer c 340) on two surfaces of the cleaned and textured absorption layer b 330 by plasma enhanced chemical vapor deposition, wherein the thickness of the passivation layer b 320 is 10nm, and the thickness of the passivation layer c 340 is 15nm.

A hole transport layer b 350 was then deposited on the 15nm thick passivation layer c 340 to a thickness of 10nm. An electron transport layer b 310 was deposited on the 10nm thick passivation layer b 320 to a thickness of 15nm.

And preparing a conducting layer b 360 on the hole transport layer b 350 by magnetron sputtering, wherein the conducting layer b is made of Indium Tin Oxide (ITO) and has the thickness of 60nm.

An n-type semiconductor layer 220 of a tunnel junction, i.e., a tin oxide film, is prepared on the electron transport layer b 310 to a thickness of 20nm.

And preparing a vanadium pentoxide layer as a p-type semiconductor layer 210 of the tunneling junction on the n-type semiconductor layer 220 of the tunneling junction, wherein the thickness is 25nm.

A hole transport layer a 150 (i.e. a hole transport layer of perovskite nickel oxide) was then prepared on the p-type semiconductor layer 210 to a thickness of 20nm.

An absorber layer a 140 is then deposited on the hole transport layer a 150. The material of the absorption layer a 140 is FA_0.9MA_0.1PbI₃(ii) a The deposition method is vacuum co-evaporation. The evaporation raw materials are FAI, MAI and PbI2 respectively; FAI evaporation temperature is 200 ℃, MAI evaporation temperature is 120 ℃, pbI evaporation temperature is₂The evaporation temperature was 400 ℃. The temperature of the substrate material was 30 ℃. The thickness of the absorption layer a 140 is 400nm.

Depositing an electron transport layer a 130 on the deposited absorption layer a 140, wherein the material is C60, and the thickness is 10nm; deposition of the material tin oxide SnO on the layer of material C60₂The deposition method is Atomic Layer Deposition (ALD) and the film thickness is 30nm.

And depositing a conductive layer a120 on the deposited electron transport layer a 130, wherein the material is Indium Tin Oxide (ITO). The deposition method is Reactive Plasma Deposition (RPD). The deposited film thickness was 80nm.

And preparing a conductive grid line on the deposited conductive layer a120 by screen printing, wherein the height of the conductive grid line is 20 micrometers, and the width of the conductive grid line is 50 micrometers. The distance between the conductive grid lines is 2 mm.

And preparing a conductive grid line on the deposited conductive layer b 360 by screen printing, wherein the height of the conductive grid line is 20 micrometers, and the width of the conductive grid line is 50 micrometers. The distance between the conductive grid lines is 1.5 mm.

And the whole laminated cell is prepared, wherein the conductive grid line a 110 on one side of the perovskite solar cell is the cathode of the cell, and the conductive grid line b 370 on the side of the SHJ cell is the anode of the cell.

Example 4

And respectively plating a passivation layer (a passivation layer b 320 and a passivation layer c 340) on the two surfaces of the cleaned and textured absorption layer b 330 by plasma enhanced chemical vapor deposition, wherein the thicknesses of the passivation layers b 320 and c 340 are both 10nm.

Then depositing a layer of p-type amorphous silicon on the passivation layer c 340 as a hole transport layer b 350; depositing a layer of n-type amorphous silicon on the passivation layer b 320 as an electron transport layer b 310; the thickness of the p-type amorphous silicon is 20nm, the doping concentration of boron element is 0.5%, the thickness of the n-type amorphous silicon is 15nm, and the doping concentration of phosphorus element is 0.4%.

And preparing a conducting layer b 360 on the hole transport layer b 350 through magnetron sputtering, wherein the material is aluminum-doped zinc oxide (AZO) and the thickness is 200nm.

An n-type semiconductor layer 220 of zinc oxide as a tunnel junction of the stacked cell was prepared on the electron transport layer b 310 to a thickness of 30nm.

And then on the n-type semiconductor layer 220. A p-type semiconductor layer 210 of nickel oxide as a tunnel junction was deposited to a thickness of 15nm.

Then, on the p-type semiconductor layer 210, the hole transport layer a 150 of the perovskite solar cell is prepared by magnetron sputtering. The film thickness was 10nm.

A perovskite absorption layer a 140 is deposited on the hole transport layer a 150. The material of the absorbing layer is FA_0.7MA_0.3PbI₃(ii) a The deposition method is vacuum co-evaporation. The evaporation raw materials are FAI, MAI and PbI2 respectively; FAI evaporation temperature is 200 ℃, MAI evaporation temperature is 140 ℃, pbI evaporation temperature is₂The evaporation temperature was 400 ℃. The temperature of the substrate material was 30 ℃. The thickness of the perovskite absorption layer is 400nm.

Depositing an electron transport layer a 130 on the deposited absorption layer a 140, the material being fullerene (C)₆₀) The deposition method is vacuum evaporation, and the evaporation temperature of the raw materials is 420 ℃. The substrate temperature was 30 ℃. The film thickness was 10nm.

And depositing a front transparent conductive layer a120 on the deposited electron transport layer a 130, wherein the material is indium tungsten oxide (IWO). The deposition method is Reactive Plasma Deposition (RPD). The deposited film thickness was 80nm.

And preparing a conductive grid line on the deposited conductive layer a120 by screen printing, wherein the height of the conductive grid line is 15 micrometers, and the width of the conductive grid line is 60 micrometers. The distance between the conductive grid lines is 2 mm.

And preparing a conductive grid line on the deposited back electrode transparent conductive layer b 360 by screen printing, wherein the height of the conductive grid line is 15 micrometers, and the width of the conductive grid line is 50 micrometers. The distance between the conductive grid lines is 1.5 mm.

And the whole laminated battery is prepared, wherein the conductive grid line on the perovskite side is the anode of the battery, and the conductive grid line on the SHJ battery side is the cathode of the battery.

Example 5

And respectively plating a passivation layer (a passivation layer b 320 and a passivation layer c 340) on the two surfaces of the cleaned and textured absorption layer b 330 by plasma enhanced chemical vapor deposition, wherein the thickness of the passivation layer c 340 is 10nm, and the thickness of the passivation layer b 320 is 12nm.

Then, a p-type amorphous silicon electron transport layer b 310 with the thickness of 10nm is deposited on the passivation layer b 320 with the thickness of 12nm. An n-type amorphous silicon layer was deposited as a hole transport layer b 350 on the 10nm thick passivation layer c 340 to a thickness of 15nm.

And preparing a conducting layer b 360 on the hole transport layer b 350 by magnetron sputtering, wherein the conducting layer b is made of Indium Tin Oxide (ITO) and has the thickness of 100nm.

And preparing a p-type semiconductor layer 210 of molybdenum oxide as a tunnel junction of the laminated cell on the electron transport layer b 310, wherein the thickness is 15nm.

And then preparing an n-type semiconductor layer 220 with tin oxide as a tunneling junction on the p-type semiconductor layer 210 with the thickness of 10nm by adopting magnetron sputtering.

Then, on the n-type semiconductor layer 220, the electron transport layer a 130 of the perovskite solar cell was prepared from tin oxide by a water bath method. The thickness was 15nm.

A perovskite absorption layer a 140 is then deposited on the electron transport layer a. The material of the absorbing layer is FA_0.9MA_0.1PbI₃(ii) a The deposition method is vacuum co-evaporation. The evaporation raw materials are FAI, MAI and PbI2 respectively; FAI evaporation temperature is 200 ℃, MAI evaporation temperature is 120 ℃, pbI₂The evaporation temperature was 400 ℃. The temperature of the substrate material was 30 ℃. The thickness of the perovskite absorption layer is 400nm.

And depositing a hole transport layer a 150 on the deposited absorption layer a 140, wherein the material is nickel oxide, and the deposition method is Atomic Layer Deposition (ALD). The film thickness was 30nm.

And depositing a conductive layer a120 on the deposited hole transport layer a 150, wherein the material is Indium Tin Oxide (ITO). The deposition method is Reactive Plasma Deposition (RPD). The deposited film thickness was 80nm.

And finishing the preparation of the whole laminated cell, wherein the conductive grid line on one side of the perovskite solar cell is the cathode of the cell, and the conductive grid line on the side of the SHJ cell is the anode of the cell.

The structure of the perovskite/crystalline silicon stacked cell structure provided by the present invention and the embodiments thereof have been described above schematically, the description is not limited, and what is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto. Therefore, if the person skilled in the art receives the teaching, without departing from the spirit of the present invention, the person skilled in the art shall not inventively design the similar structural modes and embodiments to the technical solutions, but shall fall within the protection scope of the present invention.

Claims

1. A perovskite/crystalline silicon laminated cell structure is characterized in that,

the battery structure comprises, from front to back:

a perovskite roof battery;

a tunneling junction; and the number of the first and second groups,

a crystalline silicon bottom cell;

in the direction from the front surface to the back surface,

the p-type semiconductor layer is a p-type metal oxide layer, and the n-type semiconductor layer is an n-type metal oxide layer.

2. The perovskite/crystalline silicon stacked cell structure as claimed in claim 1,

the perovskite top battery also comprises a conductive grid line a stacked on the conductive layer a;

the crystalline silicon bottom cell further comprises a conductive grid line b stacked on the conductive layer b.

3. The perovskite/crystalline silicon stacked cell structure as set forth in claim 1,

the conductive layer a has a thickness of 0.08-50 μm;

the thickness of the electronic transmission layer a is 0.1nm to 1000nm;

the absorption layer a has a thickness of 50nm to 3000 nm;

the hole transport layer a has a thickness of 0.1nm to 1000nm;

the electronic transmission layer b has a thickness of 1nm to 100nm;

the passivation layer b has a thickness of 1nm to 100nm;

the passivation layer c has a thickness of 1nm to 100nm;

the thickness of the absorption layer b is 50 to 500 mu m;

the hole transport layer b has a thickness of 1nm to 100nm;

the conductive layer b has a thickness of 0.08-50 μm.

4. The perovskite/crystalline silicon stacked cell structure of any one of claims 1 to 3, wherein the tunneling junction has a value of 10⁴Ω·cm~10^-3Resistivity of Ω · cm.

5. The perovskite/crystalline silicon stacked cell structure as claimed in claim 4,

the p-type semiconductor layer has a thickness of 1 to 200nm;

the n-type semiconductor layer has a thickness of 1 to 200nm.

6. The perovskite/crystalline silicon stacked cell structure as claimed in claim 4,

the p-type metal oxide layer is a vanadium oxide layer, or a nickel oxide layer, or a molybdenum oxide layer, or a copper oxide layer, or cuprous oxide layer;

the n-type metal oxide layer is a tin oxide layer, a zinc oxide layer, a titanium oxide layer or an indium oxide layer.

7. The perovskite/crystalline silicon stacked cell structure of claim 4,

the conducting layer a is an indium tin oxide film;

the electron transmission layer a is a tin oxide layer or a titanium oxide layer or a zinc oxide layer;

the absorption layer a is a perovskite thin film;

the hole transport layer a is a nickel oxide layer.

8. The perovskite/crystalline silicon stacked cell structure of claim 4,

the electron transmission layer b is an N-type amorphous silicon film;

the passivation layer b is an I-type amorphous silicon film;

the absorption layer b is a crystal silicon wafer;

the passivation layer c is an I-type amorphous silicon film;

the hole transport layer b is a P-type amorphous silicon film;

the conducting layer b is an indium tin oxide film.

9. The perovskite/crystalline silicon stacked cell structure of claim 8,

the perovskite thin film is FA_1-xCs_xPbI₃A film;

the crystal silicon wafer is an N-type crystal silicon wafer or a P-type crystal silicon wafer.

10. The perovskite/crystalline silicon stacked cell structure of claim 5,

the tunneling junction further comprises a carrier;

wherein the carriers comprise holes and electrons; the p-type semiconductor layer includes holes and the n-type semiconductor layer includes electrons;

the p-type semiconductor layer has a carrier mobility of 1 × 10⁻⁸cm²/V·s~1×10⁻²cm²/V·s；

The carrier mobility of the n-type semiconductor layer is 1 × 10⁻⁸cm²/V·s~1×10⁻²cm²/V·s。