CN216286205U - Power switch control circuit and electronic equipment - Google Patents
Power switch control circuit and electronic equipment Download PDFInfo
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- CN216286205U CN216286205U CN202121819636.0U CN202121819636U CN216286205U CN 216286205 U CN216286205 U CN 216286205U CN 202121819636 U CN202121819636 U CN 202121819636U CN 216286205 U CN216286205 U CN 216286205U
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Abstract
The embodiment of the application discloses a power switch control circuit and electronic equipment. The power switch control circuit comprises an MCU module, a traffic blocking module and a power output module; and a PWM signal output module is arranged in the MCU module, the PWM signal output module is connected with the input end of the AC blocking module, and the output end of the AC blocking module is connected with the power output module. The situation that a rear-stage circuit is conducted when the master control MCU module is abnormally started is avoided, and the stability of the power switch control circuit is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of power switches, in particular to a power switch control circuit and electronic equipment.
Background
In an application circuit that needs to control the power on and off of a peripheral, a certain IO pin of a main controller is usually used to output a fixed level signal to control the power on or off, and if the pin outputs a high level to control the power on, the pin outputs a low level to control the power off.
When the master control is not normally started or runs abnormally, the level state of the IO pin cannot be determined, and may be high or low, and the state of the power switch cannot be determined, so that the risk that the master control is abnormal but the power control is still turned on exists.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a power switch control circuit and electronic equipment, which can solve the problem of unstable control of a power switch and improve the stability of the power switch control circuit.
The embodiment of the application provides a power switch control circuit, which comprises an MCU module, an AC blocking module and a power output module;
and a PWM signal output module is arranged in the MCU module, the PWM signal output module is connected with the input end of the AC blocking module, and the output end of the AC blocking module is connected with the power output module.
Further, the traffic blocking module comprises a capacitor-diode module and an MOS (metal oxide semiconductor) module; the PWM signal output module is connected with the input end of the capacitor-diode module, the output end of the capacitor-diode module is connected with the grid end of the MOS transistor module, the drain end of the MOS transistor module is connected with the power output module, the source end of the MOS transistor module is grounded, the capacitor-diode module is used for controlling the conduction of the drain end and the source end of the MOS transistor, and the MOS transistor is used for controlling the voltage output of the power output module.
Further, the capacitor-diode module comprises a first capacitor (C1), a second capacitor (C2), a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2) and a third resistor (R3);
the PWM signal output module is connected with one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected with the cathode of the first diode (D1) and the anode of the second diode (D2);
the negative pole of second diode (D2) is connected the one end of first resistance (R1), the other end of first resistance (R1) with the one end of second electric capacity (C2), the one end of second resistance (R2) and the one end of third resistance (R3) is connected, the other end of third resistance (R3) with the MOS transistor module is connected, the positive pole of first diode (D1), the other end of second electric capacity (C2) and the other end of second resistance (R2) all ground.
Further, the MOS transistor module comprises a first MOS transistor (Q1), a fourth resistor (R4) and a fifth resistor (R5);
the grid of the first MOS tube (Q1) is connected with the other end of the third resistor (R3), the drain of the first MOS tube (Q1) is connected with one end of the fourth resistor (R4) and one end of the fifth resistor (R5), the other end of the fourth resistor (R4) and the other end of the fifth resistor (R5) are connected with the power output module, and the source of the first MOS tube (Q1) is grounded.
Further, the power supply output module comprises a power supply VCC and a second MOS (Q2);
the power supply VCC is connected with the source electrode of the second MOS tube (Q2);
the other end of the fourth resistor (R4) is connected with the power supply VCC and the source electrode of the second MOS tube (Q2), the other end of the fifth resistor (R5) is connected with the grid electrode of the second MOS tube (Q2), the drain electrode of the second MOS tube (Q2) is connected with one end of a rear-stage circuit (RL), and the other end of the rear-stage circuit (RL) is grounded.
Further, the first MOS transistor (Q1) is an NMOS transistor, and the second MOS transistor (Q2) is a PMOS transistor.
Further, the capacitance value of the first capacitor (C1) is 1uF, the capacitance value of the second capacitor (C2) is 0.1uF, the types of the first diode (D1) and the second diode (D2) are both 1N4148WS, the resistance value of the first resistor (R1) is 100 Ω, the resistance value of the second resistor (R2) is 10K Ω, and the resistance value of the third resistor (R3) is 1K Ω.
Furthermore, the model of the first MOS transistor (Q1) is 2N7002, the resistance of the fourth resistor (R4) is 100K omega, and the resistance of the fifth resistor (R5) is 1K omega.
Further, the PWM signal output by the PWM signal output module is 10 KHz.
The embodiment of the application also provides electronic equipment which comprises the power switch control circuit.
The embodiment of the application provides a power switch control circuit, has following beneficial effect:
through adopting the PWM signal output module in the MCU module to output the PWM signal, the warp the interchange of interchange stopping the direct current effect, when the MCU module starts normal output PWM signal, back level switch control circuit just switches on, the condition that back level circuit also can switch on when avoiding appearing master control MCU module abnormal start has improved switch control circuit's stability.
Drawings
Fig. 1 is a schematic circuit diagram of a power switch control circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Fig. 1 shows a schematic circuit diagram of a power switch control circuit provided in an embodiment of the present application, and as shown in fig. 1, the power switch control circuit includes an MCU module, an ac/dc blocking module 11, and a power output module 12;
a PWM signal output module is arranged in the MCU module, the PWM signal output module is connected with the input end of the traffic stopping module 11, and the output end of the traffic stopping module 11 is connected with the power output module 12.
Further, the traffic blocking module 11 comprises a capacitance-diode module 13 and a MOS transistor module 14; the PWM signal output module is connected to an input terminal of the capacitor-diode module 13, an output terminal of the capacitor-diode module 13 is connected to a gate terminal of the MOS transistor module 14, a drain terminal of the MOS transistor module 14 is connected to the power output module 12, a source terminal of the MOS transistor module 14 is grounded, the capacitor-diode module 13 is configured to control conduction of the drain terminal and the source terminal of the MOS transistor, and the MOS transistor is configured to control voltage output of the power output module 12.
Further, the capacitor-diode module 13 includes a first capacitor (C1), a second capacitor (C2), a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2), and a third resistor (R3);
the PWM signal output module is connected with one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected with the cathode of the first diode (D1) and the anode of the second diode (D2);
the negative pole of second diode (D2) is connected the one end of first resistance (R1), the other end of first resistance (R1) with the one end of second electric capacity (C2), the one end of second resistance (R2) and the one end of third resistance (R3) is connected, the other end of third resistance (R3) with MOS transistor module 14 is connected, the positive pole of first diode (D1), the other end of second electric capacity (C2) and the other end of second resistance (R2) all ground.
Further, the MOS transistor module 14 includes a first MOS transistor (Q1), a fourth resistor (R4), and a fifth resistor (R5);
the grid of the first MOS transistor (Q1) is connected with the other end of the third resistor (R3), the drain of the first MOS transistor (Q1) is connected with one end of the fourth resistor (R4) and one end of the fifth resistor (R5), the other end of the fourth resistor (R4) and the other end of the fifth resistor (R5) are connected with the power output module 12, and the source of the first MOS transistor (Q1) is grounded.
Further, the power output module 12 includes a power VCC and a second MOS transistor (Q2);
the power supply VCC is connected with the source electrode of the second MOS tube (Q2);
the other end of the fourth resistor (R4) is connected with the power supply VCC and the source electrode of the second MOS tube (Q2), the other end of the fifth resistor (R5) is connected with the grid electrode of the second MOS tube (Q2), the drain electrode of the second MOS tube (Q2) is connected with one end of a rear-stage circuit (RL), and the other end of the rear-stage circuit (RL) is grounded.
Further, the first MOS transistor (Q1) is an NMOS transistor, and the second MOS transistor (Q2) is a PMOS transistor.
Further, the capacitance value of the first capacitor (C1) is 1uF, the capacitance value of the second capacitor (C2) is 0.1uF, the types of the first diode (D1) and the second diode (D2) are both 1N4148WS, the resistance value of the first resistor (R1) is 100 Ω, the resistance value of the second resistor (R2) is 10K Ω, and the resistance value of the third resistor (R3) is 1K Ω.
Furthermore, the model of the first MOS transistor (Q1) is 2N7002, the resistance of the fourth resistor (R4) is 100K omega, and the resistance of the fifth resistor (R5) is 1K omega.
Further, the PWM signal output by the PWM signal output module is 10 KHz.
Exemplarily, after the main control MCU module is normally started and operated, the PWM signal output module outputs a PWM signal to the first capacitor (C1), and when the main control MCU module is not normally started or is abnormal, the PWM signal output module cannot output a PWM signal with alternating high and low levels, so that the first capacitor (C1) blocks direct current, thereby causing the first MOS transistor (Q1) to be non-conductive, and the power switch is not turned on.
For example, referring to fig. 1, the main control MCU module outputs a PWM signal through the PWM signal output module, the first capacitor (C1) plays a role of alternating current and direct current, and the direct current signal cannot pass through the C1, so that the power switch control circuit can continue to operate only when the MCU module continuously outputs the PWM signal. When the PWM signal is a high level signal, the PWM high level signal passes through the first capacitor (C1), and then charges the second capacitor (C2) through the second diode (D2) and the first resistor (R1). When the PWM signal is a low level signal, the second capacitor (C2) discharges after the PWM low level signal passes through the first capacitor (C1), the voltage on the second capacitor (C2) is applied to the gate (G) and the source (S) of the first MOS transistor (Q1) through the third resistor (R3), and the first MOS transistor (Q1) turns on the drain (D) and the source (S). Since the source (S) of the first MOS transistor (Q1) is grounded, the gate (G) of the second MOS transistor (Q2) is also pulled to ground through the second resistor (R5), and the second MOS transistor (Q2) is turned on, so that the power VCC can be applied to the subsequent circuit (RL) through the second MOS transistor (Q2).
Illustratively, when the main control MCU module is not normally started or abnormally operated, the MCU module cannot output the PWM signal and changes to a continuous high level or a continuous low level. Due to the existence of the first capacitor (C1) of the blocking capacitor, the continuous high level or the continuous low level of the master control output cannot be loaded on a rear-stage circuit through the first capacitor (C1), the first MOS transistor (Q1) and the second MOS transistor (Q2) are turned off by default, and the power supply is turned off by default, so that the risk that the power supply is possibly turned on when the master control is abnormal is avoided.
In this scheme, through adopting the PWM signal output module in the MCU module to output the PWM signal, the warp the interchange of interchange DC blocking module 11 separates the direct current effect, when the MCU module starts normal output PWM signal, back stage switch control circuit just switches on, and the condition that back stage circuit also can switch on when avoiding appearing master control MCU module and starting unusually has improved switch control circuit's stability.
The embodiment of the application also provides electronic equipment which comprises the power switch control circuit.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the utility model.
In the present invention, unless otherwise expressly stated or limited, the terms "disposed," "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; they may be mechanically coupled, directly coupled, or indirectly coupled through intervening agents, both internally and/or in any other manner known to those skilled in the art. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
It is noted that in the present disclosure, unless otherwise explicitly specified or limited, a first feature "on" or "under" a second feature may be directly contacted with the first and second features, or indirectly contacted with the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and equivalent alternatives or modifications according to the technical solution of the present invention and the inventive concept thereof should be covered by the scope of the present invention.
Claims (10)
1. A power switch control circuit is characterized by comprising an MCU module, an AC blocking module and a power output module;
and a PWM signal output module is arranged in the MCU module, the PWM signal output module is connected with the input end of the AC blocking module, and the output end of the AC blocking module is connected with the power output module.
2. The power switch control circuit of claim 1, wherein the traffic blocking module comprises a capacitor-diode module and a MOS transistor module; the PWM signal output module is connected with the input end of the capacitor-diode module, the output end of the capacitor-diode module is connected with the grid end of the MOS transistor module, the drain end of the MOS transistor module is connected with the power output module, the source end of the MOS transistor module is grounded, the capacitor-diode module is used for controlling the conduction of the drain end and the source end of the MOS transistor, and the MOS transistor is used for controlling the voltage output of the power output module.
3. The power switch control circuit of claim 2, wherein the capacitor-diode module comprises a first capacitor (C1), a second capacitor (C2), a first diode (D1), a second diode (D2), a first resistor (R1), a second resistor (R2), and a third resistor (R3);
the PWM signal output module is connected with one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected with the cathode of the first diode (D1) and the anode of the second diode (D2);
the negative pole of second diode (D2) is connected the one end of first resistance (R1), the other end of first resistance (R1) with the one end of second electric capacity (C2), the one end of second resistance (R2) and the one end of third resistance (R3) is connected, the other end of third resistance (R3) with the MOS transistor module is connected, the positive pole of first diode (D1), the other end of second electric capacity (C2) and the other end of second resistance (R2) all ground.
4. The power switch control circuit of claim 3, wherein the MOS transistor module comprises a first MOS transistor (Q1), a fourth resistor (R4) and a fifth resistor (R5);
the grid of the first MOS tube (Q1) is connected with the other end of the third resistor (R3), the drain of the first MOS tube (Q1) is connected with one end of the fourth resistor (R4) and one end of the fifth resistor (R5), the other end of the fourth resistor (R4) and the other end of the fifth resistor (R5) are connected with the power output module, and the source of the first MOS tube (Q1) is grounded.
5. The power switch control circuit of claim 4, wherein the power output module comprises a power source VCC and a second MOS transistor (Q2);
the power supply VCC is connected with the source electrode of the second MOS tube (Q2);
the other end of the fourth resistor (R4) is connected with the power supply VCC and the source electrode of the second MOS tube (Q2), the other end of the fifth resistor (R5) is connected with the grid electrode of the second MOS tube (Q2), the drain electrode of the second MOS tube (Q2) is connected with one end of a rear-stage circuit (RL), and the other end of the rear-stage circuit (RL) is grounded.
6. The power switch control circuit of claim 5, wherein the first MOS transistor (Q1) is an NMOS transistor, and the second MOS transistor (Q2) is a PMOS transistor.
7. The power switch control circuit of claim 3, wherein the capacitance of the first capacitor (C1) is 1uF, the capacitance of the second capacitor (C2) is 0.1uF, the types of the first diode (D1) and the second diode (D2) are 1N4148WS, the resistance of the first resistor (R1) is 100 Ω, the resistance of the second resistor (R2) is 10K Ω, and the resistance of the third resistor (R3) is 1K Ω.
8. The power switch control circuit according to claim 4, wherein the first MOS transistor (Q1) is 2N7002, the fourth resistor (R4) is 100K Ω, and the fifth resistor (R5) is 1K Ω.
9. The power switch control circuit of claim 1, wherein the PWM signal output module outputs a PWM signal of 10 KHz.
10. An electronic device comprising the power switch control circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121819636.0U CN216286205U (en) | 2021-08-05 | 2021-08-05 | Power switch control circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121819636.0U CN216286205U (en) | 2021-08-05 | 2021-08-05 | Power switch control circuit and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216286205U true CN216286205U (en) | 2022-04-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121819636.0U Active CN216286205U (en) | 2021-08-05 | 2021-08-05 | Power switch control circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216286205U (en) |
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- 2021-08-05 CN CN202121819636.0U patent/CN216286205U/en active Active
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