CN214672618U - Packaging structure - Google Patents

Abstract

The utility model discloses a packaging structure, this packaging structure includes: a chip unit, a first surface of the chip unit including a sensing region; an upper cover plate covering the first surface of the chip unit; and the supporting structure is positioned between the upper cover plate and the chip unit, the sensing area is positioned in a cavity enclosed by the supporting structure and the first surface of the chip unit, and a light absorption layer covers the surface of the inner wall of the cavity. The utility model discloses an inner wall surface covering at the cavity has the light-absorption layer, can absorb the reflection light through the cavity lateral wall, avoids this light to disturb the positive response area.

Description

Packaging structure

Technical Field

The utility model belongs to the technical field of the semiconductor, concretely relates to packaging structure.

Background

Wafer level Chip Packaging (WLCSP) is a technology in which a whole wafer is subjected to a Packaging test and then cut to obtain a single finished Chip, and the size of the packaged Chip is consistent with that of a bare Chip. The wafer level chip packaging technology subverts the mode of traditional packaging such as Ceramic Leadless chip carriers (Ceramic Leadless chip carriers) and Organic Leadless chip carriers (Organic Leadless chip carriers), and meets the increasingly light, small, short, thin and low-price requirements of the market on microelectronic products. The chip packaged by the wafer level chip packaging technology achieves high miniaturization, and the chip cost is obviously reduced along with the reduction of the chip and the increase of the wafer size. The wafer level chip packaging technology is a technology capable of integrating IC design, wafer manufacturing, packaging test and integration, and is a hot spot and development trend in the current packaging field.

In the existing wafer level packaging technology, especially for packaging of an image sensing chip, an upper cover substrate is usually covered on one surface of a semiconductor wafer on which a device is formed, so as to protect the device from being damaged and polluted in the packaging process, and protect the device.

With the trend of miniaturization of wafer level chip packages, the more finished chip packages are integrated on a wafer level chip, the smaller the size of a single finished chip package is, the smaller the distance between a corresponding sensing area and a cavity side wall is, and the more obvious the interference of light reflection on the sensing area is.

Chinese patent CN205789975U discloses an image sensor package structure, which uses a cofferdam with a rack-shaped inner side wall higher than 100 microns to replace a low photoresist polymer cofferdam, increasing the height of the cofferdam, increasing the distance between the contamination particles on the surface of the transparent cover plate and the photosensitive area, and reducing the influence area of the light reaching the photosensitive area after being blocked by the particles; the cofferdam inside wall is the rack form, and the tooth's socket is the arc, can make the cofferdam inside wall coarse, can't form the mirror surface to effectively restrain oblique ray or sensitization district reflection light at the reflection of cofferdam inside wall, reduce the interference light who incides the sensitization district, improve the formation of image quality. However, the thickness of the final package is greatly increased by increasing the height of the wall, especially the wall above 100um, which is contrary to the current trend of miniaturization and lightness (the height of the wall is generally 30-40 um).

How to provide a package structure and a method thereof that have a light and thin structure and can reduce the incident interference light to the photosensitive region is a problem that needs to be solved urgently.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a packaging structure for can't satisfy light thin and anti-interference problem simultaneously among the solution prior art, include:

a package structure, comprising:

a chip unit, a first surface of the chip unit including a sensing region;

an upper cover plate covering the first surface of the chip unit;

a support structure located between the upper cover plate and the chip unit, and the sensing region located in a cavity enclosed by the support structure and the first surface of the chip unit,

and the surface of the inner wall of the cavity is covered with a light absorption layer.

In one embodiment, the light absorbing layer extends between the support structure and the chip unit.

In one embodiment, the light absorbing layer is glued to the first surface of the chip unit.

In one embodiment, the light absorbing layer is a black bonding adhesive.

In one embodiment, the chip unit further includes:

the welding pad is positioned outside the sensing area;

a through hole penetrating the chip unit from a second surface of the chip unit opposite to the first surface, the through hole exposing the pad;

an insulating layer covering the second surface of the chip unit and the surface of the side wall of the through hole;

the metal layer is positioned on the surface of the insulating layer and electrically connected with the welding pad;

the solder mask is positioned on the surfaces of the metal layer and the insulating layer and is provided with an opening for exposing a part of the metal layer;

and filling the opening and exposing the external connection bump outside the surface of the solder resist layer.

In one embodiment, the upper cover plate is configured to have a predetermined thickness and/or shape and/or a surface thereof is covered with a light shielding layer, so that light reflected from a sidewall of the upper cover plate cannot directly irradiate or is reduced from irradiating the sensing region.

Compared with the prior art, the utility model discloses in cover through the inner wall surface at the cavity has the light-absorbing layer, can absorb the reflection light through the cavity lateral wall, avoids this light to disturb the positive response region.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a sectional view of a package structure in embodiment 1 of the present application;

FIG. 2 is a prior art optical path diagram of light interference with a sensing region;

fig. 3 to 12 are schematic views of intermediate structures formed by the package structure in embodiment 1 of the present application;

fig. 13 is a sectional view of a package structure in embodiment 2 of the present application;

fig. 14 to 18 are schematic views of intermediate structures formed by the package structure in embodiment 2 of the present application;

fig. 19 is a schematic structural view of a light absorbing layer in embodiment 3 of the present application.

Detailed Description

The present invention will be more fully understood from the following detailed description, which should be read in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed embodiment.

Example 1

The present embodiment provides a package structure, and referring to fig. 1, the package structure includes a chip unit 10 and an upper cover plate 20.

In one embodiment, the chip unit is preferably an image sensor chip unit.

The chip unit 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a, and the first surface 10a includes a sensing region 11.

The chip unit 10 further includes a pad 12, a via (not labeled), an insulating layer 13, a metal layer 14, a solder resist layer 15, and a circumscribed bump 16.

The bonding pad 12 is located outside the sensing region 11; the through hole penetrates through a second surface, opposite to the first surface, of the chip unit, and the through hole exposes the welding pad 12; the insulating layer 13 covers the second surface of the chip unit and the side wall surface of the through hole; the metal layer 14 is positioned on the surface of the insulating layer 13 and electrically connected with the bonding pad 12; the solder mask layer 15 is positioned on the surfaces of the metal layer 14 and the insulating layer 13, and the solder mask layer 15 is provided with an opening for exposing part of the metal layer 14; the external bump 16 fills the opening and is exposed outside the surface of the solder resist layer 15.

The upper cover plate 20 includes a first surface 20a and a second surface 20b opposite to the first surface 20a, the first surface 20a is provided with a supporting structure 30, the upper cover plate 20 covers the first surface 10a of the chip unit 10, the supporting structure 30 is supported between the upper cover plate 20 and the chip unit 10, and the sensing region 11 is located in a cavity 31 enclosed by the supporting structure 30 and the first surface 10a of the chip unit 10.

As shown in fig. 2, 4 light rays are emitted from the same light source and reach the photosensitive region through the upper cover plate (high light transmittance glass), wherein the light ray s2 passes through the upper cover plate and is reflected by the cavity sidewall, which interferes with the photosensitive region. Along with the technical development of a wafer factory and the requirement of miniaturization of packaging size, the size of a non-induction area part of a chip is smaller and smaller, namely, the distance between a cavity side wall reflecting surface and an induction area is continuously reduced, light reflected to the induction area through the surface is increased, interference is increased and strengthened, and therefore final imaging quality is influenced, the influence of the edge area of an image is maximum, and a dazzling phenomenon can be generated.

To overcome the interference of the light ray s2 in fig. 2, the present embodiment covers the sidewalls of the cavity 31 with a light absorbing layer 40.

In one embodiment, the light absorbing layer 40 is a black adhesive that extends between the contact surfaces of the support structure 30 and the chip unit 10.

In the technical scheme, the black bonding glue can realize the adhesion between the supporting structure and the chip unit on one hand, and on the other hand, the black bonding glue covers the inner wall of the cavity and can absorb the reflected light rays passing through the side wall of the cavity.

Referring to fig. 2, in order to overcome the interference of the light rays s1 and s3, the upper cover plate 20 is provided with a predetermined thickness, shape and/or surface thereof covered with a light shielding layer, so that the light rays reflected from the side wall of the upper cover plate cannot directly irradiate or reduce the irradiation to the sensing area.

Light ray s1 is the light ray reflected by the side edge of the upper cover plate and is the interference light ray; light s3 reflects off the sides of the top cover and is transmitted through the cavity sidewall/sidewall bond (non-absorbing bond) and interferes with the light.

In one embodiment, the area of the second surface 20a of the upper plate 20 is smaller than the area of the first surface 20b (not shown), and the package structure can reduce the interference light incident on the sensing region. For example, the side wall of the upper cover plate includes a vertical wall and an inclined wall, a first end of which is connected to an edge of the second surface of the upper cover plate, and an opposite second end of which is connected to a top end of the vertical wall. The side wall structure with the inclined wall can prevent light rays reflected on the side wall from entering the upper cover plate structure, interference light rays reflected from the side wall of the upper cover plate and entering the sensing area are reduced, and therefore imaging quality of a chip packaging structure used as an image sensor can be improved. This technology is prior art (CN205050824U) and will not be described in detail.

In an embodiment, a light shielding layer (not shown) is disposed on a surface of the upper cover plate 20, and the light shielding layer covers a second surface of the upper cover plate opposite to the first surface, or is disposed on a side surface of the upper cover plate 20 and exposes a middle area opposite to the sensing area. The packaging structure can reduce interference light incident to the sensing area. The technology is the prior art (CN204991711U, CN105244360A and CN106449546A) and is not described in detail.

In one embodiment, the upper cover plate has a predetermined thickness of 50 μm to 200 μm, so that the light reflected from the sidewall of the upper cover plate cannot directly irradiate the sensing region. This technique is prior art (105118843a) and will not be described in detail.

Correspondingly, the embodiment of the invention provides a packaging method for forming the packaging structure shown in fig. 1. Please refer to fig. 3 to 12, which are schematic diagrams of intermediate structures formed in the packaging process of the packaging method according to an embodiment of the present invention.

First, referring to fig. 3 and 4, a wafer 200 to be packaged is provided, wherein fig. 3 is a schematic top view of the wafer 200 to be packaged, and fig. 4 is a cross-sectional view taken along a-a1 in fig. 3.

The chip unit 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a, and the first surface 10a includes a sensing region 11.

The wafer to be packaged 200 has a plurality of chip units 10 and scribe line regions 210 located between the chip units 10.

In this embodiment, the plurality of chip units 10 on the wafer 200 to be packaged are arranged in an array, the dicing street region 210 is located between adjacent chip units 10, and subsequently, the wafer 200 to be packaged is diced along the dicing street region 210, so that a plurality of chip packaging structures including the chip units 10 can be formed.

In this embodiment, the chip unit 10 is an image sensor chip unit, and the chip unit 10 has a sensing region 11 and a pad 12 outside the sensing region 11. The sensing region 11 is an optical sensing region, and may be formed by a plurality of photodiodes arranged in an array, for example, and the photodiodes may convert optical signals irradiated to the sensing region 11 into electrical signals. The pads 12 serve as input and output terminals for the connection of the devices in the sensing region 11 to external circuitry.

In some embodiments, the chip unit 10 is formed on a silicon substrate, and the chip unit 10 may further include other functional devices formed in the silicon substrate.

It should be noted that, in the subsequent steps of the packaging method of the embodiment of the present invention, for the sake of simplicity and clarity, only the cross-sectional view along the direction a-a1 of the wafer 200 to be packaged is taken as an example for illustration, and similar process steps are performed in other areas.

Next, referring to fig. 5 to 7, an upper cover plate 20 is provided, the upper cover plate 20 includes a first surface 20a and a second surface 20b opposite to the first surface 20a, a plurality of supporting structures 30 are formed on the first surface 20a of the upper cover plate 20, and a groove structure defined by the supporting structures 30 and the first surface 20a of the upper cover plate 20 corresponds to the sensing region 11 on the wafer 200 to be packaged.

In this embodiment, the upper cover plate 20 covers the first surface 10a of the wafer 200 to be packaged in the subsequent process, and is used for protecting the sensing region 11 on the wafer 200 to be packaged. Since it is necessary that the light reaches the sensing region 11 through the upper cover plate 20, the upper cover plate 20 has high light transmittance and is made of a light-transmitting material. Both surfaces of the upper cover plate 20 are flat and smooth, and do not scatter or diffuse incident light.

Specifically, the material of the upper cover plate 20 may be inorganic glass, organic glass, or other light-transmitting material with a specific strength. In the present embodiment, the thickness of the upper cover plate 20 is 300 μm to 500 μm, and may be 400 μm, for example. If the thickness of the upper cover plate 20 is too large, the thickness of the finally formed chip packaging structure is too large, and the requirement of thinning and lightening of electronic products cannot be met; if the thickness of the upper cover plate 20 is too small, the strength of the upper cover plate 20 is small, and the upper cover plate is easily damaged, so that the sensing area covered subsequently cannot be sufficiently protected.

In some embodiments, the support structures 30 are formed by etching after depositing a layer of support structure material on the first surface 20a of the upper cover plate 20. Specifically, a layer of support structure material covering the first surface 20a of the upper cover plate 20 is formed, and then patterned, and after removing a portion of the layer of support structure material, the support structure 30 is formed. The position of the groove structure defined by the supporting structure 30 and the first surface 20a of the upper cover plate 20 on the upper cover plate 20 corresponds to the position of the sensing region 11 on the wafer 200 to be packaged, so that after the subsequent bonding process, the sensing region 11 can be located in the groove defined by the supporting structure 30 and the first surface 20a of the upper cover plate 20.

In some embodiments, the material of the support structure material layer is a wet film or a dry film photoresist, and is formed by spraying, spin coating, or pasting, and the support structure 30 is formed after the support structure material layer is exposed and developed to be patterned.

In some embodiments, the support structure material layer may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and is formed by a deposition process, and then patterned by a photolithography and etching process to form the support structure 30.

In other embodiments, the support structure 30 may be formed by etching the upper cover plate 20. Specifically, a patterned photoresist layer may be formed on the upper cover plate 20, and then the upper cover plate 20 is etched by using the patterned photoresist layer as a mask, so as to form the support structure 30 in the upper cover plate 20, where the support structure 30 is a protruding portion on the first surface 20a of the upper cover plate 20.

Next, referring to fig. 8, a layer of black bonding glue 40 is formed on the surface of the supporting structure 30 opposite to the first surface 10a of the chip unit 10. The gluing method can be roller glue brushing or screen printing and the like.

Then, referring to fig. 9a, 9b and 9c, the first surface 20a of the upper cover plate 20 is opposite to and bonded to the first surface 10a of the wafer 200 to be packaged, so that the supporting structure 30 is bonded to the first surface 10a of the wafer 200 to be packaged, and the bonding process is controlled by pressure, temperature, time, etc., so that a part of the black bonding glue flows to the side edge of the cavity wall under the action of temperature and pressure and covers the cavity wall completely, but does not flow to the sensing region.

In this embodiment, after the first surface 20a of the upper cover plate 20 and the first surface 10a of the wafer 200 to be packaged are combined relatively, the supporting structure 30 and the first surface 10a of the wafer 200 to be packaged form a cavity. The position of the cavity corresponds to the position of the sensing region 11, and the area of the cavity is slightly larger than that of the sensing region 11, so that the sensing region 11 can be located in the cavity. In this embodiment, after the upper cover plate 20 and the wafer 200 to be packaged are combined, the pads 12 on the wafer 200 to be packaged are covered by the support structures 30 on the upper cover plate 20. The upper cover plate 20 may serve to protect the wafer 200 to be packaged in a subsequent process.

Next, referring to fig. 10, a packaging process is performed on the wafer 200 to be packaged.

Specifically, firstly, thinning the wafer 200 to be packaged from the second surface 10b of the wafer 200 to be packaged so as to facilitate the subsequent etching of the through hole, and the thinning of the wafer 200 to be packaged can adopt a mechanical grinding process, a chemical mechanical grinding process and the like; then, etching the wafer 200 to be packaged from the second surface 10b of the wafer 200 to be packaged to form a through hole (not labeled), wherein the through hole exposes the bonding pad 12 on one side of the first surface 10a of the wafer 200 to be packaged; then, forming an insulating layer 13 on the second surface 10b of the wafer 200 to be packaged and on the sidewall of the through hole, where the insulating layer 13 exposes the pad 12 at the bottom of the through hole, the insulating layer 13 may provide electrical insulation for the second surface 10b of the wafer 200 to be packaged, and may also provide electrical insulation for the substrate of the wafer 200 to be packaged exposed by the through hole, and the insulating layer 13 may be made of silicon oxide, silicon nitride, silicon oxynitride, or insulating resin; then, forming a metal layer 14 connected with the bonding pad 12 on the surface of the insulating layer 13, wherein the metal layer 14 can be used as a rewiring layer, the bonding pad 12 is led to the second surface 10b of the wafer 200 to be packaged and then is connected with an external circuit, and the metal layer 14 is formed after metal film deposition and metal film etching; then, forming a solder mask layer 15 with an opening (not labeled) on the surface of the metal layer 14 and the surface of the insulating layer 13, wherein the opening exposes a part of the surface of the metal layer 14, and the solder mask layer 15 is made of insulating dielectric materials such as silicon oxide and silicon nitride and is used for protecting the metal layer 14; then, an external bump 16 is formed on the surface of the solder mask layer 15, the external bump 16 fills the opening, the external bump 16 may be a solder ball, a metal pillar, or other connection structure, and the material may be a metal material such as copper, aluminum, gold, tin, or lead.

After the wafer 200 to be packaged is packaged, the chip package structure obtained by subsequent cutting may be connected to an external circuit through the external connection bump 16. After the sensing region 11 of the chip unit converts the optical signal into an electrical signal, the electrical signal may sequentially pass through the pad 12, the metal layer 14 and the external bump 16, and be transmitted to an external circuit for processing.

Next, referring to fig. 11 and 12, the wafer 200 to be packaged and the upper cover plate 20 are diced along the scribe line region 210 of the wafer 200 to be packaged, so as to form a plurality of package structures as shown in fig. 1.

The cutting can be performed by a slicing knife or a laser cutting, and the slicing knife can be performed by a metal knife or a resin knife.

Example 2

In the present embodiment, another package structure is provided, and referring to fig. 13, compared to embodiment 1, the light absorbing layer 40 in the present embodiment does not use a bonding glue, and it preferably uses a black chrome material.

In order to achieve bonding between the upper cover plate 20 and the wafer 200 to be packaged, bonding between the light absorbing layer 40 and the first surface 10a of the wafer 200 to be packaged is achieved through the adhesive layer 301.

In this embodiment, the upper cover plate 20 and the wafer 200 to be packaged are bonded by an adhesive layer (not shown). For example, an adhesive layer may be formed on the top surface of the formed light absorbing layer 40 and/or the first surface 10a of the wafer 200 to be packaged by a spraying, spin coating or pasting process, and the first surface 20a of the upper cover plate 20 and the first surface 10a of the wafer 200 to be packaged are pressed against each other and bonded by the adhesive layer. The adhesive layer can realize the adhesive function and also can play the insulating and sealing functions. The adhesive layer may be a polymer adhesive material, such as a polymer material, e.g., silicone, epoxy, benzocyclobutene, etc.

Except for the above differences, the structure of embodiment 2 is similar to that of embodiment 1, and the description is omitted.

Correspondingly, the embodiment of the present invention provides a method for manufacturing a light-absorbing layer (the encapsulation method is the same as that of embodiment 1, and is not repeated here). Please refer to fig. 14 to 17, which are schematic diagrams illustrating intermediate structures formed by the light absorbing layer according to an embodiment of the present invention.

First, referring to FIG. 14, a light absorbing film 302 (e.g., black chrome vapor deposition) is deposited on the sidewalls of the cavity and the top cover plate 20;

next, as shown in fig. 15, a photoresist 303 is sprayed on the light absorbing film 302, and a pattern is formed by photolithography (exposure, development);

then, as shown in fig. 16, the light absorbing film is etched (e.g., chemically) and the photoresist 303 is removed, forming the light absorbing layer 40.

Finally, referring to fig. 17 and 18, an adhesive layer 304 is spin-coated on the surface of the light absorbing layer 40, the upper cover plate 20 and the wafer 200 to be packaged are combined, and the subsequent packaging is completed to form the packaging structure shown in fig. 13.

Example 3

Because of the light absorption property of the material, if a photo-lithographically black material is used in combination with the photo-lithography method, the light is easily absorbed by a layer of the material on the surface and cannot penetrate through to the bottom for exposure, thereby generating residue, as in example 2.

To overcome this problem, as shown in fig. 19, a patterned screen 401 may be used to print black light absorbing material to directly form a patterned wall on the inner wall of the cavity.

The aspects, embodiments, features and examples of the present invention should be considered illustrative in all respects and not intended to be limiting, the scope of the invention being defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.

The use of headings and chapters in this application is not meant to limit the invention; each section may apply to any aspect, embodiment, or feature of the present invention.

Throughout this application, where a composition is described as having, containing, or comprising specific components or where a process is described as having, containing, or comprising specific process steps, it is contemplated that the compositions taught by the present invention also consist essentially of, or consist of, the recited components, and that the processes taught by the present invention also consist essentially of, or consist of, the recited process steps.

In this application, where an element or component is referred to as being included in and/or selected from a list of recited elements or components, it is understood that the element or component can be any one of the recited elements or components and can be selected from a group consisting of two or more of the recited elements or components. Moreover, it should be understood that elements and/or features of the compositions, apparatus, or methods described herein may be combined in various ways, whether explicitly described or implicitly described herein, without departing from the spirit and scope of the present teachings.

Unless specifically stated otherwise, use of the terms "comprising", "including", "having" or "having" is generally to be understood as open-ended and not limiting.

The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. Furthermore, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In addition, where the term "about" is used before a quantity, the teachings of the present invention include the particular quantity itself unless specifically stated otherwise.

It should be understood that the order of steps or the order in which particular actions are performed is not critical, so long as the teachings of the present invention remain operable. Further, two or more steps or actions may be performed simultaneously.

It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for purposes of clarity, other elements. However, those skilled in the art will recognize that these and other elements may be desirable. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. It should be understood that the figures are presented for illustrative purposes and not as construction diagrams. The omission of details and modifications or alternative embodiments is within the scope of one skilled in the art.

It is to be understood that in certain aspects of the present invention, a single component may be replaced by multiple components and that multiple components may be replaced by a single component to provide an element or structure or to perform a given function or functions. Such substitutions are considered to be within the scope of the present invention, except where such substitution would not operate to practice a particular embodiment of the invention.

While the invention has been described with reference to illustrative embodiments, it will be understood by those skilled in the art that various other changes, omissions and/or additions may be made and substantial equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims (6)

1. A package structure, comprising:

a chip unit, a first surface of the chip unit including a sensing region;

an upper cover plate covering the first surface of the chip unit;

a support structure located between the upper cover plate and the chip unit, and the sensing region located in a cavity enclosed by the support structure and the first surface of the chip unit,

and the surface of the inner wall of the cavity is covered with a light absorption layer.

2. The package structure of claim 1, wherein the light absorbing layer extends between the support structure and the chip unit.

3. The package structure of claim 2, wherein the light absorbing layer is glued to the first surface of the chip unit.

4. The package structure of claim 1, wherein the light absorbing layer is a black adhesive.

5. The package structure of claim 1, wherein the chip unit further comprises:

the welding pad is positioned outside the sensing area;

a through hole penetrating the chip unit from a second surface of the chip unit opposite to the first surface, the through hole exposing the pad;

an insulating layer covering the second surface of the chip unit and the surface of the side wall of the through hole;

the metal layer is positioned on the surface of the insulating layer and electrically connected with the welding pad;

the solder mask is positioned on the surfaces of the metal layer and the insulating layer and is provided with an opening for exposing a part of the metal layer;

and filling the opening and exposing the external connection bump outside the surface of the solder resist layer.

6. The package structure according to claim 1, wherein the upper cover plate is provided with a predetermined thickness and/or shape and/or a surface thereof is covered with a light shielding layer, so that light reflected from the sidewall of the upper cover plate cannot directly irradiate or is reduced to irradiate the sensing region.

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