CN203881841U

CN203881841U - Over-current detection circuit, load switch and portable device

Info

Publication number: CN203881841U
Application number: CN201420093698.1U
Authority: CN
Inventors: 李茂旭; 郑石德
Original assignee: Fairchild Semiconductor Suzhou Co Ltd
Current assignee: Fairchild Semiconductor Suzhou Co Ltd
Priority date: 2014-02-27
Filing date: 2014-02-27
Publication date: 2014-10-15
Anticipated expiration: 2024-02-27

Abstract

The utility model discloses an over-current detection circuit, a load switch and a portable device, wherein the over-current detection circuit comprises a first over-current detection sub circuit for over-current detection of a switching circuit when the voltage of an output end of the switching circuit is greater than or equal to a set threshold; and a second over-current detection sub circuit for over-current detection of the switching circuit when the voltage of the output end of the switching circuit is less than the set threshold.

Description

Overcurrent detection circuit, load switch, and portable device

Technical Field

The present invention relates to an overcurrent technology, and more particularly to an overcurrent detection circuit, a load switch and a Portable Device.

Background

In recent years, with the development of portable devices, in order to save electric power, in addition to an Integrated Circuit (IC) that applies high efficiency, a plurality of load switches are required for the purpose of supplying power to a load used by a user among the load switches and turning off the power supply to an unused load.

The load switch is a power supply channel device which controls on and off by using logic level between a power supply and a load so as to enable the load to be powered on or powered off. In order to improve the operational reliability of the conventional load switch, functions such as: a Reverse Current Blocking (RCB) function, and accordingly, a load switch having the RCB function may be referred to as an RCB load switch.

In use, a conventional RCB load switch may generate an excessive current flowing through a power N-channel metal oxide semiconductor field effect transistor (NMOS), and therefore, to avoid the excessive current, the conventional RCB load switch generally has an overcurrent protection circuit, thereby protecting the power NMOS and a load.

SUMMERY OF THE UTILITY MODEL

For solving the technical problem that exists now, the embodiment of the utility model provides an overcurrent detection circuit, load switch and portable equipment.

The utility model provides an overcurrent detection circuit, include: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

and a second overcurrent detection sub-circuit which detects overcurrent of the switch circuit when the voltage at the output end of the switch circuit is smaller than a set threshold value.

The utility model also provides a load switch, load switch includes overcurrent detection circuit, overcurrent detection circuit includes: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

and a second overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when the voltage at the output terminal of the switching circuit is smaller than a set threshold value.

The utility model also provides a portable equipment, portable equipment includes: a load switch, the load switch comprising: an overcurrent detection circuit, the overcurrent detection circuit comprising: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

and when the voltage at the output end of the switching circuit is smaller than a set threshold value, performing overcurrent detection on the switching circuit by using a second overcurrent detection sub-circuit.

The embodiment of the utility model provides an overcurrent detection circuit, load switch and portable equipment, when the threshold value that the voltage more than or equal to of switch circuit output set up, it is right by first overcurrent detection sub-circuit switch circuit carries out overcurrent detection, works as when the voltage of switch circuit output is less than the threshold value that sets up, it is right by second overcurrent detection sub-circuit switch circuit carries out overcurrent detection, so, can carry out effective detection to switch circuit from the electricity of going up to the overcurrent in the normal just work engineering of going up.

Drawings

In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

FIG. 1 is a schematic diagram of an embodiment of an over-current protection circuit;

fig. 2 is a schematic structural diagram of a first overcurrent detection circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second overcurrent detection circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a third overcurrent detection circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a fourth over-current detection circuit according to an embodiment of the present invention

Fig. 6 is a schematic diagram of an overcurrent detection circuit according to an embodiment of the present invention;

fig. 7 is a diagram showing simulation results of the overcurrent detection circuit according to the embodiment of the present invention.

Detailed Description

In the following description, a load switch having an RCB function is referred to as an RCB load switch.

In an embodiment, fig. 1 is a schematic diagram of an overcurrent protection circuit of an RCB load switch, as shown in fig. 1, when the voltage of the output terminal VOUT is high, that is, when the voltage of the output terminal VOUT has risen to a certain voltage value after the power NMOS M1 and M2 are turned on, the overcurrent protection circuit shown in fig. 1 can effectively detect the current I1 flowing through M1 and M2, and turn off M1 and M2 when detecting that the current I1 flowing through M1 and M2 is greater than or equal to a set threshold, so as to protect the overcurrent flowing through M1 and M2; however, when the voltage of the output terminal VOUT is low or the output terminal VOUT is Grounded (GND), in other words, when M1 and M2 just start to be turned on and the output terminal VOUT starts to have a voltage output, that is: when the voltage rises from 0V, the current I1 flowing through M1 and M2 cannot be effectively detected by the overcurrent protection circuit shown in fig. 1. This is because: when the charge pump (charge pump) starts to operate, the current output by the charge pump causes M1, M2, and M3 to turn on, and then a large current flows from the input terminal VIN to the output terminal VOUT, at this time, because the voltage of the output terminal VOUT is low or the output terminal VOUT is grounded, the voltage at the point a is equal to the voltage of the output terminal VOUT, that is, the voltage at the point a is close to 0V, and the voltage at the point B is equal to I2R 1, so that the voltage at the point a is not equal to the voltage at the point B, and thus the current mirror ratio error is very large, the current mirror ratio is smaller than the set value K, that is, the current I2 cannot truly reflect the magnitude of the current I1, in this case, when the current I1 is greater than or equal to the set threshold value, since the current I2 cannot truly reflect the magnitude of the current I1, the current I2R 1 is still smaller than the reference voltage Vref1, which makes the comparator COMP1 still output a low voltage signal, thereby, the charge pump continues to operate to make M1 and M2 in a conducting state, which may cause the power NMOS M1 and M2 to be burned out by a large current.

Based on this, in the following various embodiments of the present invention: the overcurrent detection is performed by a first overcurrent detection sub-circuit for the switching circuit when the voltage at the output terminal of the switching circuit is equal to or greater than a set threshold value, and the overcurrent detection is performed by a second overcurrent detection sub-circuit for the switching circuit when the voltage at the output terminal of the switching circuit is less than the set threshold value.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

The embodiment of the utility model provides an overcurrent detection circuit, as shown in FIG. 2, include: a first overcurrent detection sub-circuit 21 and a second overcurrent detection sub-circuit 22; wherein,

the first overcurrent detection sub-circuit 21 performs overcurrent detection on the switch circuit 23 when the voltage at the output terminal of the switch circuit 23 is equal to or higher than a set threshold value, and the second overcurrent detection sub-circuit 22 performs overcurrent detection on the switch circuit 23 when the voltage at the output terminal of the switch circuit 23 is lower than the set threshold value.

Here, in practical application, the over-current detection circuit provided by the embodiment of the present invention is applicable to an application scenario in which the switch circuit 23 is in a conducting state; the switching circuit 23 is in a conducting state, that is: a current flows through the switching circuit 23.

The threshold value may be set according to the needs of the circuit being designed.

The switching circuit 23 may be implemented by a metal oxide semiconductor field effect transistor (MOS), and more specifically, may be implemented by an NMOS or a P-channel metal oxide semiconductor field effect transistor (PMOS); in practical application, the implementation is generally performed by NMOS in consideration of cost.

As shown in fig. 3, the overcurrent detection circuit may further include: an enable circuit 24; when the voltage at the output end of the switch circuit 23 is greater than or equal to the set threshold, the enable circuit 24 inputs an enable signal to the first overcurrent detection sub-circuit 21, and the first overcurrent detection sub-circuit 21 performs overcurrent detection on the switch circuit 23 after receiving the enable signal input by the enable circuit 24; when the voltage at the output terminal of the switching circuit 23 is smaller than the set threshold, the enable circuit 24 inputs an enable signal to the second overcurrent detection sub-circuit 22, and the second overcurrent detection sub-circuit 22 performs overcurrent detection on the switching circuit 23 after receiving the enable signal input by the enable circuit 24.

As shown in fig. 4 and 5, the overcurrent detection circuit may further include: an overcurrent protection circuit 25; when the first overcurrent detecting sub-circuit 21 or the second overcurrent detecting sub-circuit 21 detects that the switch circuit 23 has an overcurrent, the overcurrent protection circuit 25 sends the result that the switch circuit 23 has the overcurrent to the overcurrent protection circuit 23, and after receiving the result that the switch circuit 23 has the overcurrent, which is sent by the first overcurrent detecting sub-circuit 21 or the second overcurrent detecting sub-circuit 21, the overcurrent protection circuit 25 enables the switch circuit 23 to be in a turn-off state, so that the switch circuit 23 can be effectively prevented from being burnt out, and the function of protecting the switch circuit 23 is achieved. Here, the detection of the overcurrent of the switch circuit 23 means that the current flowing through the switch circuit 23 exceeds a set current threshold; the turning off of the switching circuit 23 means: no current flows through the switching circuit 23.

Fig. 6 is a schematic circuit structure diagram of an embodiment of the present invention, and as shown in fig. 6, the switch circuit 23 may include: a first NMOS MN1 and a second NMOS MN 2; the first overcurrent detecting sub-circuit 21 may include: a third NMOS MN3, an operational amplifier OP, a fourth NMOS MN4, a first resistor R1, a third switch SW3, a fourth switch SW4, and a first comparator COMP 1; the second overcurrent detecting sub-circuit 22 may include: reference current source I₀A second resistor R2, a third resistor R3, a second switch SW2 and a second comparator COMP 2; the enabling circuit 24 may include: a first switch SW1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third comparator COMP3 and an inverter INV; the overcurrent protection circuit 25 may include: an OR gate circuit, a logic control circuit and a charge pump; the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are single-pole single-throw switches, and the third switch SW3 and the fourth switch SW4 form a single-pole double-throw switch.

The connection relationship of the components of the overcurrent detection circuit shown in fig. 6 is:

in the switch circuit 23, the gate of the first NMOS MN1 is connected to the charge pump in the overcurrent protection circuit 25, the drain of the first NMOS MN1 is connected to the voltage input node VIN, the source of the first NMOS MN1 is connected to the source of the second NMOS MN2, the inverting input terminal of the operational amplifier OP, and the positive input terminal of the second comparator COMP2 in the second overcurrent detection sub-circuit 22, the gate of the second NMOS MN2 is connected to the charge pump in the overcurrent protection circuit 25, and the drain of the second NMOS MN2 is connected to the voltage output node VOUT, one end of the second resistor R2 in the second overcurrent detection sub-circuit 22, and one end of the fourth resistor in the enable circuit 24;

in the first overcurrent detecting sub-circuit 21, a gate of the third NMOS MN3 is connected to the charge pump in the overcurrent protection circuit 25, a drain of the third NMOS MN3 is connected to the voltage input node VIN, a source of the third NMOS MN3 is connected to the non-inverting input terminal of the operational amplifier OP and the drain of the fourth NMOS MN4, an output terminal of the operational amplifier OP is connected to the gate of the fourth NMOS MN4, a source of the fourth NMOS MN4 is connected to one end of the first resistor R1 and the positive input terminal of the first comparator COMP1, the other end of the first resistor R1 is grounded, a negative input terminal of the first comparator COMP1 is connected to one end of the third switch SW3 and one end of the fourth switch SW4, the other end of the third switch SW3 is connected to a node outputting the first reference voltage, the other end of the fourth switch SW4 is connected to a node outputting the second reference voltage, and an output terminal of the first comparator COMP1 is connected to a first input terminal of an or gate circuit in the overcurrent protection circuit 25;

in the second overcurrent detecting sub-circuit 22, the other end of the second resistor R2 is connected to one end of the third resistor R3 and the first end of the second switch SW2, and the other end of the third resistor R3 is connected to the second end of the second switch SW2 and the reference current source I₀And a negative input terminal of a second comparator COMP2, a reference current source I₀The other end of the first comparator COMP2 is connected to the voltage input node VIN, and the output end of the second comparator COMP2 is connected to the third end of the second switch SW2 and the second input end of the or gate circuit in the overcurrent protection circuit 25;

in the enable circuit 24, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and the first end of the first switch SW1, the other end of the fifth resistor R5 is connected to the second end of the first switch SW1, one end of the sixth resistor R6 and the negative input end of the third comparator COMP3, the other end of the sixth resistor R6 is grounded, the positive input end of the third comparator COMP3 is connected to a node outputting a third reference voltage, the output end of the third comparator COMP3 is connected to the third end of the first switch SW1, the enable input end of the second comparator COMP2 and the input end of the inverter INV, and the output end of the inverter INV is connected to the enable input end of the first comparator COMP 1;

in the overcurrent protection circuit 25, the output terminal of the or gate circuit is connected to the input terminal of the logic control circuit, and the output terminal of the logic control circuit is connected to the enable input terminal of the charge pump.

The operation principle of the overcurrent detection circuit shown in fig. 6 is described in detail below.

For convenience of description, in the following description, the voltage of the voltage output terminal is referred to as V_outThe first reference voltage is referred to as V_ref1The second reference voltage is referred to as V_ref2The third reference voltage is referred to as V_ref3The resistance of the first resistor is referred to as R₁The resistance of the second resistor R2 is referred to as R₂The resistance of the third resistor R3 is referred to as R₃The resistance of the fourth resistor R4 is referred to as R₄The resistance of the fifth resistor R5 is referred to as R₅The resistance of the sixth resistor R6 is referred to as R₆The connection point formed by the first NMOS MN1, the second NMOS MN2 and the operational amplifier OP is called point A, and the corresponding voltage is called V_AThe connection point formed by the third NMOS MN3, the operational amplifier OP, and the fourth NMOS MN4 is referred to as point B, the connection point formed by the fourth NMOS MN4, the first resistor R1, and the first comparator COMP1 is referred to as point C, and the reference current source I is referred to as point C₀The connection point formed by the third resistor R3 and the second comparator COMP2 is called point D, and the corresponding voltage is called V_DA connection point formed by the second comparator COMP2, the third comparator COMP3, and the inverter INV is referred to as SEL, a connection point formed by the inverter INV and the first comparator COMP1 is referred to as SELB, a connection point formed by the first comparator COMP1 and the or gate circuit is referred to as OCP1, and a connection point formed by the second comparator COMP2 and the or gate circuit is referred to as OCP 2.

The enabling circuit 24 operates on the principle of: when in useWhen, the first switch SW1 is turned off, so that the third comparator COMP3 outputs a high voltage signal, and the inverter INV outputs a low voltage signal, that is: the voltage at the point SEL is high, the voltage at the point SELB is zero, and the output of the third comparator COMP3The output high voltage signal enables the second comparator COMP2, so that the second comparator COMP2 works; at this time, the low voltage signal output by the inverter INV does not enable the first comparator COMP1, and therefore, the first comparator COMP1 does not operate, in other words, at this time, the second overcurrent detection sub-circuit 22 operates, and the first overcurrent detection sub-circuit 21 does not operate;

when in useWhen the first switch SW1 is turned on, the third comparator COMP3 outputs a low voltage signal, and the inverter INV outputs a high voltage signal, that is: the voltage at the point SEL is zero, the voltage at the point SELB is a high voltage, and the high voltage signal output by the inverter INV enables the first comparator COMP1, so that the first comparator COMP1 operates; at this time, the low voltage signal output by the third comparator COMP3 does not enable the second comparator COMP2, and therefore, the second comparator COMP2 does not operate, in other words, at this time, the first overcurrent detecting sub-circuit 21 operates, and the second overcurrent detecting sub-circuit 22 does not operate; since the first switch SW1 is turned on at this time, only whenOnly when the first switch SW1 is turned off, the third comparator COMP3 outputs a high voltage signal, and the inverter INV outputs a low voltage signal.

Here, whether the fifth resistor R5 is short-circuited is controlled by turning on and off the first switch SW1, and the detection point of the voltage output node VOUT is changed, in other words, the first switch SW1, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 function as a hysteresis function. The high voltage signal is: show thatThe output signal of the third comparator COMP 3; the low voltage signal is: show thatThe output signal of the third comparator COMP 3; for example, if the output signal includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

The operating principle of the first overcurrent detecting sub-circuit 21 is: when I is₁<V_ref1/R₁K, the third switch SW3 is turned on, and the fourth switch SW4 is turned off, so that the first comparator COMP1 outputs a low voltage signal, that is: the voltage at point OCP1 is zero when I₁Is gradually increased and I₁≥V_ref2/R₁K, the fourth switch SW4 is turned on, the third switch SW3 is turned off, and the first comparator COMP1 outputs a high voltage signal, that is: the voltage at the point OCP1 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the first overcurrent detection sub-circuit 21 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when I₁Is gradually reduced, and I₁≤V_ref1/R₁When K is reached, the third switch SW3 is turned on again, and the fourth switch SW4 is turned off again, so that the first comparator COMP1 outputs a low voltage signal again, thereby effectively realizing hysteresis and ensuring the detection accuracy; wherein, I₁Representing the current flowing through the first NMOS MN1 and the second NMOS MN2, K representing the current mirror ratio, V_ref1<V_ref2. Here, the high voltage signal means: shows I₁≥V_ref2/R₁K, the output signal of the first comparator COMP1, the low voltage signal is: shows I₁<V_ref2/R₁K, the output signal of the first comparator; for example, assuming that the signal output by the first comparator COMP1 includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

The operating principle of the second overcurrent detecting sub-circuit 22 is: when V is_A<V_DAt this time, the second switch SW2 is turned off due to V_A＝V_out+I₁·Rdson_MN2，V_D＝V_out+I₃·(R₂+R₃) So when I₁·Rdson_MN2<I₃·(R₂+R₃) At this time, the second comparator COMP2 outputs a low voltage signal, namely: the voltage at point OCP2 is zero; when V is_A≥V_DWhen the second switch SW2 is turned on, i.e. when I is₁·Rdson_MN2≥I₃·(R₂+R₃) When the third resistor R3 is short-circuited, the second comparator COMP2 outputs a high voltage signal, that is: the voltage at the point OCP2 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the second overcurrent detection sub-circuit 22 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when V_DIs reduced, and I₁·Rdson_MN2≤I₃·R₂In the meantime, the second switch SW2 is turned off again, and the voltage at the point OCP2 is changed from the high voltage to the low voltage again, so that hysteresis can be effectively realized, and the accuracy of detection is ensured. Wherein, I₁Representing the current, Rdson, flowing through the first NMOS MN1 and the second NMOS MN2_MN2Represents the on-resistance, I, of the second NMOS MN2₃Represents a reference current source I₀The output current.

Here, the result is that during the turn-on of the second NMOS MN2, Rdson_MN2Is a resistance which gradually changes from large to small, and simultaneously, because of I₁The voltage drop across the source and drain of the second NMOS MN2 is a variable value, and gradually increases with the increase of the gate voltage of the second NMOS MN2, so that in practical application, the maximum value V in the normal power-on process of the voltage output contact needs to be obtained through simulation experiments_maxAnd let I₃·(R₂+R₃) Greater than V_maxTherefore, the second comparator COMP2 can be ensured not to output a high voltage signal by mistake during the normal power-on process of the voltage output contact, in other words, the second over-current detection sub-circuit 22 can be ensured not to generate a false detection during the normal power-on process of the voltage output contact; at the same time, I₃·(R₂+R₃) Cannot be too large, so that the first overcurrent detecting sub-circuit 21 and the second overcurrent detecting sub-circuit are ensuredThe overcurrent detection sub-circuit 22 operates in order to actually perform the overcurrent protection function.

Wherein, the high voltage signal is: shows V_A≥V_DThe output signal of the second comparator COMP 2; the low voltage signal is: shows V_A<V_DThe output signal of the second comparator COMP 2; for example, assuming that the signal output by the second comparator COMP2 includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

The operating principle of the overcurrent protection circuit 25 is: when the or gate circuit receives the high voltage signal output by the first comparator COMP1 or the high voltage signal output by the second comparator COMP2, the or gate circuit inputs the high voltage signal to the logic control circuit, and when the logic control circuit receives the high voltage signal, the logic control circuit stops outputting the enable signal to the charge pump, so as to turn off the charge pump, and after the charge pump is turned off, the first NMOS MN1 and the second NMOS MN2 are turned off, so as to perform an overcurrent protection function.

It should be noted that: when the overcurrent detecting circuit shown in fig. 6 is employed, if the first overcurrent detecting sub-circuit 21 is used alone, that is: only when the voltage value of VOUT is lower or close to GND, V is adopted_AIs equal to V_outAnd the voltage at point B is equal to I₂×R₁Therefore, the voltage at point A is not equal to the voltage at point B, resulting in a very large error in the current mirror ratio K, therefore, when I is equal to₁At maximum time I₂×R₁Will still be less than V_ref2Causing the first NMOS MN1 and the second NMOS MN2 to be burned out by a large current; and the second over-current detection sub-circuit 22 can solve V after being operated_outAnd at low, the current flowing through the switch circuit 23 is not detected accurately. However, in practical use, it is necessary to pay attention to the threshold value of the path selection voltage at which the first overcurrent detecting sub-circuit 21 and the second overcurrent detecting sub-circuit 22 operate, and if the threshold value is set to be too small, the threshold value is set so that the threshold value V is appropriate_outAt a lower but still higher threshold value, this will occur due to the overcurrent detection of the switching circuit 23 by the first overcurrent detection sub-circuit 21The current mirror image is not accurate, and the switch circuit 23 is easy to burn; if the threshold is set too large, when V_outHigher but still lower than the set threshold, V will be caused by the second over-current detection sub-circuit 22 performing over-current detection on the switch circuit 23_DIs close to the voltage of the voltage input node VIN, resulting in I₃Become smaller and result in I₃·(R₂+R₃) The value of (a) becomes small; thus, it is easy to trigger the overcurrent protection by mistake, that is, V appears_A>V_DTherefore, the second comparator COMP2 outputs a high voltage signal to trigger the overcurrent protection by mistake, so that the first NMOS MN1 and the second NMOS MN2 are turned off, and the corresponding chips cannot work normally. Wherein, I₂Representing the current flowing through the fourth NMOS MN 4.

Fig. 7 is a diagram of simulation results of each sub-circuit obtained by adopting the technical solution of the embodiment of the present invention. As can be seen in fig. 7:

in state one, namely: in the power-up stage of the voltage output node VOUT, in which the voltage output node VOUT is short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second over-current detection sub-circuit 22 is activated and the first over-current detection sub-circuit 21 is deactivated, in other words, the output of the first comparator COMP1 is a low voltage signal, that is: the voltage at the OCP1 is zero, and in this state, the voltage output by the charge pump gradually increases, and at this time, the current I flowing through the first NMOS MN1 and the second NMOS MN2 is₁Less than or equal to the set value, the output of the second comparator COMP2 is a low voltage signal, that is: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero;

in the second state, in which the voltage output node VOUT is still short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second overcurrent detection sub-circuit 22 is activated and the first overcurrent detection sub-circuit 21 is still deactivated, in other words, the output of the first comparator COMP1 is a low voltage signal, namely: the voltage at point OCP1 is zero, and in this state, the charge pump output is zeroThe output voltage is still gradually increased, and as the output voltage of the charge pump is further increased, the current I flowing through the first NMOS MN1 and the second NMOS MN2₁Greater than the set value, the output of the second comparator COMP2 is a high voltage signal, i.e.: the voltage at the point OCP2 is high, so the voltage at the output OCP of the or gate is also high;

in state three, where the voltage output node VOUT has normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at the OCP2 is zero, and in this state, the voltage output by the charge pump is still gradually increased when the current I flows through the first NMOS MN1 and the second NMOS MN2₁Is less than or equal to a set value V_ref2/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero; when the current flowing through the first NMOS MN1 and the second NMOS MN2 is larger than the set value V_ref2/R₁K, the output of the first comparator COMP1 is a high voltage signal, i.e.: the voltage at the point OCP1 is high, so the voltage at the output OCP of the or gate is also high;

in state four, in which the voltage output node VOUT is still normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at OCP2 is zero, and in this state, the charge pump is turned off when the current I flows through the first NMOS MN1 and the second NMOS MN2₁Start to fall and flow asThe current through the first NMOS MN1 and the second NMOS MN2 is reduced to be less than or equal to V_ref1/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP1 is zero, and thus the voltage at the output OCP of the or gate is also zero.

It can be seen from the above description that, by adopting the technical solution of the embodiment of the present invention, the overcurrent in the normal and working engineering of the switch circuit from the start of power-on to power-on can be effectively detected.

Based on above-mentioned overcurrent detection circuit, the embodiment of the utility model provides an overcurrent detection method is still provided, include: when the voltage at the output end of the switch circuit is larger than or equal to a set threshold value, the first overcurrent detection sub-circuit of the overcurrent detection circuit detects the overcurrent of the switch circuit, and when the voltage at the output end of the switch circuit is smaller than the set threshold value, the second overcurrent detection sub-circuit of the overcurrent detection circuit detects the overcurrent of the switch circuit.

Here, the threshold value may be set according to the need of a designed circuit.

The method may further comprise: when the voltage at the output end of the switch circuit is greater than or equal to a set threshold value, outputting an enable signal to the first overcurrent detection sub-circuit, and correspondingly, after receiving the enable signal, performing overcurrent detection on the switch circuit by the second overcurrent detection sub-circuit;

when the voltage at the output end of the switch circuit is smaller than a set threshold value, the second overcurrent detection sub-circuit outputs an enable signal, and accordingly, after receiving the enable signal, the second overcurrent detection sub-circuit performs overcurrent detection on the switch circuit.

The method may further comprise: when the overcurrent of the switch circuit is detected, the switch circuit is in a turn-off state, so that the switch circuit can be effectively prevented from being burnt out, and the function of protecting the switch circuit is achieved. Here, the detection of the overcurrent in the switching circuit means: the current flowing through the switching circuit exceeds a set current threshold; the making the switch circuit in the off state means: no current flows through the switching circuit.

Based on above-mentioned overcurrent detection circuit, the embodiment of the utility model provides a load switch is still provided, load switch includes overcurrent detection circuit, as shown in fig. 2, this overcurrent detection circuit includes: a first overcurrent detection sub-circuit 21 and a second overcurrent detection sub-circuit 22; wherein,

The switch circuit 23 may be implemented by MOS, more specifically, NMOS or PMOS; in practical application, the implementation is generally performed by NMOS in consideration of cost.

For convenience of description, in the following description, the voltage of the voltage output terminal is referred to as V_outThe first reference voltage is referred to as V_ref1The second reference voltage is referred to as V_ref2The third reference voltage is referred to as V_ref3The resistance of the first resistor is referred to as R₁The resistance of the second resistor R2 is referred to as R₂The resistance of the third resistor R3 is referred to as R₃The resistance of the fourth resistor R4 is referred to as R₄The resistance of the fifth resistor R5 is referred to as R₅The resistance of the sixth resistor R6 is referred to as R₆The connection point formed by the first NMOS MN1, the second NMOS MN2 and the operational amplifier OP is called point A, and the corresponding voltage is called V_AThe connection point formed by the third NMOS MN3, the operational amplifier OP, and the fourth NMOS MN4 is referred to as point B, the connection point formed by the fourth NMOS MN4, the first resistor R1, and the first comparator COMP1 is referred to as point C, and the reference current source I is referred to as point C₀The connection point formed by the third resistor R3 and the second comparator COMP2 is called point D, and the corresponding voltage is called V_DThe connection point formed by the second comparator COMP2, the third comparator COMP3 and the inverter INV is referred to as SEL, and the inverter INV and the first comparator INV are referred toThe connection point formed by the COMP1 is called SELB, the connection point formed by the first comparator COMP1 and the or gate is called OCP1, and the connection point formed by the second comparator COMP2 and the or gate is called OCP 2.

The enabling circuit 24 operates on the principle of: when in useWhen, the first switch SW1 is turned off, so that the third comparator COMP3 outputs a high voltage signal, and the inverter INV outputs a low voltage signal, that is: the voltage of the point SEL is high, the voltage of the point SELB is zero, and a high-voltage signal output by the third comparator COMP3 enables the second comparator COMP2, so that the second comparator COMP2 works; at this time, the low voltage signal output by the inverter INV does not enable the first comparator COMP1, and therefore, the first comparator COMP1 does not operate, in other words, at this time, the second overcurrent detection sub-circuit 22 operates, and the first overcurrent detection sub-circuit 21 does not operate;

when in useWhen the first switch SW1 is turned on, the third comparator COMP3 outputs a low voltage signal, and the inverter INV outputs a high voltage signal, that is: the voltage at the point SEL is zero, the voltage at the point SELB is a high voltage, and the high voltage signal output by the inverter INV enables the first comparator COMP1, so that the first comparator COMP1 operates; at this time, the low voltage signal output by the third comparator COMP3 does not enable the second comparator COMP2, and therefore, the second comparator COMP2 does not operate, in other words, at this time, the first overcurrent detecting sub-circuit 21 operates, and the second overcurrent detecting sub-circuit 22 does not operate; since the first switch SW1 is turned on at this time, all only ifOnly when the first switch SW1 is turned off, the third comparator COMP3 outputs a high voltage signal, and the inverter INV outputs a low voltage signal.

The operating principle of the first overcurrent detecting sub-circuit 21 is: when I is₁<V_ref1/R₁K, the third switch SW3 is turned on, and the fourth switch SW4 is turned off, so that the first comparator COMP1 outputs a low voltage signal, that is: the voltage at point OCP1 is zero when I₁Is gradually increased and I₁≥V_ref2/R₁K, the fourth switch SW4 is turned on, the third switch SW3 is turned off, and the first comparator COMP1 outputs a high voltage signal, that is: the voltage at the point OCP1 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the first overcurrent detection sub-circuit 21 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when I₁Is gradually reduced, and I₁≤V_ref1/R₁When K is reached, the third switch SW3 is turned on again, and the fourth switch SW4 is turned off again, so that the first comparator COMP1 outputs a low voltage signal again, thereby effectively realizing hysteresis and ensuring the detection accuracy; wherein, I₁Representing the current flowing through the first NMOS MN1 and the second NMOS MN2, K representing the current mirror ratio, V_ref1<V_ref2. Here, the high voltage signal means: shows I₁≥V_ref2/R₁When K isThe output signal of the first comparator COMP1, the low voltage signal is: shows I₁<V_ref2/R₁K, the output signal of the first comparator COMP 1; for example, assuming that the signal output by the first comparator COMP1 includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

The operating principle of the second overcurrent detecting sub-circuit 22 is: when V is_A<V_DAt this time, the second switch SW2 is turned off due to V_A＝V_out+I₁·Rdson_MN2，V_D＝V_out+I₃·(R₂+R₃) So when I₁·Rdson_MN2<I₃·(R₂+R₃) When the second comparator COMP2 outputs a high-low voltage signal, namely: the voltage at point OCP2 is zero; when V is_A≥V_DWhen the second switch SW2 is turned on, i.e. when I is₁·Rdson_MN2≥I₃·(R₂+R₃) When the third resistor R3 is short-circuited, the second comparator COMP2 outputs a high voltage signal, that is: the voltage at the point OCP2 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the second overcurrent detection sub-circuit 22 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when V_DIs reduced, and I₁·Rdson_MN2≤I₃·R₂In the meantime, the second switch SW2 is turned off again, and the voltage at the point OCP2 is changed from the high voltage to the low voltage again, so that hysteresis can be effectively realized, and the accuracy of detection is ensured. Wherein, I₁Representing the current, Rdson, flowing through the first NMOS MN1 and the second NMOS MN2_MN2Represents the on-resistance, I, of the second NMOS MN2₃Represents a reference current source I₀The output current.

Here, the result is that during the turn-on of the second NMOS MN2, Rdson_MN2Is a resistance which gradually changes from large to small, and simultaneously, because of I₁Is gradually changed from small to big, so the voltage drop between the source and the drain of the second NMOS MN2 is a variable value with the voltage of the second NMOS MN2The increase of the gate voltage is gradually increased, so that in practical application, the maximum value V in the process of normally electrifying the voltage output contact needs to be obtained through simulation experiments_maxAnd let I₃·(R₂+R₃) Greater than V_maxTherefore, the second comparator COMP2 can be ensured not to output a high voltage signal by mistake during the normal power-on process of the voltage output contact, in other words, the second over-current detection sub-circuit 22 can be ensured not to generate a false detection during the normal power-on process of the voltage output contact; at the same time, I₃·(R₂+R₃) It cannot be too large, so that the orderly operation of the first overcurrent detecting sub-circuit 21 and the second overcurrent detecting sub-circuit 22 can be ensured, and the overcurrent protection function can be really realized.

It should be noted that: when the overcurrent detecting circuit shown in fig. 6 is employed, if the first overcurrent detecting sub-circuit 21 is used alone, that is: only when the voltage value of VOUT is lower or close to GND, V is adopted_AIs equal to V_outAnd the voltage at point B is equal to I₂×R₁Therefore, the voltage at point A is not equal to the voltage at point B, resulting in a very large error in the current mirror ratio K, therefore, when I is equal to₁At maximum time I₂×R₁Will still be less than V_ref2Causing the first NMOS MN1 and the second NMOS MN2 to be burned out by a large current; and the second over-current detection sub-circuit 22 can solve V after being operated_outAnd at low, the current flowing through the switch circuit 23 is not detected accurately. However, in practical use, it is necessary to pay attention to the threshold value of the path selection voltage at which the first overcurrent detecting sub-circuit 21 and the second overcurrent detecting sub-circuit 22 operate, and if the threshold value is set to be too small, the threshold value is set so that the threshold value V is appropriate_outWhen the current is lower but still greater than the set threshold, since the first overcurrent detection sub-circuit 21 performs overcurrent detection on the switch circuit 23, current mirror image is inaccurate, and the switch circuit 23 is easily burnt; if the threshold is set too large, when V_outHigher but still lower than the set threshold, V will be caused by the second over-current detection sub-circuit 22 performing over-current detection on the switch circuit 23_DIs close to the voltage of the voltage input node VIN, resulting in I₃Become smaller and result in I₃·(R₂+R₃) The value of (a) becomes small; thus, it is easy to trigger the overcurrent protection by mistake, that is, V appears_A>V_DTherefore, the second comparator COMP2 outputs a high voltage signal to trigger the overcurrent protection by mistake, so that the first NMOS MN1 and the second NMOS MN2 are turned off, and the corresponding chips cannot work normally. Wherein, I₂Representing the current flowing through the fourth NMOS MN 4.

In practical application, the load switch may be an RCB load switch.

in state one, namely: in the power-up stage of the voltage output node VOUT, in which the voltage output node VOUT is short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second over-current detection sub-circuit 22 is activated and the first over-current detection sub-circuit 21 is deactivated, in other words, the output of the first comparator COMP1 is a low voltage signalThe signals, namely: the voltage at the OCP1 is zero, and in this state, the voltage output by the charge pump gradually increases, and at this time, the current I flowing through the first NMOS MN1 and the second NMOS MN2 is₁Less than or equal to the set value, the output of the second comparator COMP2 is a low voltage signal, that is: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero;

in the second state, in which the voltage output node VOUT is still short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second overcurrent detection sub-circuit 22 is activated and the first overcurrent detection sub-circuit 21 is still deactivated, in other words, the output of the first comparator COMP1 is a low voltage signal, namely: the voltage at the OCP1 is zero, in this state, the voltage output by the charge pump is still gradually increased, and as the output voltage of the charge pump is further increased, the current I flowing through the first NMOS MN1 and the second NMOS MN2 is increased₁Greater than the set value, the output of the second comparator COMP2 is a high voltage signal, i.e.: the voltage at the point OCP2 is high, so the voltage at the output OCP of the or gate is also high;

in state three, where the voltage output node VOUT has normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at the OCP2 is zero, and in this state, the voltage output by the charge pump is still gradually increased, and when the current flowing through the first NMOS MN1 and the second NMOS MN2 is less than or equal to the set value V_ref2/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero; when the current I flows through the first NMOS MN1 and the second NMOS MN2₁Greater than a set value V_ref2/R₁K, the output of the first comparator COMP1 is a high voltage signal, i.e.: electricity at point OCP1The voltage is high voltage, so the voltage of the output end OCP of the OR gate circuit is also high voltage;

in state four, in which the voltage output node VOUT is still normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at the point OCP2 is zero, in which state the charge pump is turned off when the current through the first NMOS MN1 and the second NMOS MN2 begins to decrease and when the current I through the first NMOS MN1 and the second NMOS MN2 begins to decrease₁Down to less than or equal to V_ref1/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP1 is zero, and thus the voltage at the output OCP of the or gate is also zero.

Based on above-mentioned load switch, the embodiment of the utility model provides a portable equipment is still provided, portable equipment includes load switch, load switch includes: an overcurrent protection circuit, as shown in fig. 2, includes: a first overcurrent detection sub-circuit 21 and a second overcurrent detection sub-circuit 22; wherein,

FIG. 6 shows the present inventionReferring to fig. 6, the switch circuit 23 may include: a first NMOS MN1 and a second NMOS MN 2; the first overcurrent detecting sub-circuit 21 may include: a third NMOS MN3, an operational amplifier OP, a fourth NMOS MN4, a first resistor R1, a third switch SW3, a fourth switch SW4, and a first comparator COMP 1; the second overcurrent detecting sub-circuit 22 may include: reference current source I₀A second resistor R2, a third resistor R3, a second switch SW2 and a second comparator COMP 2; the enabling circuit 24 may include: a first switch SW1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third comparator COMP3 and an inverter INV; the overcurrent protection circuit 25 may include: an OR gate circuit, a logic control circuit and a charge pump; the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are single-pole single-throw switches, and the third switch SW3 and the fourth switch SW4 form a single-pole double-throw switch.

For convenience of description, in the following description, the voltage is outputtedThe voltage at the contact is called V_outThe first reference voltage is referred to as V_ref1The second reference voltage is referred to as V_ref2The third reference voltage is referred to as V_ref3The resistance of the first resistor is referred to as R₁The resistance of the second resistor R2 is referred to as R₂The resistance of the third resistor R3 is referred to as R₃The resistance of the fourth resistor R4 is referred to as R₄The resistance of the fifth resistor R5 is referred to as R₅The resistance of the sixth resistor R6 is referred to as R₆The connection point formed by the first NMOS MN1, the second NMOS MN2 and the operational amplifier OP is called point A, and the corresponding voltage is called V_AThe connection point formed by the third NMOS MN3, the operational amplifier OP, and the fourth NMOS MN4 is referred to as point B, the connection point formed by the fourth NMOS MN4, the first resistor R1, and the first comparator COMP1 is referred to as point C, and the reference current source I is referred to as point C₀The connection point formed by the third resistor R3 and the second comparator COMP2 is called point D, and the corresponding voltage is called V_DA connection point formed by the second comparator COMP2, the third comparator COMP3, and the inverter INV is referred to as SEL, a connection point formed by the inverter INV and the first comparator COMP1 is referred to as SELB, a connection point formed by the first comparator COMP1 and the or gate circuit is referred to as OCP1, and a connection point formed by the second comparator COMP2 and the or gate circuit is referred to as OCP 2.

The operating principle of the first overcurrent detecting sub-circuit 21 is: when I is₁<V_ref1/R₁K, the third switch SW3 is turned onThe fourth switch SW4 is turned off, so that the first comparator COMP1 outputs a low voltage signal, that is: the voltage at point OCP1 is zero when I₁Is gradually increased and I₁>V_ref2/R₁K, the fourth switch SW4 is turned on, the third switch SW3 is turned off, and the first comparator COMP1 outputs a high voltage signal, that is: the voltage at the point OCP1 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the first overcurrent detection sub-circuit 21 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when I₁Is gradually reduced, and I₁≤V_ref1/R₁When K is reached, the third switch SW3 is turned on again, and the fourth switch SW4 is turned off again, so that the first comparator COMP1 outputs a low voltage signal again, thereby effectively realizing hysteresis and ensuring the detection accuracy; wherein, I₁Representing the current flowing through the first NMOS MN1 and the second NMOS MN2, K representing the current mirror ratio, V_ref1<V_ref2. Here, the high voltage signal means: shows I₁≥V_ref2/R₁K, the output signal of the first comparator COMP1, the low voltage signal is: shows I₁<V_ref2/R₁K, the output signal of the first comparator COMP 1; for example, assuming that the signal output by the first comparator COMP1 includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

The operating principle of the second overcurrent detecting sub-circuit 22 is: when V is_A<V_DAt this time, the second switch SW2 is turned off due to V_A＝V_out+I₁·Rdson_MN2，V_D＝V_out+I₃·(R₂+R₃) So when I₁·Rdson_MN2<I₃·(R₂+R₃) When the second comparator COMP2 outputs a high-low voltage signal, namely: the voltage at point OCP2 is zero; when V is_A≥V_DWhen the second switch SW2 is turned on, i.e. when I is₁·Rdson_MN2>I₃·(R₂+R₃) When the third resistor R3 is short-circuited, the second comparator COMP2 outputs a high voltage signal, namely: the voltage at the point OCP2 is high, which indicates that the current flowing through the first NMOS MN1 and the second NMOS MN2 is too large, and an overcurrent occurs, in other words, the second overcurrent detection sub-circuit 22 detects the overcurrent of the first NMOS MN1 and the second NMOS MN 2; only when V_DIs reduced, and I₁·Rdson_MN2≤I₃·R₂In the meantime, the second switch SW2 is turned off again, and the voltage at the point OCP2 is changed from the high voltage to the low voltage again, so that hysteresis can be effectively realized, and the accuracy of detection is ensured. Wherein, I₁Representing the current, Rdson, flowing through the first NMOS MN1 and the second NMOS MN2_MN2Represents the on-resistance, I, of the second NMOS MN2₃Represents a reference current source I₀The output current.

Here, the result is that during the turn-on of the second NMOS MN2, Rdson_MN2Is a resistance which gradually changes from large to small, and simultaneously, because of I₁The voltage drop across the source and drain of the second NMOS MN2 is a variable value, and gradually increases with the increase of the gate voltage of the second NMOS MN2, so that in practical application, the maximum value V in the normal power-on process of the voltage output contact needs to be obtained through simulation experiments_maxAnd let I₃·(R₂+R₃) Greater than V_maxTherefore, the second comparator COMP2 can be ensured not to output a high voltage signal by mistake during the normal power-on process of the voltage output contact, in other words, the second over-current detection sub-circuit 22 can be ensured not to generate a false detection during the normal power-on process of the voltage output contact; at the same time, I₃·(R₂+R₃) It cannot be too large, so that the orderly operation of the first overcurrent detecting sub-circuit 21 and the second overcurrent detecting sub-circuit 22 can be ensured, and the overcurrent protection function can be really realized.

Wherein, the high voltage signal is: shows V_A≥V_DThe output signal of the second comparator COMP 2; the low voltage signal is: shows V_A<V_DThe output signal of the second comparator COMP 2; lifting deviceFor example, assuming that the signal output by the second comparator COMP2 includes two signals, i.e., 0 and 1, 1 is a high voltage signal and 0 is a low voltage signal.

In practical application, the load switch may be an RCB load switch; the portable device further includes: a shell, a CPU and the like.

in state one, namely: in the power-up stage of the voltage output node VOUT, in which the voltage output node VOUT is short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second overcurrent detection sub-circuit 22 is activated and the first overcurrent detection sub-circuit 21 is deactivated, in other words, the output of the first comparator COMP1 is a low voltage signal, that is: the voltage at the OCP1 is zero, and in this state, the voltage output by the charge pump gradually increases, and at this time, the current I flowing through the first NMOS MN1 and the second NMOS MN2 is₁Less than or equal to the set value, the output of the second comparator COMP2 is a low voltage signal, that is: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero;

in the second state, in which the voltage output node VOUT is still short-circuited to ground, the third comparator COMP3 outputs a high voltage signal, so the second overcurrent detection sub-circuit 22 is activated and the first overcurrent detection sub-circuit 21 is still deactivated, in other words, the output of the first comparator COMP1 is a low voltage signal, namely: the voltage at the OCP1 is zero, in this state, the voltage output by the charge pump is still gradually increased, and as the output voltage of the charge pump is further increased, the current I flowing through the first NMOS MN1 and the second NMOS MN2 is increased₁Greater than the set value, the output of the second comparator COMP2 is thereforeHigh voltage signals, namely: the voltage at the point OCP2 is high, so the voltage at the output OCP of the or gate is also high;

in state three, where the voltage output node VOUT has normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at the OCP2 is zero, and in this state, the voltage output by the charge pump is still gradually increased when the current I flows through the first NMOS MN1 and the second NMOS MN2₁Is less than or equal to a set value V_ref2/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP2 is zero, so the voltage at the output OCP of the or gate is also zero; when the current I flows through the first NMOS MN1 and the second NMOS MN2₁Greater than a set value V_ref2/R₁K, the output of the first comparator COMP1 is a high voltage signal, i.e.: the voltage at the point OCP1 is high, so the voltage at the output OCP of the or gate is also high;

in state four, in which the voltage output node VOUT is still normally powered up, at this time,therefore, the third comparator COMP3 outputs a low voltage signal, the first overcurrent detection sub-circuit 21 is active, and the second overcurrent detection sub-circuit 22 is inactive, in other words, the output of the second comparator COMP2 is a low voltage signal, namely: the voltage at the point OCP2 is zero, in which state the charge pump is turned off when the current through the first NMOS MN1 and the second NMOS MN2 begins to decrease and when the current I through the first NMOS MN1 and the second NMOS MN2 begins to decrease₁Down to less than or equal to V_ref1/R₁K, the output of the first comparator COMP1 is a low voltage signal, i.e.: the voltage at point OCP1 is zero becauseThe voltage at the output OCP of this or-gate is also zero.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. An overcurrent detection circuit, comprising: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

2. The circuit of claim 1, wherein the switching circuit is implemented by a metal oxide semiconductor field effect transistor (MOS).

3. The circuit of claim 1, wherein the overcurrent detection circuit further comprises: when the voltage of the output end of the switch circuit is larger than or equal to a set threshold value, inputting an enabling signal to the first overcurrent detection sub-circuit; an enable circuit that inputs an enable signal to the second overcurrent detection sub-circuit when the voltage at the output terminal of the switching circuit is smaller than a set threshold value;

accordingly, the first overcurrent detection sub-circuit is a first overcurrent detection sub-circuit which performs overcurrent detection on the switch circuit after receiving the enable signal input by the enable circuit;

the second overcurrent detection sub-circuit is used for detecting the overcurrent of the switch circuit after receiving the enable signal input by the enable circuit.

4. The circuit of claim 3, wherein the overcurrent detection circuit further comprises: an overcurrent protection circuit for turning off the switching circuit after receiving an overcurrent result of the switching circuit from the first overcurrent detection sub-circuit or the second overcurrent detection sub-circuit;

accordingly, the first overcurrent detection sub-circuit is a first overcurrent detection sub-circuit which, when detecting that the switch circuit has an overcurrent, transmits a result that the switch circuit has the overcurrent to the overcurrent protection circuit;

the second overcurrent detection sub-circuit is a second overcurrent detection sub-circuit that, when detecting that the switching circuit has an overcurrent, sends a result that the switching circuit has an overcurrent to the overcurrent protection circuit.

5. The circuit of claim 4, wherein the switching circuit comprises: a first NMOS and a second NMOS;

the first overcurrent detection sub-circuit includes: the third NMOS, the operational amplifier, the fourth NMOS, the first resistor, the third switch, the fourth switch and the first comparator;

the second overcurrent detection sub-circuit includes: the reference current source, the second resistor, the third resistor, the second switch and the second comparator;

the enabling circuit includes: the circuit comprises a first switch, a fourth resistor, a fifth resistor, a sixth resistor, a third comparator and an inverter;

the overcurrent protection circuit includes: an OR gate circuit, a logic control circuit and a charge pump.

6. The circuit of claim 5,

in the switch circuit, a gate of a first NMOS is connected to the charge pump in the overcurrent protection circuit, a drain of the first NMOS is connected to the voltage input node, a source of the first NMOS is connected to a source of a second NMOS, an inverting input terminal of an operational amplifier, and a positive input terminal of a second comparator in the second overcurrent detection sub-circuit, a gate of the second NMOS is connected to the charge pump in the overcurrent protection circuit, and a drain of the second NMOS is connected to the voltage output node, one end of a second resistor in the second overcurrent detection sub-circuit, and one end of a fourth resistor in the enable circuit;

in the first overcurrent detection sub-circuit, the gate of a third NMOS is connected to the charge pump in the overcurrent protection circuit, the drain of the third NMOS is connected to the voltage input node, the source of the third NMOS is connected to the non-inverting input terminal of the operational amplifier and the drain of a fourth NMOS, the output terminal of the operational amplifier is connected to the gate of the fourth NMOS, the source of the fourth NMOS is connected to one end of a first resistor and the positive input terminal of a first comparator, the other end of the first resistor is grounded, the negative input terminal of the first comparator is connected to one end of a third switch and one end of a fourth switch, the other end of the third switch is connected to a node that outputs a first reference voltage, the other end of the fourth switch is connected to a node that outputs a second reference voltage, and the output terminal of the first comparator is connected to the first input terminal of the or gate circuit in the overcurrent protection circuit;

in the second overcurrent detection sub-circuit, the other end of the second resistor is connected with one end of a third resistor and a first end of a second switch, the other end of the third resistor is connected with a second end of the second switch, one end of a reference current source and a negative electrode input end of a second comparator, the other end of the reference current source is connected with a voltage input node, and the output end of the second comparator is connected with a third end of the second switch and a second input end of an OR gate circuit in the overcurrent protection circuit;

in the enabling circuit, the other end of the fourth resistor is connected with one end of a fifth resistor and the first end of the first switch, the other end of the fifth resistor is connected with the second end of the first switch, one end of a sixth resistor and the negative electrode input end of a third comparator, the other end of the sixth resistor is grounded, the positive electrode input end of the third comparator is connected with a node outputting a third reference voltage, the output end of the third comparator is connected with the third end of the first switch, the enabling input end of the second comparator and the input end of an inverter, and the output end of the inverter is connected with the enabling input end of the first comparator;

in the overcurrent protection circuit, the output end of the OR gate circuit is connected with the input end of the logic control circuit, and the output end of the logic control circuit is connected with the enabling input end of the charge pump.

7. A load switch comprising an overcurrent detection circuit, the overcurrent detection circuit comprising: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

8. The load switch of claim 7, wherein the switching circuit is implemented by MOS.

9. The load switch of claim 7, wherein the over-current detection circuit further comprises: when the voltage of the output end of the switch circuit is larger than or equal to a set threshold value, inputting an enabling signal to the first overcurrent detection sub-circuit; an enable circuit that inputs an enable signal to the second overcurrent detection sub-circuit when the voltage at the output terminal of the switching circuit is smaller than a set threshold value;

10. The load switch of claim 9, wherein the over-current detection circuit further comprises: an overcurrent protection circuit for turning off the switching circuit after receiving an overcurrent result of the switching circuit from the first overcurrent detection sub-circuit or the second overcurrent detection sub-circuit;

11. The load switch of claim 10, wherein the switching circuit comprises: a first NMOS and a second NMOS;

12. The load switch of claim 11,

13. A portable device, the portable device comprising: a load switch, the load switch comprising: an overcurrent detection circuit, characterized in that the overcurrent detection circuit comprises: a first overcurrent detection sub-circuit that performs overcurrent detection on the switching circuit when a voltage at an output terminal of the switching circuit is equal to or higher than a set threshold value; and

14. The portable device of claim 13, wherein the switching circuit is implemented by MOS.

15. The portable device of claim 13, wherein the overcurrent detection circuit further comprises: when the voltage of the output end of the switch circuit is larger than or equal to a set threshold value, inputting an enabling signal to the first overcurrent detection sub-circuit; an enable circuit that inputs an enable signal to the second overcurrent detection sub-circuit when the voltage at the output terminal of the switching circuit is smaller than a set threshold value;

16. The portable device of claim 15, wherein the overcurrent detection circuit further comprises: an overcurrent protection circuit for turning off the switching circuit after receiving an overcurrent result of the switching circuit from the first overcurrent detection sub-circuit or the second overcurrent detection sub-circuit;

the second overcurrent detection sub-circuit is a second overcurrent detection sub-circuit which sends the result that the switch circuit has the overcurrent to the overcurrent protection circuit when the second overcurrent detection sub-circuit detects that the switch circuit has the overcurrent;

the overcurrent protection circuit is configured to put the switching circuit in an off state after receiving a result that the switching circuit has an overcurrent, which is sent by the first overcurrent detection sub-circuit or the second overcurrent detection sub-circuit.

17. The portable device of claim 16, wherein the switching circuit comprises: a first NMOS and a second NMOS;

18. The portable device of claim 17,