JP6446181B2 - Charging circuit and electronic device using the same - Google Patents

Description

  The present invention relates to a switch circuit.

  When a DC voltage is supplied to a certain terminal (input terminal), there are cases where it is desired to switch between electrical continuity and interruption between the input terminal and another terminal (output terminal). A switch circuit is used for such applications. For example, the related art is disclosed in FIG.

FIG. 1 is a circuit diagram of a switch circuit investigated by the present inventors. The switch circuit 100r in FIG. 1 should not be recognized as a known technique. The switch circuit 100r can switch between conduction and interruption between the input terminal IN and the output terminal OUT. For example, a voltage (battery voltage) _VBAT from the battery 20 is input to the input (IN) terminal, and a smoothing capacitor C1 is connected to the output (OUT) terminal.

The switch circuit 100r includes a transistor M1 and a gate voltage controller 104r. The transistor M1 is a P-channel MOS FEF, and its source is connected to the IN terminal and its drain is connected to the OUT terminal. The gate voltage controller 104r can switch between the first state φ1 that supplies the ground voltage V _GND to the gate of the transistor M1 and the second state φ2 that supplies the gate of the transistor M1 with the voltage V _BAT equal to its source. It has become. In the first state φ1, the transistor M1 is fully turned on and the switch circuit 100r becomes conductive. In the second state φ2, the gate-source voltage of the transistor M1 becomes zero, and the transistor M1 is turned off.

Japanese Patent Laid-Open No. 2002-281692

As a result of studying the switch circuit 100r of FIG. 1, the present inventor has recognized the following problems. Consider the case where the battery 20 is a detachable battery pack. When the battery 20 is removed, the capacitor C1 connected to the OUT terminal is discharged, and the output voltage _VOUT is zero. When the battery 20 is mounted when the gate voltage controller 104r is in the first state φ1, a current flows from the battery 20 to the capacitor C1, the capacitor C1 is charged, and the output voltage _VOUT increases to the vicinity of the battery voltage _VBAT. .

  Here, in order to reduce the loss of the switch circuit 100r, the on-resistance of the transistor M1 is often designed to be about several tens of mΩ. Therefore, if the transistor M1 is fully on when the battery 20 is mounted, there is a problem that a rush current flows from the battery 20 to the capacitor C1.

  In the conventional switch circuit 100r, it is necessary to determine the transistor size of the transistor M1, the wiring width between elements, or the number of bonding wires so that the reliability does not deteriorate even when a rush current flows. However, the rush current is affected by the internal resistance of the battery 20 and the contact resistance between the battery 20 and the battery holder, and these are often unknown or unpredictable. Therefore, the transistor size of the transistor M1 in the switch circuit 100r, The wiring width between elements or the number of bonding wires must be designed in consideration of an excessive margin, and it is difficult to say that the design is optimized.

  The present invention has been made in such a situation, and one of exemplary purposes of an embodiment thereof is to provide a switch circuit capable of suppressing a rush current.

  One embodiment of the present invention relates to a switch circuit. The switch circuit includes an input terminal that receives an input voltage from a DC power supply, an output terminal, a first transistor of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided between the input terminal and the output terminal, A second transistor which is a P-channel MOSFET having an electrode connected to the input terminal, a gate connected to the gate of the first transistor, and a connection between the gate and the second electrode; a second electrode of the second transistor; and a ground line And a resistor provided between the two.

  When an input voltage is supplied to the input terminal, the current flowing through the second transistor gradually increases. Since the gates and sources of the second transistor and the first transistor are connected in common, the current flowing through the first transistor gradually increases in proportion to the current flowing through the second transistor. Thereby, it is possible to prevent a rush current from flowing through the first transistor.

The switch circuit according to an aspect may further include a gate controller provided between the gate of the first transistor and the gate of the second transistor. The gate controller may be capable of switching between a first state in which the gate voltage of the second transistor is supplied to the gate of the first transistor and a second state in which the voltage of the ground line is supplied to the gate of the first transistor. .
By setting the second state after the possibility of generating a rush current is reduced, the first transistor is fully turned on to minimize the on-resistance, thereby reducing power loss.

The gate controller may enter the second state when the potential difference between the voltage at the input terminal and the voltage at the output terminal is smaller than a predetermined value, in other words, when the voltage at the input terminal and the voltage at the output terminal are substantially equal.
When the potential difference between the voltage at the input terminal and the voltage at the output terminal is reduced, the risk of rush current is reduced. According to this aspect, it is possible to reduce power loss while suppressing rush current.

The gate controller may be configured to be able to supply the voltage of the input terminal to the gate of the second transistor.
By applying the voltage of the input terminal to the gate of the second transistor, the second transistor and the first transistor can be turned off. That is, immediately after the battery is connected, the first transistor and the second transistor can be gradually turned on from the off state, and the rush current can be further suppressed.

The switch circuit according to an aspect may further include a shunt switch provided in series with the second transistor and the resistor between the input terminal and the ground line.
By providing the shunt switch, the current flowing from the input terminal to the ground line in the OFF state can be cut off, and wasteful current can be reduced.

  The shunt switch may be on in the first state and off in the second state. Thereby, after the 1st transistor will be in a full-on state, the electric current which passes through a 2nd transistor can be interrupted | blocked.

  The switch circuit includes a first back gate switch provided between the back gate of the first transistor and the first electrode, a second back gate switch provided between the back gate of the first transistor and the second electrode, And a back gate controller that controls the first back gate switch and the second back gate switch.

  As a result, not only when the voltage at the input terminal is higher, but also when the voltage at the output terminal is higher, it is possible to control conduction and interruption between the input terminal and the output terminal, thereby expanding the application of the switch circuit. be able to.

The switch circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes any one of the switch circuits described above.

  Another aspect of the present invention relates to a charging circuit that charges a secondary battery with an external DC power supply and supplies power to a load. The charging circuit includes a DC input terminal that receives a DC voltage from a DC power supply, a battery terminal to which a secondary battery is detachably connected, a system terminal to which a smoothing capacitor is connected, and a first electrode that is connected to the battery terminal. A first transistor which is a P-channel MOSFET, a second transistor which is a P-channel MOSFET whose first electrode is connected to the battery terminal and whose gate is connected to the gate of the first transistor, and a second electrode of the second transistor A resistor provided between the ground line, a third transistor which is a P-channel MOSFET in which the first electrode is connected to the system terminal and the second electrode is connected to the second electrode of the first transistor; A gate controller for controlling the gate voltage of the third transistor, and provided between the system terminal and the DC input terminal; A DC input switch that is turned on when a DC voltage is supplied to the power terminal; a first back gate switch provided between the back gate and the first electrode of the first transistor; A second back gate switch provided between the two electrodes; and a back gate controller for controlling the first back gate switch and the second back gate switch.

  The gate controller may include a charge controller that adjusts the gate voltages of the first transistor and the third transistor when a DC voltage is supplied to the DC input terminal.

  The gate controller is provided between the gate of the first transistor and the gate of the second transistor, and supplies a gate voltage of the second transistor to the gate of the first transistor, and a ground line to the gate of the first transistor. The second state in which the voltage is supplied may be switchable.

  The gate controller may be set to the second state when the voltage at the battery terminal and the voltage at the system terminal are substantially equal.

The charging circuit may further include a shunt switch that is provided in series with the second transistor and the resistor between the battery terminal and the ground line, and is turned off while the secondary battery is being charged by the DC power source.
The shunt switch may be on in the first state and off in the second state.

  The charging circuit may be integrated on a single semiconductor substrate.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes a secondary battery and any of the above-described charging circuits that charge the secondary battery.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, the rush current can be suppressed.

It is a circuit diagram of the switch circuit which this inventor examined. It is a circuit diagram of the switch circuit concerning an embodiment. FIG. 3 is an operation waveform diagram of the switch circuit of FIG. 2. It is a circuit diagram of a switch circuit concerning the 1st modification. FIG. 3 is a circuit diagram of a switch circuit according to a modification. FIG. 6 is an operation waveform diagram of the switch circuit of FIG. 5. It is a circuit diagram of a switch circuit concerning the 3rd modification. It is a circuit diagram of a switch circuit concerning the 4th modification. It is a circuit diagram of an electronic device provided with a charging circuit. It is a perspective view of an electronic device provided with PMIC.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. Including the case of being indirectly connected through other members that do not substantially affect the state of connection, or do not impair the functions and effects achieved by the combination thereof.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

FIG. 2 is a circuit diagram of the switch circuit 100 according to the embodiment. The switch circuit 100 includes a first transistor M1, a second transistor M2, and a resistor R1. A DC power supply, for example, an input voltage _VIN from the battery 20 is input to the IN terminal. The battery 20 is detachable from the IN terminal. A smoothing capacitor C1 and a load (not shown) are connected to the output terminal OUT. The ground (GND) terminal is grounded. The switch circuit 100 is integrated on one semiconductor substrate.

  The first transistor M1 is a P-channel MOSFET, and is provided between the IN terminal and the OUT terminal. The first electrode E1 (source) of the first transistor M1 is connected to the IN terminal, and the second electrode (drain) E2 is connected to the OUT terminal. The back gate of the first transistor M1 is connected to the IN terminal.

  The second transistor M2 is the same type as the first transistor M1, that is, a P-channel MOSFET, the first electrode E1 (source) is connected to the IN terminal, and the control electrode (gate) is connected to the gate of the first transistor M1. Is done. The resistor R1 is provided between the second electrode E2 (drain) of the second transistor M2 and the ground line 102. The ground line 102 is grounded via a GND terminal. The gate of the second transistor M2 is connected to its drain.

The transistor sizes of the first transistor M1 and the second transistor M2 are designed to be N: 1 (N> 1). At this time, current _{I S} flowing through the current _{I OUT} and the second transistor M2 flowing to the first transistor M1, N: 1 relationship is established.

For example N, the current I _S flowing through the second transistor M2 may be determined so that the order of several tens of .mu.A. When the rating is 300 mA, N may be 10,000. In this case, the current I _S = 300 mA / 10000 = 30 μA.

The resistance value of the resistor R1 is determined so that (V _BAT −V _GS ) / R1 is on the order of several tens of μA. V _GS is a gate-source voltage of the MOSFET. For example, when V _BAT = 3.5 V and V _GS = 0.5 V, R1 is several tens of kΩ to several hundreds of kΩ.

The above is the configuration of the switch circuit 100. Next, the operation will be described. FIG. 3 is an operation waveform diagram of the switch circuit 100 of FIG. Prior to time t0, the battery 20 is removed, the input voltage _VIN is zero (ground voltage _VGND ), and the output voltage _VOUT is also zero. The gates of the first transistor M1 and the second transistor M2 are _pulled down to the ground voltage V _GND by the resistor R1, and therefore the gate voltage V _G is zero.

At time t0, the battery 20 is attached. When the battery 20 is attached, the input voltage _VIN immediately rises to the battery voltage _VBAT . The gate-source voltage _{V GS} of the first transistor M1 and the second transistor M2 is _V IN -V _G, when the _V IN _{= V BAT} at time t0, the first transistor M1, the second transistor M2 is turned on.

When the second transistor M2 is turned on, the current _IS starts to flow and gradually increases with time. When the current I _S is increased, the voltage drop of the resistor R1 is increased, thus also the gate voltage V _G of the second transistor M2 gradually increases. When the gate voltage V _G is increased, the gate-source voltage V _GS of the second transistor M2 is reduced, the current I _S is so negative feedback is returned low. Eventually the current _{I S} is clamped by a certain amount of current _{I CL.}
I _CL = (V _BAT −V _GS ) / R1

Since the first transistor M1 and the second transistor M2 have the same gate-source voltage, a current I _OUT = N × I _S proportional to the current I _S of the second transistor M2 flows through the first transistor M1.

By the capacitor C1 is charged by current _{I OUT} of the first transistor M1, the output voltage _{V OUT} increases. Eventually, when V _OUT ≈V _BAT , the drain-source voltage of the first transistor M1 becomes substantially equal, and the current I _OUT becomes zero.

The above is the operation of the switch circuit 100. The advantage of the switch circuit 100 becomes clear by comparison with the switch circuit 100r of FIG. For comparison, FIG. 3 shows the operation of the switch circuit 100r of FIG. In the switch circuit 100r, the gate voltage V _G of the transistor M1 is fixed to 0 V, and is always full on. Therefore, the current I _{OUT of the} transistor M1 increases without any restriction and becomes a rush current.

In the switch circuit 100 of FIG. 2 with respect to this, the current _{I OUT} flowing through the first transistor M1 is proportional to the current _{I S} flowing through the second transistors M2, gradually increases to the amount of current _{I CL} × N Will be clamped. Thereby, a rush current can be suppressed.

  Next, a modified example of the switch circuit 100 will be described.

(First modification)
FIG. 4 is a circuit diagram of the switch circuit 100a according to the first modification.
The switch circuit 100a includes a gate controller 104 in addition to the switch circuit 100 of FIG. The gate controller 104 is provided between the gate of the first transistor M1 and the gate of the second transistor M2. The gate controller 104 includes a first state φ1 in which the gate of the first transistor M1 and the gate of the second transistor M2 are conductive, a second state φ2 in which the gate of the first transistor M1 and the ground line 102 are conductive, Can be switched.

The gate controller 104 enters the first state φ1 when V _IN > V _OUT and there is a possibility of occurrence of a rush current, and the second state φ2 when V _IN ≈V _OUT and there is no possibility of occurrence of a rush current. Become.

For example, the gate controller 104 includes a selector 106 and a comparator 108. The selector 106 has two inputs and one output, the first input terminal is connected to the gate of the second transistor M2, the second input terminal is connected to the ground line 102, and the output terminal is connected to the gate of the first transistor M1. The The comparator 108 controls the selector 106 in accordance with the potential difference between the input voltage _VIN and the output voltage _VOUT . For example, the comparator 108 sets the selector 106 to the first state φ1 when the potential difference is larger than a predetermined threshold value, and sets the selector 106 to the second state φ2 when the potential difference is smaller than the threshold value.

  The configuration of the gate controller 104 is not limited to that of FIG.

  According to the switch circuit 100a of FIG. 4, by switching to the second state φ2 after the possibility of generating a rush current is reduced, the first transistor M1 is fully turned on to minimize its on-resistance, thereby reducing power loss.

The rush current contact it decreases the potential difference between the voltage _{V OUT} of the voltage _{V IN} and OUT terminals of the IN terminal is reduced. Therefore, by controlling the state of the gate controller 104 according to the potential difference between the input / output voltages V _IN and V _OUT , power loss can be reduced while suppressing the rush current.

(Second modification)
FIG. 5 is a circuit diagram of the switch circuit 100b according to the second modification.
The gate controller 104 of the switch circuit 100b is configured to be able to supply the input voltage _VIN to the gate of the second transistor M2. For example, the gate controller 104 includes a switch 110 provided between the gate and source of the second transistor M2.

  When the switch 110 is turned on, the gate-source voltage of the second transistor M2 becomes zero, and the second transistor M2 is turned off. In this state, when the selector 106 is in the first state φ1, the first transistor M1 is also turned off.

FIG. 6 is an operation waveform diagram of the switch circuit 100b of FIG. The initial state is the first state φ1. At time t0, the battery 20 is mounted, and the input voltage _VIN becomes the battery voltage _VBAT . The switch 110 is turned on immediately after the battery 20 is connected. Therefore, the gate-source voltage of the second transistor M2 and the first transistor M1 is zero, and the first transistor M1 is turned off.

When the switch 110 is turned off at time t1, the gate voltage of the second transistor M2 is pulled down by the resistor R1, and the second transistor M2 is turned on. As a result, the current _IS starts to flow through the second transistor M2, and the gate voltage V _G approaches V _BAT −V _GS while being affected by the negative feedback by the resistor R1.

When eventually the output voltage _{V OUT} at time t2 is equal to the input voltage _{V BAT} and substantially the second state φ2, and the gate voltage is a ground voltage 0V and the first transistor M1, it is full-on.

According to this modified example, immediately after the battery 20 is mounted, the second transistor M2 is to begin to flow a current I _S from off, it can be suppressed more rush current.

(Third Modification)
FIG. 7 is a circuit diagram of a switch circuit 100c according to a third modification. The switch circuit 100c further includes a shunt switch 112 in addition to the switch circuit 100b of FIG. The shunt switch 112 is provided in series with the second transistor M2 and the resistor R1 on a path from the IN terminal to the ground line 102. The rest is the same as the switch circuit 100b of FIG.

  For example, the shunt switch 112 may be turned off after the gate controller 104 is turned on while the gate controller 104 is in the second state φ2 while the gate controller 104 is in the second state φ2. In addition, the shunt switch 112 may be turned off in the system shutdown state.

Second transistors M2, the current I _S flowing through the resistor R1 is a loss that is not supplied to the load, it can be said that the leakage current. According to this modification, by providing a shunt switch 112 in its OFF state, it can cut off the current I _S that flows from the IN terminal to the ground line 102, thereby reducing the useless leakage current.

(Fourth modification)
FIG. 8 is a circuit diagram of a switch circuit 100d according to a fourth modification.
The switch circuit 100d further includes a DC input (DCIN) switch, a DC input switch 114, a first back gate switch SW11, a second back gate switch SW12, and a back gate controller 130 in addition to the switch circuit 100c of FIG.

A DC voltage _VDC from a DC power source (not shown) is input to the DCIN terminal. The switch circuit 100d selects one of the battery voltage V _BAT and the DC voltage V _DC and outputs it from the OUT terminal. The DC input switch 114 is provided between the DCIN terminal and the OUT terminal. DC input switch 114 is turned on when the DC voltage _{V DC} from DC power source is input.

The first back gate switch SW11 is provided between the first electrode E1 and the back gate of the first transistor M1, and the second back gate switch SW12 is provided between the second electrode E2 and the back gate. The back gate controller 130 complementarily controls on and off of the first back gate switch SW11 and the second back gate switch SW12. Specifically, the back gate controller 130 turns on the first back gate switch SW11 when V _IN > V _OUT and turns on the second back gate switch SW12 when V _IN <V _OUT .

  As a result, not only when the voltage at the input terminal is higher, but also when the voltage at the output terminal is higher, conduction and interruption between the input terminal and the output terminal can be controlled.

(Use)
Next, the application of the switch circuit according to the embodiment will be described. The switch circuit can be suitably used for a charging circuit that charges a secondary battery.
FIG. 9 is a circuit diagram of the electronic device 1 including the charging circuit 10. The electronic device 1 includes a charging circuit 10, a secondary battery 20, a power supply circuit 22, a CPU 24, and a plurality of peripheral circuits 26. The secondary battery 20 is a lithium ion battery or a nickel metal hydride battery, and outputs a battery voltage _VBAT .

The plurality of peripheral circuits 26 include a memory (RAM: Random Access Memory), a hard disk, a display, and the like. A DC power source 2 such as an AC adapter or a USB host can be attached to and detached from an external power source (EXT) terminal of the electronic device 1 and supplied with a DC voltage _VDC .

When the DC power source 2 is connected to the EXT terminal, the charging circuit 10 receives the DC voltage _VDC and charges the secondary battery 20. The charging circuit 10 selects one of the battery voltage V _{BAT and the} DC voltage V _DC and outputs the system voltage V _SYS from the system (SYS) terminal.

The power supply circuit 22 receives the system voltage _VSYS , generates a power supply voltage V _DD by stepping up or down the system voltage _VSYS , and supplies the power supply voltage V _DD to the CPU 24 and the peripheral circuit 26 that are loads. The power supply circuit 22 includes a DC / DC converter, a charge pump circuit, a linear regulator (LDO: Low Drop Output), and the like.

  The charging circuit 10 is configured using the switch circuit 100 according to the embodiment or a modification thereof. The charging circuit 10 of FIG. 9 is configured based on the switch circuit 100d of FIG. The BAT terminal, DCIN terminal, and SYS terminal in FIG. 9 correspond to the IN terminal, DCIN terminal, and OUT terminal in FIG. 8, respectively.

The DC voltage _VDC from the DC power source 2 is input to the direct current input (DCIN) terminal, and the secondary battery 20 is connected to the battery (BAT) terminal. The DC input switch 114 is provided between the DCIN terminal and the SYS terminal. For example, the DC input switch 114 includes two N-channel MOSFETs connected in reverse series.

The DC power supply detection unit 124 determines whether or not the DC power supply 2 is connected based on the voltage of the DCIN terminal. The gate controller 120 turns on the DC input switch 114 when the DC power source 2 is connected and a normal DC voltage V _DC is supplied. When the DC input switch 114 is turned on, the DC voltage _VDC appears at the SYS terminal.

The first transistor M1 is provided between the SYS terminal and the BAT terminal. Back gate switches SW11 and SW12 are provided between the back gate of the first transistor M1 and the first electrode E1, and between the back gate and the second electrode E2, respectively. The back gate controller 130 controls the first back gate switch SW11 and the second back gate switch SW12 in a complementary manner. The back gate controller 130 turns on the first back gate switch SW11 when V _SYS <V _BAT , and turns on the second back gate switch SW12 when V _SYS > V _BAT .

The gate controller 104 includes a charge controller 122. When the normal DC voltage V _DC is supplied, the charge controller 122 charges the secondary battery 20.

  The above is the configuration of the charging circuit 10. Next, the operation will be described. This will be explained in several cases.

1. When both the DC power source 2 and the battery 20 are connected, the DC input switch 114 is turned on. The selector 106 enters the third state φ3, and connects the output of the charge controller 122 to the gate of the first transistor M1. Since V _SYS > V _BAT , the second back gate switch SW12 is turned on and the first back gate switch SW11 is turned off. The shunt switch 112 is off.

A DC voltage _VDC from the DC power supply 2 is supplied to the power supply circuit 22 connected to the SYS terminal. Further, the charge controller 122 adjusts the gate voltage of the first transistor M1, and charges the secondary battery 20 in the CC (constant current) charge mode or the CV (constant voltage) charge mode.

2. When the DC power source 2 is not connected and the battery 20 is connected, the DC input switch 114 is off. The gate controller 104 is in the second state φ2, and the first transistor M1 is fully turned on. Since V _SYS <V _BAT , the first back gate switch SW11 is turned on and the second back gate switch SW12 is turned off. The battery voltage V _BAT from the battery 20 is supplied to the power supply circuit 22 connected to the SYS terminal. The shunt switch 112 is off.

3. When both the DC power source 2 and the battery 20 are not connected In the initial state, the gate controller 104 is in the first state φ1. Then, according to the flow shown in FIG. 3, the first transistor M1 is gradually turned on, and the voltage V _SYS at the SYS terminal gradually increases. When V _SYS = V _BAT is detected by the comparator 108, the second state φ2 is entered, and the first transistor M1 is fully turned on.

  The above is the operation of the charging circuit 10. According to the charging circuit 10, it is possible to suppress a rush current that flows into the SYS terminal when the battery 20 is attached.

The charging circuit 10 and the power supply circuit 22 in FIG. 9 may be integrated. In order to start and stop the electronic device 1 normally, it is necessary to generate and stop the power supply voltage V _DD for the CPU 24 and the peripheral circuit 26 in accordance with a predetermined sequence. For this reason, a power management controller may be mounted. . Therefore, the charging circuit 10, the power supply circuit 22, and the power management (PM) controller may be integrated into one IC (referred to as PMIC).

  Finally, the use of the charging circuit 10 will be described. FIG. 10 is a perspective view of an electronic device 500 that includes the PMIC 40. The electronic device 500 is, for example, a tablet terminal or a smart phone. The housing 520 includes a CPU 24, a peripheral circuit 26 such as a RAM and an HDD, a secondary battery 20, and a PMIC 40. The PMIC 40 may supply a power supply voltage to the display panel 510, its driver, audio circuit, and the like in addition to the CPU 24, RAM, and HDD. Note that the electronic device 500 may be a notebook PC, console game device, portable game device, wearable PC, portable audio player, digital camera, or the like.

  Note that the electronic device 500 may include the charging circuit 10 and the power supply circuit 22 separately instead of the PMIC 40.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... DC power supply, 10 ... Charging circuit, 20 ... Battery, 22 ... Power supply circuit, 24 ... CPU, 26 ... Peripheral circuit, 100 ... Switch circuit, 102 ... Ground line, 104 ... Gate controller, 106 ... Selector, 108 ... Comparator, 110 ... Switch, 112 ... Shunt switch, 114 ... DC input switch, 120 ... Gate controller, 122 ... Charge controller, 124 ... DC power supply detection unit, 130 ... Back gate controller, M1 ... First transistor, M2 ... second transistor, R1 ... resistor, C1 ... capacitor, SW11 ... first back gate switch, SW12 ... second back gate switch.

Claims (8)

A charging circuit that charges a secondary battery with an external DC power source and supplies power to a load,
A DC input terminal for receiving a DC voltage from a DC power source;
A battery terminal to which the secondary battery is detachably connected;
A system terminal to which a smoothing capacitor is connected;
A first transistor that is a P-channel MOSFET with a first electrode connected to the battery terminal;
A second transistor that is a P-channel MOSFET, the first electrode being connected to the battery terminal, the gate being connected to the gate of the first transistor, and the gate and the second electrode being always connected;
A resistor provided between the second electrode of the second transistor and a ground line;
A gate controller for controlling a gate voltage of each of the first transistor and the second transistor;
A DC input switch that is provided between the system terminal and the DC input terminal, and becomes conductive when the DC voltage is supplied to the DC input terminal;
A first back gate switch provided between a back gate and a first electrode of the first transistor;
A second back gate switch provided between the back gate and the second electrode of the first transistor;
A back gate controller for controlling the first back gate switch and the second back gate switch;
A charging circuit comprising: The gate controller, when said DC voltage is supplied to the DC input terminals, the charging circuit according to claim 1, characterized in that it comprises a charge controller to adjust the gate voltage of the first transistor. The gate controller includes a first state in which the gate voltage of the second transistor is supplied to the gate of the first transistor when the DC voltage is not supplied to the DC input terminal, and a ground line to the gate of the first transistor. 3. The charging circuit according to claim 1 , wherein the charging circuit is configured to be switchable between the second state in which the voltage of 2 is supplied. 4. The gate controller is set to the second state when the voltage of the battery terminal and the voltage of the system terminal are substantially equal when the DC voltage is not supplied to the DC input terminal. The charging circuit according to claim 3 . A shunt switch that is provided in series with the second transistor and the resistor between the battery terminal and the ground line and further turns off while the secondary battery is being charged by the DC power source. The charging circuit according to claim 3 or 4 . The charging circuit according to claim 5 , wherein the shunt switch is on in the first state and off in the second state. The charging circuit according to claim 1 , wherein the charging circuit is integrated on a single semiconductor substrate. A secondary battery,
The charging circuit according to any one of claims 1 to 7 , wherein the secondary battery is charged;
An electronic device comprising:

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