CN202794346U - Pulse width detection circuit - Google Patents
Pulse width detection circuit Download PDFInfo
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- CN202794346U CN202794346U CN 201220304664 CN201220304664U CN202794346U CN 202794346 U CN202794346 U CN 202794346U CN 201220304664 CN201220304664 CN 201220304664 CN 201220304664 U CN201220304664 U CN 201220304664U CN 202794346 U CN202794346 U CN 202794346U
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Abstract
The utility model provides a pulse width detection circuit, comprising: an oscillation module used for providing a clock signal; a counting module, wherein a clock input end of the counting module is connected with an output end of the oscillation module, and the counting module is used for counting the number of pulses of the clock signals; a reset module, wherein an output end of the reset module is connected with a reset end of the counting module, and the reset module is used for performing reset for the counting module; and a power supply module connected with an enable end of the counting module and used for providing an enable signal to the counting module. The pulse width detection circuit of the utility model ensures that an enable signal of an oscillator is synchronous with an input clock signal of a counter without externally connecting an input clock, and enables the counter to perform counting with a complete clock period, therefore, the pulse width detection circuit can effectively reduce detection error of the pulse width, and can raise detection precision.
Description
Technical field
The utility model relates to the pulse width detection circuit field, relates in particular to a kind of pulse width detection circuit that can effectively reduce the detection error.
Background technology
In integrated circuit (IC) design, the pulse width of often understanding pulse signals detects, and this just need to use pulse width detection circuit.Fig. 1 is existing pulse width detection circuit, pulse signal Pulse_in to be detected is as the enable signal EN of counter, counter utilizes the input clock CLK_IN of known clock period to come the term of validity that enables of counter is counted, and final detects the number that the pulse width that obtains is the output OUT(clock of counter) with the product of clock period.Pulse width detection circuit shown in Figure 1 is simple, but the present utility model people finds, such scheme is Shortcomings also: enable signal EN and the input clock CLK_IN of counter can't be synchronous, and there is error in the result who detects like this, can't satisfy the requirement of high measurement accuracy.
The utility model content
The utility model detects the technical matters of error for solving pulse width, a kind of pulse width detection circuit is provided.
The utility model provides a kind of pulse width detection circuit, comprises oscillation module, is used for providing clock signal; Counting module, the input end of clock of described counting module is connected with the output terminal of described oscillation module, is used for calculating the number of cycles of described clock signal; Reseting module, its output terminal is connected with the reset terminal of described counting module, is used for counting module is resetted; Power module is connected with the Enable Pin of counting module, and being used for provides enable signal to counting module.
Preferably, described oscillation module comprises oscillator, and pulse signal to be measured connects the Enable Pin of described oscillator, and reset signal connects the reset terminal of described oscillator.
Preferably, described oscillation module comprises oscillator and the first phase inverter, and pulse signal to be measured connects the input end of described the first phase inverter, and the output terminal of described the first phase inverter connects the Enable Pin of described oscillator, and reset signal connects the reset terminal of described oscillator.
Preferably, described pulse signal to be measured is specially square-wave signal.
Preferably, described reseting module comprise a rising edge testing circuit and one and the door, the input end of described rising edge testing circuit connects pulse signal to be measured, output terminal with described with first input end be connected, described with the second input end be connected reset signal.
Preferably, described rising edge testing circuit comprises inverter group and the Sheffer stroke gate that the phase inverter of odd number series connection forms, the input end of described inverter group is connected with pulse signal to be measured, the output terminal of described inverter group is connected with the first input end of described Sheffer stroke gate, pulse signal to be measured respectively with the input end of described inverter group be connected the second input end of Sheffer stroke gate and be connected.
Preferably, described counting module is the counter of a N position.
Compare with pulse width detection circuit commonly used, the utility model is by the oscillation module clocking, therefore do not need external input clock, counting module keeps duty always, when the oscillation module clock signal, counting module can begin to count with the complete clock period, thereby can effectively reduce the detection error of pulse width, improved accuracy of detection.
Description of drawings
Fig. 1 is the existing pulse width detection circuit figure of the utility model.
Fig. 2 is the circuit diagram of the utility model pulse width detection circuit the first embodiment.
Fig. 3 is the circuit diagram of the utility model pulse width detection circuit the second embodiment.
Fig. 4 is the circuit diagram of a kind of embodiment of the utility model rising edge testing circuit.
Embodiment
Clearer for technical matters, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
With reference to Fig. 2, the circuit diagram of the utility model pulse width detection circuit the first embodiment is shown.Pulse width detection circuit comprises oscillation module 1, is used for providing clock signal; Counting module 3, its input end of clock is connected with the output terminal of described oscillation module, is used for calculating the number of cycles of described clock signal; Reseting module 2, its output terminal is connected with the reset terminal of described counting module, is used for counting module is resetted; Power module 4 is connected with the Enable Pin of counting module, and being used for provides enable signal to counting module.
In the present embodiment, described power module 4 is power supply VCC, described oscillation module 1 is an oscillator, described counting module 3 is a N digit counter, pulse signal Pulse_in to be measured is that impulse level is the square-wave pulse signal of high level, the Enable Pin EN of its connection oscillator, the reset terminal RST of oscillator meets reset signal Reset, and the output terminal OUT clock signal CLK1 of oscillator meets the input end of clock CLK of counter; Described reseting module 2 comprise rising edge testing circuit and one two input with door AND1, pulse signal Pulse_in is surveyed in the input end reception of rising edge testing circuit, output termination two inputs of rising edge testing circuit and the input end of door AND1, another input termination reset signal Reset of two inputs and door AND1, two input the reset terminal RST that connects counter with an output signal RST1 of AND1 output terminal; The input end EN that enables of counter meets power supply VCC, output terminal Q[n:1] meet OUT[n:1], OUT[n:1] as the output of whole testing circuit, offer other circuit.
The utility model adopts power supply VCC as the enable signal of counter, makes counter keep duty always; The clock signal clk 1 of simultaneously oscillator generation does not need to connect in addition input clock signal as the input clock signal of counter, and the work start-stop of oscillator is controlled by pulse Pulse_in to be detected.When detecting impulse level and be the pulse Pulse_in to be measured of high level, oscillator clocking CLK1, unison counter begins to count, and the product of the clock period that the output of counter (number of cycles of clock signal clk 1) and oscillator are intrinsic is pulse width to be detected.The pulse width detection circuit that the utility model provides can guarantee that the enable signal (pulse Pulse_in to be measured) of oscillator keeps synchronously with the input clock signal CLK1 of counter is whole, thereby so that counter can be counted with the complete clock period, can effectively reduce the detection error of pulse width, improve accuracy of detection.
The circuit working principle is as follows: original state, and power supply VCC powers on, and reset signal Reset resets to the oscillator sum counter, and each output is low level, and circuit is started working afterwards.
When pulse signal Pulse_in to be measured was in low level, the input end EN that enables of oscillator enabled invalidly, and oscillator is not worked, and is output as low level, and counter does not have the clock input, does not count; When Pulse_in became high level by low level, the input end that enables of oscillator EN enabled effectively, and oscillator is started working, and clock signal CLK_1 provides the clock input to counter, and counter begins counting; When Pulse_in becomes low level by high level again, oscillator quits work, counter stops counting and keeps count results, the output OUT[n:1 of this hour counter] namely represent pulse signal Pulse_in to be measured and in one-period, begin to finish the number of cycles that oscillator produces to high level from high level, be the number of cycles of clock signal CLK_1, so just can calculate: the count value of the clock period * counter of pulse width to be measured (time)=oscillator.
In implementation, described rising edge testing circuit comprises inverter group and the Sheffer stroke gate that the phase inverter of odd number series connection forms, the input end of described inverter group is connected with pulse signal to be measured, the output terminal of described inverter group is connected with the first input end of described Sheffer stroke gate, pulse signal to be measured respectively with the input end of described inverter group be connected the second input end of Sheffer stroke gate and be connected.
Figure 4 shows that the circuit diagram of a kind of embodiment of the utility model rising edge testing circuit, the rising edge testing circuit comprises one second phase inverter inv2 and a Sheffer stroke gate nand, the input end of the second phase inverter inv2 be connected pulse signal Pulse_in and connect, the output terminal of the second phase inverter inv2 is connected first input end and is connected with Sheffer stroke gate nand, pulse signal Pulse_in to be measured is connected the second input end with the input end of the second phase inverter respectively and is connected with Sheffer stroke gate nand.Its principle of work is as follows: as input signal in, when namely pulse signal Pulse_in to be detected was low level, this testing circuit output out was high level; When input signal in transfers high level to by low level, be that pulse signal Pulse_in to be detected is when transferring high level to by low level, because anti-phase output b has an of short duration time-delay (a few approximately nanosecond), so testing circuit output this moment out is low level, time-delay is exported out later and is become high level.
The effect of this rising edge testing circuit is the rising edge that detects pulse signal Pulse_in to be measured, and constantly export the low level pulse of of short duration (a few approximately nanosecond) at pulse signal Pulse_in rising edge to be measured, allow counter advanced horizontal reset before beginning to count, count from zero to guarantee it.So, when needs detect counting to pulse signal Pulse_in to be measured, just first counter has been resetted.
With reference to Fig. 3, the circuit diagram of the utility model pulse width detection circuit the second embodiment is shown, comprise oscillation module 1, reseting module 2, counting module 3 and power module 4.Described power module 4 is power supply VCC; Described counting module 3 is the counter of a N position; Described oscillation module 1 comprises an oscillator and the first phase inverter inv1, pulse signal Pulse_in to be measured is that impulse level is low level square-wave pulse signal, Enable Pin EN through the first phase inverter inv1 connection oscillator, the reset terminal RST of oscillator meets reset signal Reset, and the clock signal CLK1 of output terminal OUT meets the input end of clock CLK of counter; Described reseting module 2 comprise rising edge testing circuit and one two input with door AND1, pulse signal Pulse_in ' after the input termination of rising edge testing circuit is anti-phase through the first phase inverter inv1, the input end of two inputs of output termination and door AND1, another input termination reset signal Reset of two inputs and door AND1, the output signal RST1 of output terminal meets the reset terminal RST of counter; The input end EN that enables of counter meets power supply VCC, and input end of clock CLK connects clock signal clk 1, output terminal Q[n:1] meet OUT[n:1], OUT[n:1] as the output of whole circuit, process for other circuit.
The circuit working principle is as follows: original state, and power supply VCC powers on, and reset signal Reset resets to the oscillator sum counter, and each output is low level, and circuit is started working afterwards.
When pulse signal Pulse_in was in high level, the input end EN that enables of oscillator enabled invalidly, and oscillator is not worked, and is output as low level, and counter does not have the clock input, does not count; When Pulse_in became low level by high level, the input end that enables of oscillator EN enabled effectively, and oscillator is started working, and clock signal CLK_1 provides the clock input to counter, and counter begins counting; When Pulse_in becomes high level by low level again, oscillator quits work, counter stops counting and keeps count results, the output OUT[n:1 of this hour counter] namely represent pulse signal Pulse_in to be measured and in one-period, begin to finish the number of cycles that oscillator produces to low level from low level, be the number of cycles of clock signal CLK_1, so just can calculate: the count value of the clock period * counter of pulse width to be measured (time)=oscillator.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (7)
1. a pulse width detection circuit is characterized in that: comprise
Oscillation module is used for providing clock signal;
Counting module, the input end of clock of described counting module is connected with the output terminal of described oscillation module, is used for calculating the number of cycles of described clock signal;
Reseting module, its output terminal is connected with the reset terminal of described counting module, is used for counting module is resetted;
Power module is connected with the Enable Pin of counting module, and being used for provides enable signal to counting module.
2. pulse width detection circuit as claimed in claim 1 is characterized in that, described oscillation module comprises oscillator, and pulse signal to be measured connects the Enable Pin of described oscillator, and reset signal connects the reset terminal of described oscillator.
3. pulse width detection circuit as claimed in claim 1, it is characterized in that, described oscillation module comprises oscillator and the first phase inverter, pulse signal to be measured connects the input end of described the first phase inverter, the output terminal of described the first phase inverter connects the Enable Pin of described oscillator, and reset signal connects the reset terminal of described oscillator.
4. pulse width detection circuit as claimed in claim 2 or claim 3 is characterized in that described pulse signal to be measured is specially square-wave signal.
5. pulse width detection circuit as claimed in claim 1, it is characterized in that, described reseting module comprise a rising edge testing circuit and one and the door, the input end of described rising edge testing circuit connects pulse signal to be measured, output terminal is connected with described first input end with door, and described the second input end with door is connected reset signal.
6. pulse width detection circuit as claimed in claim 5, it is characterized in that, described rising edge testing circuit comprises inverter group and the Sheffer stroke gate that the phase inverter of odd number series connection forms, the input end of described inverter group is connected with pulse signal to be measured, the output terminal of described inverter group is connected with the first input end of described Sheffer stroke gate, pulse signal to be measured respectively with the input end of described inverter group be connected the second input end of Sheffer stroke gate and be connected.
7. pulse width detection circuit as claimed in claim 1 is characterized in that, described counting module is the counter of a N position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304664 CN202794346U (en) | 2012-06-27 | 2012-06-27 | Pulse width detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304664 CN202794346U (en) | 2012-06-27 | 2012-06-27 | Pulse width detection circuit |
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| CN202794346U true CN202794346U (en) | 2013-03-13 |
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| CN 201220304664 Expired - Fee Related CN202794346U (en) | 2012-06-27 | 2012-06-27 | Pulse width detection circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103994713A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring method |
| CN103995218A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring device |
| CN104202040A (en) * | 2014-09-04 | 2014-12-10 | 南京矽力杰半导体技术有限公司 | Detecting circuit and method for bit level |
| CN109580975A (en) * | 2018-12-10 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of speed detector based on pwm signal, processing circuit and chip |
| CN117538622A (en) * | 2024-01-08 | 2024-02-09 | 湖南进芯电子科技有限公司 | Pulse width measuring circuit and pulse width measuring method |
-
2012
- 2012-06-27 CN CN 201220304664 patent/CN202794346U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103994713A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring method |
| CN103995218A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring device |
| CN104202040A (en) * | 2014-09-04 | 2014-12-10 | 南京矽力杰半导体技术有限公司 | Detecting circuit and method for bit level |
| CN104202040B (en) * | 2014-09-04 | 2017-09-29 | 南京矽力杰半导体技术有限公司 | Bit level detects circuit and method |
| CN109580975A (en) * | 2018-12-10 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of speed detector based on pwm signal, processing circuit and chip |
| CN109580975B (en) * | 2018-12-10 | 2023-09-05 | 珠海一微半导体股份有限公司 | Speed detector, processing circuit and chip based on PWM signal |
| CN117538622A (en) * | 2024-01-08 | 2024-02-09 | 湖南进芯电子科技有限公司 | Pulse width measuring circuit and pulse width measuring method |
| CN117538622B (en) * | 2024-01-08 | 2024-03-26 | 湖南进芯电子科技有限公司 | Pulse width measuring circuit and pulse width measuring method |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130313 Termination date: 20190627 |
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| CF01 | Termination of patent right due to non-payment of annual fee |