CN113092858B - High-precision frequency scale comparison system and comparison method based on time-frequency information measurement - Google Patents

Abstract

The invention provides a high-precision frequency standard comparison system and comparison method based on time-frequency information measurement, including a frequency standard module, a frequency standard pulse signal module, an adjustable delay module, a phase detection module, and a gate generation module connected in sequence. module, time interval measurement module, data processing module and display module, the signal output terminal of the frequency standard pulse signal module is also connected with the signal input terminal of the time interval measurement module, and also includes the measured frequency module and the measured pulse signal module. The signal output end of the pulse signal module is connected with the signal input end of the phase detection module and the time interval measurement module; the invention avoids the normalization processing of the frequency in the traditional frequency standard comparison method, and uses the FPGA technology to overcome the influence of additional noise , so that the robustness of the system is further strengthened; the invention realizes fast and direct phase measurement of any frequency relationship in the radio frequency range, and accelerates the speed of frequency standard comparison.

Description

A high-precision frequency standard comparison system and comparison method based on time-frequency information measurement

technical field

The invention relates to a frequency standard comparison system and a comparison method, in particular to a high-precision frequency standard comparison system and a comparison method based on time-frequency information measurement.

Background technique

In the measurement of time-frequency information, the traditional frequency standard comparison method is based on the same-frequency phase comparison. For the phase comparison between different frequency standard signals, it is necessary to go through complex processes such as frequency mixing, frequency doubling, and frequency synthesis. The frequency conversion process normalizes the frequency. The normalization of the frequency not only complicates the system structure and increases the cost, but also easily introduces additional noise of the synthetic circuit, so that the accuracy of the frequency standard comparison and the frequency of the frequency measurement are stable. It is difficult to guarantee the degree of accuracy; the inter-frequency phase comparison method can directly complete the phase measurement between the two comparison signals without frequency normalization, which overcomes the defects of the traditional frequency standard comparison method in principle, but the inter-frequency phase comparison method obtains The basis of high precision is the fixed frequency relationship between the two comparison signals. For the phase comparison between the two frequency standard signals under the complex frequency relationship and the large frequency difference relationship, due to the difficulty in generating the phase coincidence point of the gate signal, the measured Accuracy and stability will be greatly reduced, and even cause the system to be unable to measure.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a high-precision frequency standard comparison system and comparison method based on time-frequency information measurement, which can change the passive generation of the phase coincidence point as the gate signal into active detection, and realize the detection of any frequency relationship under complex background. The direct phase measurement improves the response time of the frequency standard comparison in the time-frequency information measurement, that is, the second-level frequency stability of the speed and frequency measurement, and enhances the stability and reliability of the system.

In order to achieve the above object, the present invention adopts the following technical solutions:

A high-precision frequency standard comparison system based on time-frequency information measurement, including a frequency standard module, a measured frequency module, a frequency standard pulse signal module, a measured pulse signal module, an adjustable delay module, a phase detection module, and a gate generation module module, time interval measurement module, data processing module, display module and power supply module; frequency standard module, frequency standard pulse signal module, adjustable delay module, phase detection module, gate generation module, time interval measurement module, data processing module and The display modules are connected in sequence, the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module, the signal output end of the measured frequency module is connected with the signal input end of the measured pulse signal module, and the measured pulse signal The signal output end of the module is connected with the signal input end of the phase detection module and the time interval measurement module;

The frequency standard module is used to generate a frequency standard signal with a frequency accuracy higher than ±1×10 ^-12 magnitude;

The measured frequency module is used to generate a comparison frequency signal whose frequency accuracy is lower than ±1×10 ^-12 magnitude, that is, the measured frequency signal;

The frequency standard pulse signal module and the measured pulse signal module are respectively used to generate a rectangular frequency standard pulse signal with a duty ratio of 50% and a rectangular measured pulse signal with a duty ratio of 50%;

The adjustable time delay module is used for generating the fixed time delay signal and the fine-tuning time delay signal of the frequency standard signal;

The phase detection module is used to generate the phase coincidence point pulse signal;

The gate generation module is used to generate the reference gate time interval and the actual gate switch signal;

The time interval measurement module is used to generate the count value of the frequency standard signal and the measured frequency signal;

The data processing module is used to process the count value of the frequency standard signal and the measured frequency signal, and generate the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system;

The display module is used for receiving and displaying the processing result of the data processing module.

The frequency standard module uses a 10MHz 5071A high-performance cesium atomic frequency standard with a frequency accuracy of ±5×10 ^-13 .

The measured frequency module adopts a crystal oscillator or a KDS rubidium atomic clock, and the frequency accuracy is lower than the order of ±1×10 ^-12 .

The frequency standard pulse signal module and the measured pulse signal module both use Schmitt contactor 74LS14N chips.

The adjustable delay module is composed of a first-level delay circuit, a second-level delay circuit and a third-level delay circuit;

The first stage delay circuit is composed of a first edge type D flip-flop 74LS175 chip and a first D flip-flop 74LS375 chip, the first edge type D flip-flop 74LS175 chip and the signal input end of the first D flip-flop 74LS375 chip , that is, the signal input end of the first stage delay circuit is connected to the signal output end of the frequency standard pulse signal module, the signal output end of the first D flip-flop 74LS375 chip is connected to the signal input end of the second stage delay circuit, the first The signal output end of the edge type D flip-flop 74LS175 chip is connected to the signal input end of the phase detection module;

The second stage delay circuit is composed of a second edge type D flip-flop 74LS175 chip and a second D flip-flop 74LS375 chip, the second edge type D flip-flop 74LS175 chip and the signal input end of the second D flip-flop 74LS375 chip , that is, the signal input terminal of the second stage delay circuit is connected to the signal output terminal of the first D flip-flop 74LS375 chip in the first stage delay circuit, and the signal output terminal of the second D flip-flop 74LS375 chip is connected to the third stage. The signal input end of the extension circuit, the signal output end of the second edge type D flip-flop 74LS175 chip is connected to the signal input end of the phase detection module;

The third stage delay circuit is composed of the third edge type D flip-flop 74LS175 chip, the third D flip-flop 74LS375 chip and the fourth edge type D flip-flop 74LS175 chip, the third edge type D flip-flop 74LS175 chip and the third edge type D flip-flop 74LS175 chip. The signal input terminal of the three-D flip-flop 74LS375 chip, that is, the signal input terminal of the third-stage time delay circuit, is connected to the signal output terminal of the second D flip-flop 74LS375 chip in the second-stage time delay circuit, and the third D flip-flop 74LS375 The signal output terminal of the chip is connected to the signal input terminal of the fourth edge type D flip-flop 74LS175 chip, the signal output terminal of the third edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module, and the fourth edge type D flip-flop 74LS175 The signal output end of the chip is connected to the signal input end of the phase detection module.

The phase detection module is composed of a first pulse conversion circuit, a second pulse conversion circuit, a third pulse conversion circuit, a fourth pulse conversion circuit, a fifth pulse conversion circuit, a first phase coincidence detection circuit, and a second phase coincidence detection circuit. , the third phase coincidence detection circuit and the fourth phase coincidence detection circuit are composed;

The first pulse conversion circuit, the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit, and the fifth pulse conversion circuit all use pulse conversion circuits, and the pulse conversion circuit is composed of a pulse conversion D flip-flop. 74LS375 chip, pulse transformation logic AND gate circuit 74LS08D chip and pulse transformation logic NOT gate circuit 74LS04N chip. The D signal input terminal of the pulse transformation D flip-flop 74LS375 chip is connected to the pulse transformation logic AND gate circuit. The Q signal output end of the transform D flip-flop 74LS375 chip is connected to the signal input end of the pulse transform logic NOT circuit 74LS04N chip, and the signal output end of the pulse transform logic NOT circuit 74LS04N chip is connected to the pulse transform logic AND gate circuit The B signal input of the 74LS08D chip terminal, the signal output terminal Y of the pulse conversion logic AND gate circuit 74LS08D chip is used as the signal output terminal of the pulse conversion circuit;

The first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip. The A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B1 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected to the signal input end of the gate generating module;

The second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip. The A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The second logic The B2 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected to the signal input end of the gate generation module;

The third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip. The A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B3 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected to the signal input end of the gate generation module;

The fourth phase coincidence detection circuit is composed of a fourth logic AND gate circuit 74LS08D chip, the A4 signal input end of the fourth logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit, and the fourth logic The B4 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fifth pulse conversion circuit; the signal output end of the fourth phase coincidence detection circuit is connected to the signal input end of the gate generating module.

The gate generation module is composed of a programmable frequency divider, a three-input three-NOR gate circuit 74LS27N chip and a logic NOT gate circuit 74LS04N chip, and the signal output end of the programmable frequency divider is connected to the time interval measurement. The signal input terminal of the module, the signal input terminal of the three-input three-NOR gate circuit 74LS27N chip is respectively connected to the first phase coincidence detection circuit, the second phase coincidence detection circuit, the third phase coincidence detection circuit and the fourth phase coincidence detection circuit. The signal output end of the phase coincidence detection circuit, the signal output end of the input three-NOR gate circuit 74LS27N chip is connected to the signal input end of the logic NOT gate circuit 74LS04N chip, and the signal output end of the logic NOT gate circuit 74LS04N chip is connected to the described Signal input of the time interval measurement module.

The time interval measurement module adopts a programmable counter and is implemented by FPGA hardware description language programming; the FPGA adopts Cyclone IV chip EP4CE75.

The data processing module adopts the embedded single chip STM32F103RBT6 chip, and the display module can adopt the LCD liquid crystal display.

A high-precision frequency standard comparison method based on time-frequency information measurement, comprising the following steps:

Step A: Use the frequency standard pulse signal module and the measured pulse signal module to digitize the frequency standard signal and the measured frequency signal generated by the frequency standard module and the measured frequency module respectively, which will be generated by the 10MHz 5071A high-performance cesium atomic frequency standard. The frequency standard signal and the measured frequency signal generated by the crystal oscillator or the KDS rubidium atomic clock are converted into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with a duty cycle of 50% through the Schmitt trigger 74LS14N respectively;

Step B: sending the rectangular frequency standard pulse signal with a duty ratio of 50% into the adjustable time delay module for time delay to generate a time delay signal;

Specifically, the rectangular frequency standard pulse signal with a duty ratio of 50% is sent to the first-stage delay circuit, and the first fixed delay signal is generated by the first D flip-flop 74LS375 chip. The delay of the first fixed delay signal The amount is the clock cycle of the first D flip-flop 74LS375 chip, the first edge-type D flip-flop 74LS175 chip generates the first fine-tuning delay signal, and the delay amount of the first fine-tuning delay signal is the first edge-type D trigger The clock cycle of the 74LS175 chip of the controller, the delay amount of the first fixed delay signal is greater than the delay amount of the first fine-tuning delay signal;

The first fixed delay signal is sent to the second stage delay circuit, and the second fixed delay signal is generated by the second D flip-flop 74LS375 chip. The delay amount of the second fixed delay signal is the second D flip-flop 74LS375 The clock cycle of the chip is generated by the second edge-type D flip-flop 74LS175 chip to generate the second fine-tuning delay signal. The delay amount of the second fine-tuning delay signal is the clock cycle of the second edge-type D flip-flop 74LS175 chip. The delay amount of the fixed delay signal is greater than the delay amount of the second fine-tuning delay signal;

The second fixed delay signal is sent to the third stage delay circuit, and the third fixed delay signal is generated by the third D flip-flop 74LS375 chip. The delay amount of the third fixed delay signal is the third D flip-flop 74LS375 Clock cycle, the third trimming delay signal is generated by the third edge type D flip-flop 74LS175 chip, the delay amount of the third trimming delay signal is the clock cycle of the third edge type D flip-flop 74LS175 chip, the third fixed time The delay amount of the delay signal is greater than the delay amount of the third fine-tuning delay signal;

The third fixed time delay signal is sent to the fourth edge type D flip-flop 74LS175 chip to generate the fourth fine-tuning time delay signal. The delay amount of the fourth fine-tuning time delay signal is the clock cycle of the fourth edge type D flip-flop 74LS175 chip. , the delay amount of the third fixed delay signal is greater than the delay amount of the fourth fine-tuning delay signal;

Step C: The rectangular measured pulse signal with a duty cycle of 50% generated by the measured pulse signal module is sent to the first pulse conversion circuit to generate a rectangular measured pulse signal with a duty cycle of less than 10%. The delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal are respectively sent to the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit , respectively generating the first fine-tuning delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal after the pulse transformation;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed first fine-tuning delay signal into the first phase coincidence detection circuit to generate the first phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed second fine-tuning delay signal into the second phase coincidence detection circuit to generate the second phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed third fine-tuning delay signal into the third phase coincidence detection circuit to generate the third phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed fourth fine-tuning time delay signal into the fourth phase coincidence detection circuit to generate the fourth phase coincidence point pulse;

Step D: According to the frequency relationship between the frequency standard signal and the measured frequency signal, calculate the least common multiple of the frequency standard signal and the measured frequency signal, and use the least common multiple cycle as the time interval to generate a programmable frequency divider in the module by the gate Generate a reference gate signal;

The first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to the three-input three-NOR gate circuit 74LS27N chip in the gate generation module. The signal output end of the NOT gate circuit 74LS27N chip is connected to the signal input end of the logic NOT gate circuit 74LS04N chip. Under the control of the reference gate signal, the signal output end of the logic NOT gate circuit 74LS04N chip generates the actual gate signal of the time interval measurement module;

Step E: The rectangular frequency standard pulse signal with a duty ratio of 50% and the rectangular measured pulse signal are sent to the time interval measurement module at the same time. The time interval measurement module is composed of programmable counters. Count to obtain the count value of the rectangular frequency standard pulse signal and the rectangular measured pulse signal;

Step F: The count value of the programmable counter is sent to the data processing module, that is, the STM32F103RBT6 chip of the single-chip microcomputer for processing, and the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system are obtained.

Compared with the prior art, the beneficial effects of the present invention are:

The invention avoids the normalization processing of the frequency in the traditional frequency standard comparison method, uses the FPGA technology to simplify the system structure, reduces the cost, overcomes the influence of additional noise, and further strengthens the robustness of the system; Different from the adjustable delay chain technology of the traditional frequency standard comparison method, the influence of complex frequency relationship on the phase measurement accuracy is effectively eliminated, and the system response time and frequency accuracy of the present invention are greatly improved. The system response time is better than 1ms, and the frequency accuracy is better than ±6×10 ^-13 , which realizes fast and direct phase measurement of any frequency relationship in the radio frequency range, and speeds up the speed of frequency standard comparison.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

FIG. 1 is a principle block diagram of the present invention.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in Figure 1: a high-precision frequency standard comparison system based on time-frequency information measurement according to the present invention includes a frequency standard module, a measured frequency module, a frequency standard pulse signal module, a measured pulse signal module, a Time delay module, phase detection module, gate generation module, time interval measurement module, data processing module, display module and power supply module; frequency standard module, frequency standard pulse signal module, adjustable delay module, phase detection module, gate generation module The module, the time interval measurement module, the data processing module and the display module are connected in sequence, the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module, and the signal output end of the measured frequency module is connected with the measured pulse signal The signal input end of the module is connected, and the signal output end of the measured pulse signal module is connected with the signal input end of the phase detection module and the time interval measurement module;

The frequency standard module is used to generate a frequency standard signal with a frequency accuracy higher than ±1× ^10-12 magnitude; The frequency accuracy of the cesium atomic frequency standard is ±5E-13, which is used to generate a frequency standard signal with a frequency accuracy of the order of magnitude better than ±1×10 ^-12 ;

The measured frequency module is used to generate a comparison frequency signal with a frequency accuracy of less than ±1×10 ^-12 order of magnitude, that is, the measured frequency signal; preferably, the measured frequency module can use a crystal oscillator or The secondary frequency standard such as KDS rubidium atomic clock is used to generate a comparison frequency signal with a frequency accuracy of less than ±1×10 ^-12 , that is, the measured frequency signal;

The frequency standard pulse signal module and the measured pulse signal module are respectively used to generate a rectangular frequency standard pulse signal with a duty cycle of 50% and a rectangular measured pulse signal with a duty cycle of 50%; preferably, the described The frequency standard pulse signal module and the measured pulse signal module use the Schmitt contactor 74LS14N chip; that is, the frequency standard pulse signal module and the measured pulse signal module are used to compare the frequency standard module and the measured pulse signal module respectively. The frequency standard signal and the measured frequency signal generated by the measured frequency module are digitized;

The adjustable delay module is used to generate a fixed delay signal and a fine-tuning delay signal of the frequency standard signal; preferably, the adjustable delay module consists of a first-stage delay circuit and a second-stage delay circuit. It is composed of a third-stage delay circuit;

The first stage delay circuit is composed of a first edge type D flip-flop 74LS175 chip and a first D flip-flop 74LS375 chip, the first edge type D flip-flop 74LS175 chip and the signal input end of the first D flip-flop 74LS375 chip , that is, the signal input end of the first stage delay circuit is connected to the signal output end of the frequency standard pulse signal module, the signal output end of the first D flip-flop 74LS375 chip is connected to the signal input end of the second stage delay circuit, the first The signal output terminal of the edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module. Specifically, the signal output terminal of the first edge type D flip-flop 74LS175 chip is connected to the first phase detection module in the phase detection module. The signal input terminal of the coincidence detection circuit; the rectangular frequency standard pulse signal with a duty ratio of 50% is sent to the first-stage delay circuit, and the first fixed delay signal is generated by the first D flip-flop 74LS375 chip. The delay amount of the delay signal is the clock cycle of the first D flip-flop 74LS375. The first edge-type D flip-flop 74LS175 chip generates the first fine-tuning delay signal, and the delay amount of the first fine-tuning delay signal is the first edge. The clock cycle of the type D flip-flop 74LS175 chip, the delay amount of the first fixed delay signal is much larger than the delay amount of the first fine-tuning delay signal;

The second stage delay circuit is composed of a second edge type D flip-flop 74LS175 chip and a second D flip-flop 74LS375 chip, the second edge type D flip-flop 74LS175 chip and the signal input end of the second D flip-flop 74LS375 chip , that is, the signal input terminal of the second stage delay circuit is connected to the signal output terminal of the first D flip-flop 74LS375 chip in the first stage delay circuit, and the signal output terminal of the second D flip-flop 74LS375 chip is connected to the third stage. The signal input terminal of the delay circuit, the signal output terminal of the second edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module; specifically, the signal output terminal of the second edge type D flip-flop 74LS175 chip is connected to the The signal input terminal of the second phase coincidence detection circuit in the phase detection module described above; the first fixed time delay signal is sent to the second stage time delay circuit, and the second fixed time delay signal is generated by the second D flip-flop 74LS375 chip. The delay amount of the two fixed delay signals is the clock cycle of the second D flip-flop 74LS375, and the second fine-tuning delay signal is generated by the second edge-type D flip-flop 74LS175 chip. The delay amount of the second fine-tuning delay signal is In the clock cycle of the second edge type D flip-flop 74LS175 chip, the delay amount of the second fixed delay signal is much larger than the delay amount of the second fine-tuning delay signal;

The third stage delay circuit is composed of the third edge type D flip-flop 74LS175 chip, the third D flip-flop 74LS375 chip and the fourth edge type D flip-flop 74LS175 chip, the third edge type D flip-flop 74LS175 chip and the third edge type D flip-flop 74LS175 chip. The signal input terminal of the three-D flip-flop 74LS375 chip, that is, the signal input terminal of the third-stage time delay circuit, is connected to the signal output terminal of the second D flip-flop 74LS375 chip in the second-stage time delay circuit, and the third D flip-flop 74LS375 The signal output terminal of the chip is connected to the signal input terminal of the fourth edge type D flip-flop 74LS175 chip, and the signal output terminal of the third edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module. Specifically, the third edge type D flip-flop is connected to the signal input terminal of the phase detection module. The signal output terminal of the flip-flop 74LS175 chip is connected to the signal input terminal of the third phase coincidence detection circuit in the phase detection module; the signal output terminal of the fourth edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module. terminal; the second fixed delay signal is sent to the third stage delay circuit, and the third fixed delay signal is generated by the third D flip-flop 74LS375 chip, and the delay amount of the third fixed delay signal is the third D trigger 74LS375 clock cycle of the device, the third trimming delay signal is generated by the third edge type D flip-flop 74LS175 chip, the delay amount of the third trimming delay signal is the clock cycle of the third edge type D flip-flop 74LS175 chip, the third The delay amount of the fixed delay signal is much larger than that of the third fine-tuning delay signal; the third fixed-time delay signal is sent to the fourth edge-type D flip-flop 74LS175 chip to generate the fourth fine-tuning delay signal, and the fourth fine-tuning delay signal is generated. The delay amount of the delay signal is the clock cycle of the fourth edge type D flip-flop 74LS175 chip, and the delay amount of the third fixed delay signal is much larger than that of the fourth fine-tuned delay signal;

The phase detection module is used to generate the phase coincidence point pulse signal; A five-pulse conversion circuit, a first phase coincidence detection circuit, a second phase coincidence detection circuit, a third phase coincidence detection circuit and a fourth phase coincidence detection circuit are composed;

The first pulse conversion circuit, the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit, and the fifth pulse conversion circuit all use pulse conversion circuits, and the pulse conversion circuit is composed of a pulse conversion D flip-flop. 74LS375 chip, pulse transformation logic AND gate circuit 74LS08D chip and pulse transformation logic NOT gate circuit 74LS04N chip. The D signal input terminal of the pulse transformation D flip-flop 74LS375 chip is connected to the pulse transformation logic AND gate circuit. The Q signal output end of the transform D flip-flop 74LS375 chip is connected to the signal input end of the pulse transform logic NOT circuit 74LS04N chip, and the signal output end of the pulse transform logic NOT circuit 74LS04N chip is connected to the pulse transform logic AND gate circuit The B signal input of the 74LS08D chip terminal, the signal output terminal Y of the pulse conversion logic AND gate circuit 74LS08D chip is used as the signal output terminal of the pulse conversion circuit;

The first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip. The A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B1 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected to the signal input end of the gate generating module;

The second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip. The A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The second logic The B2 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected to the signal input end of the gate generation module;

The third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip. The A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B3 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected to the signal input end of the gate generation module;

The fourth phase coincidence detection circuit is composed of a fourth logic AND gate circuit 74LS08D chip, the A4 signal input end of the fourth logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit, and the fourth logic The B4 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fifth pulse conversion circuit; the signal output end of the fourth phase coincidence detection circuit is connected to the signal input end of the gate generation module;

The rectangular measured pulse signal with a duty cycle of 50% generated by the measured pulse signal module is sent to the first pulse conversion circuit to generate a rectangular measured pulse signal with a duty cycle of less than 10%, and the first fine-tuning delay signal , the second fine-tuning time delay signal, the third fine-tuning time delay signal and the fourth fine-tuning time delay signal are respectively sent to the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit to generate The first fine-tuning delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal after the pulse transformation;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed first fine-tuning delay signal into the first phase coincidence detection circuit to generate the first phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed second fine-tuning delay signal into the second phase coincidence detection circuit to generate the second phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed third fine-tuning delay signal into the third phase coincidence detection circuit to generate the third phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed fourth fine-tuning time delay signal into the fourth phase coincidence detection circuit to generate the fourth phase coincidence point pulse;

The gate generation module is used to generate the reference gate time interval and the actual gate switch signal; specifically, the gate generation module is composed of a programmable frequency divider, a three-input three-NOR gate circuit 74LS27N chip and a logic NOT gate circuit 74LS04N. It is composed of chips, the signal output end of the programmable frequency divider is connected to the signal input end of the time interval measurement module, and the signal input end of the three-input three-NOR gate circuit 74LS27N chip is respectively connected to the first A signal output terminal of the phase coincidence detection circuit, the second phase coincidence detection circuit, the third phase coincidence detection circuit and the fourth phase coincidence detection circuit, the signal output terminal of the input three-NOR gate circuit 74LS27N chip is connected to the logic NOT gate circuit 74LS04N chip The signal input end of the logic NOT gate circuit 74LS04N chip is connected to the signal input end of the time interval measurement module; according to the frequency relationship between the frequency standard signal and the measured frequency signal, the frequency standard signal is calculated. and the least common multiple of the measured frequency signal, with the least common multiple period as the time interval, the programmable frequency divider in the gate generation module generates the reference gate signal; the first phase coincidence point pulse, the second phase coincidence point pulse, the third The phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to the three-input three-NOR gate circuit 74LS27N chip in the gate generation module, and the signal output terminal of the three-input three-NOR gate circuit 74LS27N chip is connected to the logic NOT gate circuit 74LS04N chip. Signal input terminal, under the control of the reference gate signal, the signal output terminal of the logic NOT gate circuit 74LS04N chip generates the actual gate signal of the time interval measurement module;

The time interval measurement module is used to generate the count value of the frequency standard signal and the measured frequency signal; specifically, the time interval measurement module adopts a programmable counter, which is implemented by FPGA hardware description language programming; the FPGA adopts a programmable counter. Cyclone IV chip EP4CE75, and EP4CE75 FPGA can also realize the logic function of programmable frequency divider and 74LS series chips;

The data processing module is used to process the count value of the frequency standard signal and the measured frequency signal to generate the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system; the display module is used to receive data processing The processing result of the module is displayed; specifically, the data processing module adopts the embedded single chip STM32F103RBT6 chip, and the display module can adopt the LCD liquid crystal display.

A high-precision frequency standard comparison method based on time-frequency information measurement performed by the above-mentioned high-precision frequency standard comparison system based on time-frequency information measurement includes the following steps:

Step A: Use the frequency standard pulse signal module and the measured pulse signal module to digitize the frequency standard signal and the measured frequency signal generated by the frequency standard module and the measured frequency module respectively, which will be generated by the 10MHz 5071A high-performance cesium atomic frequency standard. The frequency standard signal and the measured frequency signal generated by the crystal oscillator or the KDS rubidium atomic clock are converted into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with a duty cycle of 50% through the Schmitt trigger 74LS14N respectively;

Step B: sending the rectangular frequency standard pulse signal with a duty ratio of 50% into the adjustable time delay module for time delay to generate a time delay signal;

Specifically, the rectangular frequency standard pulse signal with a duty ratio of 50% is sent to the first-stage delay circuit, and the first fixed delay signal is generated by the first D flip-flop 74LS375 chip. The delay of the first fixed delay signal The amount is the clock cycle of the first D flip-flop 74LS375 chip, the first edge-type D flip-flop 74LS175 chip generates the first fine-tuning delay signal, and the delay amount of the first fine-tuning delay signal is the first edge-type D trigger The clock cycle of the 74LS175 chip of the controller, the delay amount of the first fixed delay signal is greater than the delay amount of the first fine-tuning delay signal;

The first fixed delay signal is sent to the second stage delay circuit, and the second fixed delay signal is generated by the second D flip-flop 74LS375 chip. The delay amount of the second fixed delay signal is the second D flip-flop 74LS375 The clock cycle of the chip is generated by the second edge-type D flip-flop 74LS175 chip to generate the second fine-tuning delay signal. The delay amount of the second fine-tuning delay signal is the clock cycle of the second edge-type D flip-flop 74LS175 chip. The delay amount of the fixed delay signal is greater than the delay amount of the second fine-tuning delay signal;

The second fixed delay signal is sent to the third stage delay circuit, and the third fixed delay signal is generated by the third D flip-flop 74LS375 chip. The delay amount of the third fixed delay signal is the third D flip-flop 74LS375 Clock cycle, the third trimming delay signal is generated by the third edge type D flip-flop 74LS175 chip, the delay amount of the third trimming delay signal is the clock cycle of the third edge type D flip-flop 74LS175 chip, the third fixed time The delay amount of the delay signal is greater than the delay amount of the third fine-tuning delay signal;

The third fixed time delay signal is sent to the fourth edge type D flip-flop 74LS175 chip to generate the fourth fine-tuning time delay signal. The delay amount of the fourth fine-tuning time delay signal is the clock cycle of the fourth edge type D flip-flop 74LS175 chip. , the delay amount of the third fixed delay signal is greater than the delay amount of the fourth fine-tuning delay signal;

Step C: The rectangular measured pulse signal with a duty cycle of 50% generated by the measured pulse signal module is sent to the first pulse conversion circuit to generate a rectangular measured pulse signal with a duty cycle of less than 10%. The delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal are respectively sent to the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit , respectively generating the first fine-tuning delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal after the pulse transformation;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed first fine-tuning delay signal into the first phase coincidence detection circuit to generate the first phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed second fine-tuning delay signal into the second phase coincidence detection circuit to generate the second phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed third fine-tuning delay signal into the third phase coincidence detection circuit to generate the third phase coincidence point pulse;

Sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed fourth fine-tuning time delay signal into the fourth phase coincidence detection circuit to generate the fourth phase coincidence point pulse;

Step D: According to the frequency relationship between the frequency standard signal and the measured frequency signal, calculate the least common multiple of the frequency standard signal and the measured frequency signal, and use the least common multiple cycle as the time interval to generate a programmable frequency divider in the module by the gate Generate a reference gate signal;

The first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to the three-input three-NOR gate circuit 74LS27N chip in the gate generation module. The signal output end of the NOT gate circuit 74LS27N chip is connected to the signal input end of the logic NOT gate circuit 74LS04N chip. Under the control of the reference gate signal, the signal output end of the logic NOT gate circuit 74LS04N chip generates the actual gate signal of the time interval measurement module;

Step E: The rectangular frequency standard pulse signal with a duty ratio of 50% and the rectangular measured pulse signal are sent to the time interval measurement module at the same time. The time interval measurement module is composed of programmable counters. Count to obtain the count value of the rectangular frequency standard pulse signal and the rectangular measured pulse signal;

Step F: The count value of the programmable counter is sent to the data processing module, that is, the STM32F103RBT6 chip of the single-chip microcomputer for processing, and the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system are obtained.

Compared with the prior art, the high-precision frequency standard comparison system and comparison method based on time-frequency information measurement of the present invention has the following beneficial effects:

The invention avoids the normalization processing of the frequency in the traditional frequency standard comparison method, uses the FPGA technology to simplify the system structure, reduces the cost, overcomes the influence of additional noise, and further strengthens the robustness of the system; Different from the adjustable delay chain technology of the traditional frequency standard comparison method, the influence of complex frequency relationship on the phase measurement accuracy is effectively eliminated, and the system response time and frequency accuracy of the present invention are greatly improved. The system response time is better than 1ms, and the frequency accuracy is better than ±6×10 ^-13 , which realizes fast and direct phase measurement of any frequency relationship in the radio frequency range, and speeds up the speed of frequency standard comparison.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. a high-precision frequency standard comparison system based on time-frequency information measurement, is characterized in that: comprise frequency standard module, measured frequency module, frequency standard pulse signal module, measured pulse signal module, adjustable time delay module, Phase detection module, gate generation module, time interval measurement module, data processing module, display module and power supply module; frequency standard module, frequency standard pulse signal module, adjustable delay module, phase detection module, gate generation module, time interval measurement The module, the data processing module and the display module are connected in sequence, the signal output end of the frequency standard pulse signal module is also connected with the signal input end of the time interval measurement module, the signal output end of the measured frequency module is connected with the signal input end of the measured pulse signal module connection, the signal output end of the measured pulse signal module is connected with the signal input end of the phase detection module and the time interval measurement module; The frequency standard module is used to generate a frequency standard signal with a frequency accuracy higher than ±1×10 ^-12 magnitude; The measured frequency module is used to generate a comparison frequency signal whose frequency accuracy is lower than ±1×10 ^-12 magnitude, that is, the measured frequency signal; The frequency standard pulse signal module and the measured pulse signal module are respectively used to generate a rectangular frequency standard pulse signal with a duty ratio of 50% and a rectangular measured pulse signal with a duty ratio of 50%; The adjustable time delay module is used for generating the fixed time delay signal and the fine-tuning time delay signal of the frequency standard signal; The phase detection module is used to generate the phase coincidence point pulse signal; The gate generation module is used to generate the reference gate time interval and the actual gate switch signal; The time interval measurement module is used to generate the count value of the frequency standard signal and the measured frequency signal; The data processing module is used to process the frequency standard signal and the count value of the measured frequency signal to generate the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system; The display module is used for receiving and displaying the processing result of the data processing module. 2. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 1, is characterized in that: described frequency standard module adopts 10MHz 5071A high-performance cesium atomic frequency standard, and the frequency accuracy is ± 5×10 ^-13 . 3. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 2, is characterized in that: described measured frequency module adopts crystal oscillator or KDS rubidium atomic clock, and the frequency accuracy is lower than On the order of ±1× ^10-12 . 4. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 3, is characterized in that: described frequency standard pulse signal module and measured pulse signal module all adopt Schmitt contactor 74LS14N chip. 5. A high-precision frequency standard comparison system based on time-frequency information measurement according to claim 4, wherein the adjustable delay module is composed of a first-stage delay circuit, a second-stage delay The circuit and the third-stage delay circuit are composed; The first stage delay circuit is composed of a first edge type D flip-flop 74LS175 chip and a first D flip-flop 74LS375 chip, the first edge type D flip-flop 74LS175 chip and the signal input end of the first D flip-flop 74LS375 chip , that is, the signal input end of the first stage delay circuit is connected to the signal output end of the frequency standard pulse signal module, the signal output end of the first D flip-flop 74LS375 chip is connected to the signal input end of the second stage delay circuit, the first The signal output end of the edge type D flip-flop 74LS175 chip is connected to the signal input end of the phase detection module; The second stage delay circuit is composed of a second edge type D flip-flop 74LS175 chip and a second D flip-flop 74LS375 chip, the second edge type D flip-flop 74LS175 chip and the signal input end of the second D flip-flop 74LS375 chip , that is, the signal input terminal of the second stage delay circuit is connected to the signal output terminal of the first D flip-flop 74LS375 chip in the first stage delay circuit, and the signal output terminal of the second D flip-flop 74LS375 chip is connected to the third stage. The signal input end of the extension circuit, the signal output end of the second edge type D flip-flop 74LS175 chip is connected to the signal input end of the phase detection module; The third stage delay circuit is composed of the third edge type D flip-flop 74LS175 chip, the third D flip-flop 74LS375 chip and the fourth edge type D flip-flop 74LS175 chip, the third edge type D flip-flop 74LS175 chip and the third edge type D flip-flop 74LS175 chip. The signal input terminal of the three-D flip-flop 74LS375 chip, that is, the signal input terminal of the third-stage time delay circuit, is connected to the signal output terminal of the second D flip-flop 74LS375 chip in the second-stage time delay circuit, and the third D flip-flop 74LS375 The signal output terminal of the chip is connected to the signal input terminal of the fourth edge type D flip-flop 74LS175 chip, the signal output terminal of the third edge type D flip-flop 74LS175 chip is connected to the signal input terminal of the phase detection module, and the fourth edge type D flip-flop 74LS175 The signal output end of the chip is connected to the signal input end of the phase detection module. 6. A high-precision frequency standard comparison system based on time-frequency information measurement according to claim 5, characterized in that: the phase detection module is composed of a first pulse conversion circuit, a second pulse conversion circuit, a third Pulse transformation circuit, fourth pulse transformation circuit, fifth pulse transformation circuit, first phase coincidence detection circuit, second phase coincidence detection circuit, third phase coincidence detection circuit and fourth phase coincidence detection circuit; The first pulse conversion circuit, the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit, and the fifth pulse conversion circuit all use pulse conversion circuits, and the pulse conversion circuit is composed of a pulse conversion D flip-flop. 74LS375 chip, pulse transformation logic AND gate circuit 74LS08D chip and pulse transformation logic NOT circuit 74LS04N chip, the D signal input terminal of pulse transformation D flip-flop 74LS375 chip is used as the input terminal of the pulse transformation circuit to connect the pulse transformation logic AND gate The A signal input end of the circuit 74LS08D chip, the Q signal output end of the pulse transform D flip-flop 74LS375 chip is connected to the signal input end of the pulse transform logic NOT circuit 74LS04N chip, and the pulse transform logic NOT gate The signal output end of the 74LS04N chip is connected to the pulse transform The B signal input terminal of the logic AND gate circuit 74LS08D chip, the signal output terminal Y of the pulse conversion logic AND gate circuit 74LS08D chip is used as the signal output terminal of the pulse conversion circuit; The first phase coincidence detection circuit is composed of a first logic AND gate circuit 74LS08D chip. The A1 signal input end of the first logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B1 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the second pulse conversion circuit; the signal output end of the first phase coincidence detection circuit is connected to the signal input end of the gate generating module; The second phase coincidence detection circuit is composed of a second logic AND gate circuit 74LS08D chip. The A2 signal input end of the second logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The second logic The B2 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the third pulse conversion circuit; the signal output end of the second phase coincidence detection circuit is connected to the signal input end of the gate generation module; The third phase coincidence detection circuit is composed of a third logic AND gate circuit 74LS08D chip. The A3 signal input end of the third logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit. The B3 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fourth pulse conversion circuit; the signal output end of the third phase coincidence detection circuit is connected to the signal input end of the gate generation module; The fourth phase coincidence detection circuit is composed of a fourth logic AND gate circuit 74LS08D chip, the A4 signal input end of the fourth logic AND gate circuit 74LS08D chip is connected to the signal output end of the first pulse conversion circuit, and the fourth logic The B4 signal input end of the AND gate circuit 74LS08D chip is connected to the signal output end of the fifth pulse conversion circuit; the signal output end of the fourth phase coincidence detection circuit is connected to the signal input end of the gate generating module. 7. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 6, is characterized in that: described gate generation module is composed of programmable frequency divider, three-input three-NOR gate circuit 74LS27N The chip is composed of a logic NOT gate circuit 74LS04N chip, the signal output end of the programmable frequency divider is connected to the signal input end of the time interval measurement module, and the signal input end of the three-input three-NOR gate circuit 74LS27N chip is connected. The terminals are respectively connected to the signal output terminals of the first phase coincidence detection circuit, the second phase coincidence detection circuit, the third phase coincidence detection circuit and the fourth phase coincidence detection circuit, and the signal output of the three-input three-NOR gate circuit 74LS27N chip The terminal is connected to the signal input terminal of the logic NOT gate circuit 74LS04N chip, and the signal output terminal of the logic NOT gate circuit 74LS04N chip is connected to the signal input terminal of the time interval measurement module. 8. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 7, is characterized in that: described time interval measurement module adopts programmable counter, is realized by FPGA hardware description language programming; The described FPGA adopts Cyclone IV chip EP4CE75. 9. a kind of high-precision frequency standard comparison system based on time-frequency information measurement according to claim 8, is characterized in that: described data processing module adopts embedded single chip STM32F103RBT6 chip, described display module can adopt LCD LCD Monitor. 10. A kind of high-precision frequency standard comparison method based on time-frequency information measurement carried out by the high-precision frequency standard comparison system based on time-frequency information measurement according to claim 9, it is characterized in that comprising: The following steps: Step A: Use the frequency standard pulse signal module and the measured pulse signal module to digitize the frequency standard signal and the measured frequency signal generated by the frequency standard module and the measured frequency module respectively, which will be generated by the 10MHz 5071A high-performance cesium atomic frequency standard. The frequency standard signal and the measured frequency signal generated by the crystal oscillator or the KDS rubidium atomic clock are converted into a rectangular frequency standard pulse signal and a rectangular measured pulse signal with a duty cycle of 50% through the Schmitt trigger 74LS14N respectively; Step B: sending the rectangular frequency standard pulse signal with a duty cycle of 50% into the adjustable time delay module for time delay to generate a time delay signal; Specifically, the rectangular frequency standard pulse signal with a duty ratio of 50% is sent to the first-stage delay circuit, and the first fixed delay signal is generated by the first D flip-flop 74LS375 chip. The delay of the first fixed delay signal The amount is the clock cycle of the first D flip-flop 74LS375 chip, the first edge-type D flip-flop 74LS175 chip generates the first fine-tuning delay signal, and the delay amount of the first fine-tuning delay signal is the first edge-type D trigger The clock cycle of the 74LS175 chip of the controller, the delay amount of the first fixed delay signal is greater than the delay amount of the first fine-tuning delay signal; The first fixed delay signal is sent to the second stage delay circuit, and the second fixed delay signal is generated by the second D flip-flop 74LS375 chip. The delay amount of the second fixed delay signal is the second D flip-flop 74LS375 The clock cycle of the chip is generated by the second edge-type D flip-flop 74LS175 chip to generate the second fine-tuning delay signal. The delay amount of the second fine-tuning delay signal is the clock cycle of the second edge-type D flip-flop 74LS175 chip. The delay amount of the fixed delay signal is greater than the delay amount of the second fine-tuning delay signal; The second fixed delay signal is sent to the third stage delay circuit, and the third fixed delay signal is generated by the third D flip-flop 74LS375 chip. The delay amount of the third fixed delay signal is the third D flip-flop 74LS375 Clock cycle, the third trimming delay signal is generated by the third edge type D flip-flop 74LS175 chip, the delay amount of the third trimming delay signal is the clock cycle of the third edge type D flip-flop 74LS175 chip, the third fixed time The delay amount of the delay signal is greater than the delay amount of the third fine-tuning delay signal; The third fixed time delay signal is sent to the fourth edge type D flip-flop 74LS175 chip to generate the fourth fine-tuning time delay signal. The delay amount of the fourth fine-tuning time delay signal is the clock cycle of the fourth edge type D flip-flop 74LS175 chip. , the delay amount of the third fixed delay signal is greater than the delay amount of the fourth fine-tuning delay signal; Step C: The rectangular measured pulse signal with a duty cycle of 50% generated by the measured pulse signal module is sent to the first pulse conversion circuit to generate a rectangular measured pulse signal with a duty cycle of less than 10%. The delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal are respectively sent to the second pulse conversion circuit, the third pulse conversion circuit, the fourth pulse conversion circuit and the fifth pulse conversion circuit , respectively generating the first fine-tuning delay signal, the second fine-tuning delay signal, the third fine-tuning delay signal and the fourth fine-tuning delay signal after the pulse transformation; sending the rectangular measured pulse signal with a duty ratio lower than 10% and the pulse-transformed first fine-tuning delay signal into the first phase coincidence detection circuit to generate the first phase coincidence point pulse; Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed second fine-tuning delay signal into the second phase coincidence detection circuit to generate the second phase coincidence point pulse; Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed third fine-tuning delay signal into the third phase coincidence detection circuit to generate the third phase coincidence point pulse; Sending the rectangular measured pulse signal with a duty ratio below 10% and the pulse-transformed fourth fine-tuning delay signal into the fourth phase coincidence detection circuit to generate the fourth phase coincidence point pulse; Step D: According to the frequency relationship between the frequency standard signal and the measured frequency signal, calculate the least common multiple of the frequency standard signal and the measured frequency signal, and use the least common multiple cycle as the time interval to generate a programmable frequency divider in the module by the gate Generate a reference gate signal; The first phase coincidence point pulse, the second phase coincidence point pulse, the third phase coincidence point pulse and the fourth phase coincidence point pulse are simultaneously sent to the three-input three-NOR gate circuit 74LS27N chip in the gate generation module. The signal output end of the NOT gate circuit 74LS27N chip is connected to the signal input end of the logic NOT gate circuit 74LS04N chip. Under the control of the reference gate signal, the signal output end of the logic NOT gate circuit 74LS04N chip generates the actual gate signal of the time interval measurement module; Step E: The rectangular frequency standard pulse signal with a duty ratio of 50% and the rectangular measured pulse signal are sent to the time interval measurement module at the same time. The time interval measurement module is composed of programmable counters. Count to obtain the count value of the rectangular frequency standard pulse signal and the rectangular measured pulse signal; Step F: The count value of the programmable counter is sent to the data processing module, that is, the STM32F103RBT6 chip of the single-chip microcomputer for processing, and the actual gate time, the frequency of the measured frequency signal and the frequency stability of the system are obtained.

Images