CN202120623U - Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 - Google Patents

Abstract

The utility model discloses an embedded static random access memory (SRAM) testing structure based on the institute of electrical and electronic engineers (IEEE) 1500, which is formed by an embedded SRAM testing shell packaging and an SRAM testing controller. The testing packaging shell solves the problem of testing access, testing separation and testing control of the embedded SRAM. The SRAM testing controller generates testing inspiring data according to testing algorithms, controls the packaging shell wrapper, carries out a response analysis and outputs testing results. By utilizing the testing structure and the testing method, the embedded SRAM testing structure can test the bugs existing in the embedded SRAM, thereby facilitating the test and reuse of the SRAM, and being capable of effectively improving the integration efficiency of a system on chip (SoC).

Description

Test Structure of Embedded SRAM Memory Based on IEEE 1500

technical field

The utility model relates to a test structure of an embedded SRAM in a SoC chip.

Background technique

Most of the currently known embedded SRAM tests adopt the built-in self-test method, which can realize the detection of memory faults, but the existing methods cannot effectively solve the test multiplexing problem of the embedded SRAM. Because there is no standardized and unified test structure, different SoC designers have different specific structures for SRAM built-in self-test, and the design efficiency of the system is greatly affected.

Contents of the invention

The utility model aims at the deficiencies of the prior art, on the basis of fully studying the IEEE 1500 standard and the built-in self-test (BIST), proposes a test structure of the SRAM type memory in the SoC that can be used for test multiplexing.

The basic structure of the embedded SRAM test based on the IEEE 1500 standard includes: access, control and isolation (as shown in Figure 1). The test access mechanism refers to applying a test excitation signal from the input end of the embedded SRAM, and getting a test response from the output end of the embedded SRAM. Control in embedded SRAM testing refers to the module that starts and stops the test function. Isolation refers to the electrical separation of the input and output ports of the embedded SRAM from the chip circuit or other cores connected to these ports, so as to avoid the side effects of the test on other cores or user-defined logic, and also protect the core. Adjacent circuits are not affected when tested. The main components are briefly described as follows:

A. Test source and test collection, the function of the test source is to provide the test core with the stimulus needed for testing, and the function of the test collection is to obtain the test response of the test core. The detection results are judged by comparing the test source data with the test collection data.

B. Test access mechanism, the function of the test access mechanism is to transmit test data, including transmitting the test stimulus from the test source to the test core, and at the same time transmitting the test response of the test core from the test shell to the test collection;

C. The test shell, the test shell is an interface between the test core and the peripheral circuits of the core. It mainly plays the role of switching between the tested core and the test access mechanism and other circuits. Only through the test shell, the test access mechanism and other parts can access the embedded The internals of the SRAM test core.

Based on the above-mentioned basic principle structure, the utility model provides a test structure based on the IEEE 1500 SoC embedded SRAM memory, including a BIST test controller and a test shell based on the IEEE 1500 standard packaged by the embedded SRAM. The test shell receives the control signal, instruction signal, test address data, and test stimulus data sent by the BIST test controller, and outputs the test response data to the BIST test controller; the test shell Wrapper surrounds the embedded SRAM under test, and the test shell Wrapper Each constituent unit conforms to the IEEE 1500 standard functional description.

The test shell Wrapper surrounds the embedded SRAM to be tested, and solves testing problems such as test access, test control and observation mechanism of the embedded SoC. The test shell mainly includes 5 parts: boundary register WBR, bypass register WBY, instruction register WIR, serial access interface WSI and WSO, control interface WIP. in:

WBR provides the access path for test data to enter the I/O port inside the embedded SRAM from the Wrapper interface, and WBR is used to respond to the relevant instructions of WIR. The operation of WBR includes functions such as shift, capture and update, which can realize the isolation of embedded SRAM, and test the controllability of core input and the observability of output. According to the operation to be completed by WBR, WBR is composed of the following data ports: function input port FI, function output port FO, test input port TI, test output port TO.

The BIST test controller mainly includes functional modules for completing control logic, test data generation, and test response analysis. The control logic is used to start and stop the test, and to control and manage the interface WIP of the Wrapper. The test data generation includes address, read and write, and test stimulus data and input them to the test shell Wrapper. The test response analysis collects the test response. Analyze the results and judge whether there is a fault in the SRAM; the test controller includes an algorithm state machine module, an instruction data module, a read and write signal module, an address data module, an input cache module, an output cache module, a control signal module, and a result comparison module; the algorithm state The computer module is connected with the command data module, read-write signal module, address data module, control signal module, and result comparison module, and controls its working status. The read-write signal module is connected with the output cache module, and controls the read-write status of the output cache module. The instruction data module is connected with the output cache module, and the test command is output to the test shell through the output cache module, and the address data module is connected with the output cache module, and the test address data generated by the address data module is output to the test shell through the output cache module, and the data background module and The output buffer module is connected, and the test stimulus data and instruction signals generated by the data background module are output to the test case through the output buffer module. The data output terminal WSO of the output buffer module is connected to the data input terminal WSI of the test case, and the control signal module is connected to the test case. , the output control signal, the data input terminal WSI of the input buffer module is connected with the data output terminal WSO of the test shell, receives the test response signal, the input buffer module is connected with the result comparison module, and outputs the received test response data to the result comparator, The data background module is connected with the result comparison module, and outputs the generated test stimulus data to the result comparison module. The result comparison module compares the test stimulus data with the test response data, and outputs the comparison result.

The work process of embedded SRAM memory test structure in the SoC based on IEEE 1500 of the present utility model is:

A． Select the working mode, select the working mode according to the state mode selection signal, if the value is 00, the embedded SRAM works in the normal mode; if the value is 01, the embedded SRAM works in the bypass mode; if the value is 11, the embedded SRAM Type SRAM works in test mode;

B． When the start signal is 1, the SRAM fault detection is started;

C． The BIST test controller generates test stimulus data according to the test algorithm, and sends the test stimulus data to the SRAM through the test shell Wrapper.

D． The test controller obtains the test response data returned from the SRAM through the test shell Wrapper;

E． The test controller compares the test stimulus data with the test response data to obtain a comparison result;

F． If the comparison result is that the test stimulus data is different from the test response data, an error will be reported and the test will end; if they are equal, steps C, D, and E will be repeated according to the test algorithm until the test is completed.

The machines and equipment used to design the embedded SRAM test structure include computers, oscilloscopes, logic analyzers, FPGA development boards, etc., which are prior art.

Taking embedded SRAM as the test object, the function verification of the test structure is carried out, and the verification results are shown in Table 1. The verification results show that the embedded SRAM test structure based on IEEE 1500 can accurately detect the faults in the memory, and the standardized test structure of SRAM can realize the test multiplexing of the memory and improve the efficiency of SoC integration and testing.

Table 1: Contents and results of IEEE 1500-based embedded SRAM memory verification

serial number verify content Validation results 1 normal mode pass 3 no trouble pass 4 sluggish 1 glitch pass 5 sluggish 0 failure pass 6 address decoding failure pass 7 conversion failure pass 8 bridging failure pass

Advantage one of the utility model is that each component unit in the Wrapper is designed according to the functional description in the IEEE 1500 standard, which solves the test access, test isolation and test control problems of the embedded SRAM. Due to the standardization of Wrapper, different types of embedded SRAMs are isomorphic from the perspective of test integration, so that all SRAM tests can be tested with the same method, and the reuse of test structures is realized. The second is to design the corresponding BIST test controller, which generates test stimulus data according to the test algorithm, controls the package Wrapper, performs response analysis, and outputs test results. By applying the test structure and the test method, it is possible to detect faults in the embedded SRAM memory, which is beneficial to the test multiplexing of the embedded SRAM memory, and can effectively improve the integration efficiency of the SoC.

It can be known from the above that different types of embedded SRAM memories in the SoC can be packaged according to the package example of the SRAM test case in the present invention. In this way, users of SoC memory will be more convenient when testing, and test integration and test reuse will be more effective. When testing different types of embedded SRAM memories, it is only necessary to change the test algorithm without changing the interface functions of the Wrapper and the controller. The Wrapper and SRAM test controller packaged by the embedded SRAM can easily complete the fault test of different types of SRAM, which is conducive to the standardization of the memory test structure and the test reuse of the memory core.

Description of drawings

Fig. 1 is a schematic diagram of the basic principle of the utility model embedded SRAM test;

Fig. 2 is the connection schematic diagram of the embedded SRAM memory test structure of the utility model based on IEEE 1500;

Fig. 3 is a schematic structural diagram of the utility model SRAM package test shell Wrapper;

Fig. 4 is a structural schematic diagram of the BIST test controller of the present invention.

Detailed ways

The specific implementation of the present utility model will be described in detail below in conjunction with the accompanying drawings and examples.

As shown in Figure 2, an IEEE 1500-based embedded SRAM memory test structure, including a BIST test controller and an embedded SRAM package based on IEEE 1500 standard test shell, the test shell receives the control signal sent by the BIST test controller , command signal, test address data, test stimulus data, and output the test response data to the BIST test controller, the test shell Wrapper surrounds the tested embedded SRAM, and each component unit in the test shell conforms to the IEEE 1500 standard function description; BIST The test controller has a clock signal, a state mode control signal port, and the test controller’s control signal output port to the test shell Wrapper is connected to the corresponding port of the test shell; the data output port WSO of the test shell is connected to the data receiving port of the test shell ; The data input port WSI of the test shell is connected to the data output port of the test shell.

As shown in Figure 3, described test shell Wrapper comprises: boundary register WBR, bypass register WBY, instruction register WIR, control interface WIP, data input port WSI, data output port WSO etc.; Group, the parallel output terminals of a group of WBR_in are respectively connected to the data input terminal of SRAM, the address data input terminal, and the input terminal of the read and write enable signal, and the parallel input terminals of another group of WBR_out are connected to the data output terminal of SARM, and the boundary register The WBR control signal terminal is connected to the command register WIR, and the control signal output terminal of the control interface WIP is connected to the command register WIR. The bypass register WBY is connected between the WSI and the WSO, providing a bypass path so that the test data can quickly pass through the test shell, which can effectively shorten the scanning path.

As shown in Figure 4, described BIST test controller comprises: algorithm state machine module, instruction data module, read and write signal module, address data module, input buffer module, output buffer module, control signal module, result comparison module; Algorithm state The computer module is connected with the command data module, read-write signal module, address data module, control signal module, and result comparison module, and controls its working status. The read-write signal module is connected with the output cache module, and controls the read-write status of the output cache module. The instruction data module is connected with the output cache module, and the test command is output to the test shell through the output cache module, and the address data module is connected with the output cache module, and the test address data generated by the address data module is output to the test shell through the output cache module, and the data background module and The output buffer module is connected, and the test stimulus data and instruction signals generated by the data background module are output to the test case through the output buffer module. The data output terminal WSO of the output buffer module is connected to the data input terminal WSI of the test case, and the control signal module is connected to the test case. , the output control signal, the data input terminal WSI of the input buffer module is connected with the data output terminal WSO of the test shell, receives the test response signal, the input buffer module is connected with the result comparison module, and outputs the received test response data to the result comparator, The data background module is connected with the result comparison module, and outputs the generated test stimulus data to the result comparison module. The result comparison module compares the test stimulus data with the test response data, and outputs the comparison result.

According to Fig. 2, Fig. 3 and Fig. 4, a kind of embedded SRAM memory test method based on IEEE 1500 standard, under the control of the algorithm state machine module, its working process is as follows:

A． Select the working mode, select the working mode according to the state mode selection signal, if the value is 00, the embedded SRAM works in the normal mode; if the value is 01, the embedded SRAM works in the bypass mode; if the value is 11, the embedded SRAM Type SRAM works in test mode;

B． When the start signal is 1, the SRAM fault detection is started;

C． The BIST test controller generates test stimulus data according to the test algorithm, and sends the test stimulus data to the SRAM through the test shell Wrapper.

D． The test controller obtains the test response data returned from the SRAM through the test shell Wrapper;

E． The test controller compares the test stimulus data with the test response data to obtain a comparison result;

F． If the comparison result is that the test stimulus data is different from the test response data, an error will be reported and the test will end; if they are equal, steps C, D, and E will be repeated according to the test algorithm until the test is completed.

Preferably, the steps of instruction signal generation, transmission, and instruction decoding: the instruction data module is controlled by the algorithm state machine module to generate instruction data, the instruction data is sent to the output buffer module, and the output buffer module sends the instruction data to the instruction register, and the instruction register Instruction decoding is performed on the instruction data to generate an instruction signal; the instruction signal controls the test shell to receive the test stimulus data, address data, and SRAM read and write signals sent by the test controller, and controls the test shell to transmit the test response data generated by the SRAM to the Test the controller.

Preferably, the steps of address data generation and transmission: the address data generation module generates address data, the address data is sent to the output buffer module, the output buffer module sends the address data serially into the boundary register through the buffer, and the boundary register sends the address data to into SRAM.

Preferably, the steps of test stimulus data generation and transmission: the test stimulus data is generated by the data background module, the test stimulus data is sent to the output buffer module, and the output cache module sends the test stimulus data serially to the boundary register through the buffer, and the boundary register Send test stimulus data into SRAM.

Preferably, the step of obtaining and transmitting the test response data is included: the test response data generated in the SRAM is transmitted to the input buffer module through the buffer, and the result comparison module obtains the test response number from the input buffer.

Preferably, the step of bypass register work is included: when the current embedded SRAM does not need to be tested, the values of BIST test controller Mode0 and Mode1 are 01, the embedded SRAM is in bypass mode, and the test generated by the BIST controller The data no longer passes through WBR, and the test data chooses WBY as the passing path.

Claims (5)

1. the embedded SRAM memory test structure based on IEEE 1500 comprises the BIST test controller, it is characterized in that: the test shell Wrapper based on IEEE 1500 standards that also comprises the embedded SRAM encapsulation; Said test shell joint is received control signal, command signal, test address data, the test stimulus data that the BIST test controller is sent here; And test response data outputed to the BIST test controller; Test shell Wrapper is round tested embedded SRAM, and each component units in the test shell meets IEEE 1500 standard features to be described.

2. a kind of embedded SRAM memory test structure according to claim 1 based on IEEE 1500, it is characterized in that: said test shell Wrapper comprises: boundary register WBR, bypass register WBY, order register WIR, control interface WIP, data-in port WSI, data-out port WSO etc.; Respectively be divided into two groups on the boundary register WBR; The parallel output terminal of one group of WBR_in links to each other with data input pin, address date input end, the read-write enable signal input end of SRAM respectively; The parallel input end of another group WBR_out links to each other with the data output end of SARM; The clock signal input terminal of boundary register WBR, shift enable signal end, parallel enable signal end and instruction register WIR link to each other, and the control signal output ends and instruction register WIR of control interface WIP links to each other; Bypass register WBY is connected between WSI and the WSO, the path of a bypass is provided so that test data is passed through test shell, the path that can effectively shorten scanning fast.

3. a kind of embedded SRAM memory test structure according to claim 1 based on IEEE 1500, it is characterized in that: said BIST test controller comprises: algorithmic state machine module, director data module, read-write module, address date module, input buffer module, output buffer module, control signal module, comparison module as a result; Algorithmic state machine module and instruction data module, read-write module, address date module, control signal module, comparison module links to each other as a result, and controls its duty, and the read-write module links to each other with output buffer module; The read-write state of control output buffer module, the director data module links to each other with output buffer module, exports test instruction through output buffer module to the test shell; The address date module links to each other with output buffer module, and the test address data that the address date module produces output to the test shell through output buffer module, and the data background module links to each other with output buffer module; Test stimulus data and command signal that the data background module produces output to the test shell through output buffer module; The data output end WSO of output buffer module links to each other with the data input pin WSI of test shell, and the control signal module connects with the test shell facies, the output control signal; The data input pin WSI of input buffer module links to each other with the data output end WSO of test shell; The acceptance test response signal, input buffer module links to each other with comparison module as a result, and the test response data that receives is outputed to comparer as a result; The data background module links to each other with comparison module as a result; The test stimulus data that generates is outputed to comparison module as a result, and comparison module compares test stimulus data and test response data as a result, and the output comparative result.

4. a kind of embedded SRAM memory test structure based on IEEE 1500 according to claim 1 is characterized in that: include clock signal, state model control signal, to test shell control signal, test result signal output part signal.

5. a kind of embedded SRAM memory test structure based on IEEE 1500 according to claim 4 is characterized in that: said state model signal input end can be imported normal mode, test pattern and three kinds of test mode signals of bypass mode.

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