CN105760268A - On-chip random access memory built-in self-testing method and device - Google Patents
On-chip random access memory built-in self-testing method and device Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
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Abstract
The embodiment of the invention provides an on-chip random access memory built-in self-testing (RAM BIST) method and device.The method includes the steps that a writing-in functional mode Pattern and a testing function Pattern are preset; when an RAM BIST module receives the writing-in function Pattern, the RAM BIST module is switched into an RAM writing-in program state, an instruction in the writing-in function Pattern is written in an RAM, a CPU maps a valuing address into a corresponding RAM, and the instruction is read according to the valuing address; when the RAM BIST module receives the testing function Pattern, based on a March LR algorithm, the instruction starts to be executed on the RAM for testing from a testing starting address, and a testing result is output.By means of the embodiment of the invention, the number of testing chips can be increased, detection time can be saved, detection steps can be reduced, and therefore chip testing cost is reduced, and testing efficiency is improved.
Description
Technical field
The present embodiments relate to technical field of measurement and test, particularly relate to random access memory build-in self-test method and device on a kind of sheet supporting data to write.
Background technology
RAM (Random-AccessMemory, random access memory) is widely used in IC products because of the advantage such as low-power consumption, silicon-area overhead be little.Along with IC products, for instance on sheet, RAM capacity is increasing, quantity gets more and more, and unavoidably there will be the inefficacy of RAM in manufacturing process, with the mistake that the chip of failed storage unit will cause Product-level to estimate, causes correction cost abruptly increase.Therefore in the Wafer stage, test and screening that RAM carries out high coverage rate become a very important ring in chip Life cycle, and how to be tested by Wafer and quickly position defective unit, improve detection coverage rate, and then reduce the testing time, improve testing efficiency, be the problem needing to analyse in depth and solve at the beginning of chip designs.
On traditional sheet, ram test carries out usually by external test facility, such as in the test of RAM on sheet, including DC characteristic test, AC characteristic test, functional test, reliability testing etc., the test of storage failure is generally used March algorithm, this March algorithm can according to the structure of memorizer, write the resolution chart of certain forms to cover all of memory element, detect the function of these memory element.But, for different tested RAM, it usually needs different testing times and test system, for instance have different IPs logical combination on a single die in a SOC(system on a chip), the index if desired testing all core then needs all test systems of correspondence to perform test.Owing to SOC(system on a chip) scale and integrated level constantly expand, circuit structure is often more complicated, and traditional method of testing is obviously difficult to meet demand.
BIST (Build-In-Self-Test, built-in self-test) implants related functional circuits for providing the technology of selftest function in circuit when design, reduces the device detection degree of dependence to ATE with this.Therefore, the Main Means that RAMBIST is increasingly becoming on sheet ram test.The detection algorithm that the RAMBIST circuit of prior art is conventional is MarchLR algorithm.This MarchLR algorithm has the feature of detection speed, also can reach certain coverage rate in the fault detecting single unit and coupling fault.But, existing upper RAMBIST testing circuit, functionally only detects RAM physical fault defect, and underaction is with efficient.
Summary of the invention
Embodiments provide random access memory built-in self-test (RAMBIST) method and apparatus on a kind of sheet, test number of chips can be improved, save the detection time, reduce testing sequence, thus reducing chip testing cost and improving testing efficiency.
Embodiments provide a kind of RAMBIST method on sheet, including: pre-set write-in functions pattern Pattern and test function Pattern, said write function Pattern includes instruction and end mark, and described test function Pattern includes instruction, test initial address and end mark；When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to described value address；When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address and test, and output test result.
Further, the instruction in said write function Pattern is 8bits command word, and end mark is 1bit low level；Described method also includes: said write function Pattern sends out data at test clock BIST_clk trailing edge, and write-in functions Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs command function.
Further, the instruction in described test function Pattern is 8bits command word, and test initial address is 20bits command word, and end mark is 1bit low level；Described test function Pattern sends out data at test clock BIST_clk trailing edge, and test function Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs function.
Further, it is described when RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and the instruction in write-in functions Pattern is write RAM, value address is mapped to the RAM of correspondence by CPU, and read instruction according to described value address, particularly as follows: when RAMBIST module passes through I/O interface to write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, write-in functions Pattern hardware is decoded, after decoding is correct, RAM selects to enable, RAM write request signal is effective, RAMBIST module is from value address, instruction is write RAM from DIN；After write RAM completes, value address is mapped to the RAM of correspondence, system reset by CPU, and RAM selects to enable, and RAM write request signal is effective, and CPU, from value address, reads instruction from DOUT.
Further, it is described when RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address to test, and output test result particularly as follows: when RAMBIST module receives test function Pattern, obtain the instruction in test function Pattern, test initial address and end mark, RAM selects to enable, based on MarchLR algorithm, begin at RAM execution instruction from test initial address and test；If being not detected by mistake in test process, after waiting that test completes, exporting correct test result, described correct test result includes accurate indication；If mistake being detected in test process, after waiting that test completes, output error test result, described false test result includes error identification and mistake address.
Further, described method also includes: the RAM for different pieces of information width on sheet, capacity carries out concurrent testing.
The embodiment of the present invention additionally provides RAMBIST device on a kind of sheet, in described device, RAMBIST module receives information by input/output interface, and communicate with RAM connection, RAM passes through system bus and CPU interactive information, there is Rom and Flash, CPU by system bus from Rom and Flash fetching, decoding and execution in instruction；Described device pre-sets write-in functions pattern Pattern and test function Pattern, said write function Pattern and includes instruction and end mark, and described test function Pattern includes instruction, test initial address and end mark；When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to described value address；When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address and test, and output test result.
Further, the instruction in said write function Pattern is 8bits command word, and end mark is 1bit low level；Instruction in described test function Pattern is 8bits command word, and test initial address is 20bits command word, and end mark is 1bit low level.
Further, described RAM_BIST module interface signal is divided into input signal and output signal, wherein: described input signal, it is clock signal including clk, rst_n is low reset signal, en is that work enables signal, and all_en is that the work of full sheet concurrent testing enables, and addr_max is the maximum address value of test RAM；Described output signal, it is that RAM reads data including BIST_rd_data, BIST_cen is that RAM selects to enable, BIST_addr is address ram, BIST_we is RAM write request signal, BIST_oe is that RAM output enables signal, and BIST_wr_data is that RAM write enters data, and IO_out is correct/error mark and mistake address output IO.
Further, it is described when RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and the instruction in write-in functions Pattern is write RAM, value address is mapped to the RAM of correspondence by CPU, and read instruction according to described value address, particularly as follows: when RAMBIST module passes through I/O interface to write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, write-in functions Pattern hardware is decoded, after decoding is correct, RAM selects to enable, RAM write request signal is effective, RAMBIST module is from value address, instruction is write RAM from DIN；After write RAM completes, value address is mapped to the RAM of correspondence, system reset by CPU, and RAM selects to enable, and RAM write request signal is effective, and CPU, from value address, reads instruction from DOUT.
Further, it is described when RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address to test, and output test result particularly as follows: when RAMBIST module receives test function Pattern, obtain the instruction in test function Pattern, test initial address and end mark, RAM selects to enable, based on MarchLR algorithm, begin at RAM execution instruction from test initial address and test；If being not detected by mistake in test process, after waiting that test completes, exporting correct test result, described correct test result includes accurate indication；If mistake being detected in test process, after waiting that test completes, output error test result, described false test result includes error identification and mistake address.
Further, described RAMBIST module carries out concurrent testing for the RAM of different pieces of information width on sheet, capacity.
RAM build-in self-test method and device on the sheet that the embodiment of the present invention provides, based on MarchLR algorithm, support that RAM write enters instruction and performs function, add output fault address, initial address can be joined, the scheme of full sheet parallel test function simultaneously, it is possible to increase test number of chips, saving detection time, minimizing testing sequence are thus reducing chip testing cost and improving the purpose of testing efficiency.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from description, or understand by implementing the present invention.The purpose of the present invention and other advantages can be realized by structure specifically noted in description, claims and accompanying drawing and be obtained.
Accompanying drawing explanation
Accompanying drawing is for providing being further appreciated by technical solution of the present invention, and constitutes a part for description, is used for explaining technical scheme, is not intended that the restriction to technical solution of the present invention together with embodiments herein.
Fig. 1 is RAMBIST electrical block diagram on sheet in the embodiment of the present invention；
Fig. 2 is RAM_BIST module interface signal schematic representation in the embodiment of the present invention；
Fig. 3 is the schematic flow sheet of RAMBIST method on sheet in the embodiment of the present invention；
Fig. 4 is the simulation waveform schematic diagram of write-in functions Pattern decoding function in the embodiment of the present invention；
Fig. 5 is the simulation waveform schematic diagram of the write of the instruction in write-in functions Pattern RAM function in the embodiment of the present invention；
Fig. 6 is the simulation waveform schematic diagram of the configuration of single ram test initial address and startup in the embodiment of the present invention；
Fig. 7 is simulation waveform schematic diagram address error data being detected in the embodiment of the present invention；
Fig. 8 is that in the embodiment of the present invention, detection terminates rear output error mark and the simulation waveform schematic diagram of mistake address；
Fig. 9 is the simulation waveform schematic diagram detecting correct output identification in the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.It should be noted that when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
Can perform in the computer system of such as one group of computer executable instructions in the step shown in the flow chart of accompanying drawing.And, although illustrate logical order in flow charts, but in some cases, it is possible to perform shown or described step with the order being different from herein.
Fig. 1 is RAMBIST electrical block diagram on sheet in the embodiment of the present invention, as it is shown in figure 1, RAMBIST module is by I/O (input/output) interface information, and and RAM connect and communicate, RAM is by system bus and CPU interactive information；There is Rom and Flash, CPU by system bus from Rom and Flash fetching, decoding, execution in instruction, configures each module, completes application.
Fig. 2 is RAM_BIST module interface signal schematic representation in the embodiment of the present invention, and wherein clk is clock signal, and rst_n is low reset signal, and en is that work enables signal, and all_en is that the work of full sheet concurrent testing enables, and addr_max is the maximum address value of test RAM.BIST_rd_data is that RAM reads data, BIST_cen is that RAM selects to enable (low effectively), BIST_addr is address ram, BIST_we is RAM write request signal, BIST_oe is that RAM output enables signal, BIST_wr_data is that RAM write enters data, and IO_out is correct/error mark and mistake address output IO.
Due to Rom and Flash self design reasons, technological reason, or the chip Rom being likely to result in encapsulation and handling process and Flash program area damage, instruction cannot be performed after causing chip to power on, it is impossible to test each functions of modules.Although Rom and Flash damages, CPU and other modules are likely to intact, and in the prior art, such chip generally also can only be given up, thus reducing testable number of chips.But, if the attempt to new technology, or MPW (MultiProjectWafer) stage, number of chips to be measured is limited, then the chip of each encapsulation is valuable and can be made full use of.
Relative to prior art, invention increases write instruction ram data function and in RAM, perform command function, specifically, instruction repertorie write RAM and in RAM by exterior I/O, perform the command function of write, such that it is able to test functions of modules, improve test number of chips, reduce testing cost.
Additionally, existing RAMBIST tests circuit design underaction with efficient.It is mainly reflected in: existing design only outputs test result mark, does not export concrete wrong address, therefore cannot understand memorizer entirety bad block position, is unfavorable for linking up with chip manufacturer, analyzing the amendment of memorizer bad block proportion and distribution situation；Prior art starts incremental variations detection from address " 0 ", and initial detecting address cannot configure.After finding mistake in previous test and quoting mistake address, it is necessary to start the situation continuing to understand ram cell below from this address, then cannot realize；Existing design, for the chip of differently configured capacity RAM, generally requires different test model and tests respectively, add the testing time, improve testing cost.
For problem above, the invention provides a kind of based on MarchLR algorithm, support that RAM write enters instruction and performs function, add output fault address, initial address can be joined, the scheme of full sheet parallel test function simultaneously, reaches to improve test number of chips, saves the detection time, reduces testing sequence, reduces chip testing cost, improves the purpose of testing efficiency.
Fig. 3 is the schematic flow sheet of RAMBIST method on sheet in the embodiment of the present invention.As it is shown on figure 3, include:
Step 301, pre-sets write-in functions Pattern (pattern), and said write function Pattern includes instruction and end mark；When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to value address.
In this step, pre-set write-in functions Pattern structure, this write-in functions Pattern structure includes instruction and end mark, in a particular embodiment of the present invention, as shown in table 1 below, this write-in functions Pattern structure can be made up of the low level end mark of the instruction of 8bits command word and 1bit.
Table 1
When RAMBIST module passes through I/O interface to write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and the instruction in write-in functions Pattern is write RAM.
Write-in functions Pattern sends out data at test clock BIST_clk trailing edge, and write-in functions Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs command function.
Such as in one embodiment, as shown in Figure 4, the command word of write-in functions Pattern is 0x03H to simulation waveform, it is followed by 1bit low level as end mark, after decoding is correct, start to perform write-in functions Pattern, wr_RAM_cos_FLAG hardware set.Now, RAM selects CEN to drag down, and WE is high with effect, from address 0, writes write-in functions Pattern from DIN, as it is shown in figure 5, continuation address write 36 ' h8_0402_0100.
After being completed by the instruction write RAM in write-in functions Pattern, value address is mapped to the RAM of correspondence, system reset by CPU, and CPU starts to read instruction from value address, in order to subsequent execution instruction repertorie, tests system and other modules unspoiled.
Such as in one embodiment, the command word performing write-in functions Pattern from RAM is 0x06H, and after decoding is correct, RAM_cos_en hardware set, fetching address maps so far RAM.System reset sys_rstn set, RAM chip select CEN drags down, and WE is that high reading is effective, from address 0, reads instruction repertorie from DOUT, and continuation address reads 36 ' h8_0402_0100.
Step 302, pre-sets test function Pattern, described test function Pattern and includes instruction, test initial address and end mark；When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from test initial address and test, and output test result.
In this step, pre-set test function Pattern structure, this test function Pattern structure includes instruction, test initial address and end mark, in a particular embodiment of the present invention, as shown in table 2 below, this test function Pattern structure can be made up of the instruction of 8bits command word, the test initial address of 20bits command word and the low level end mark of 1bit.
Table 2
Test function Pattern sends out data at test clock BIST_clk trailing edge, and test function Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs command function.
When RAMBIST module receives test function Pattern, obtain the instruction in test function Pattern, test initial address and end mark.Opening enable, RAMBIST circuit is started working, and specifically, based on MarchLR algorithm, begins at RAM execution instruction from test initial address and tests.
If being not detected by mistake in test process, after waiting that test completes, exporting correct test result, this correct test result includes accurate indication, as shown in table 3, for instance output accurate indication " 0x9009H ".
Table 3
| 0x9009H |
If mistake being detected in test process, after waiting that test completes, output error test result, this false test result includes error identification and mistake address, as shown in table 4, for instance output error mark " 0x5555H " and first address mistake occur.
Table 4
| 0x5555H | 2Obits mistake address |
Such as in one embodiment, simulation waveform is as indicated with 6, the Pattern of single ram test is 0x33H, it is followed by 1bit low level, followed by initial address (Start_addr)=0x3H, after decoding is correct, RAM_BIST_flag hardware set, RAMBIST module starts to detect work from address " 3 ".
As it is shown in fig. 7, RAMBIST module is in detection process, " 28 " address read-write error in data is " 0xaH "；As shown in Figure 8, detection terminates rear output error mark " 0x5555H ", and output error address is " 0x28H "；
As it is shown in figure 9, AMBIST module is not detected by mistake in detection process, after waiting that test completes, then export accurate indication " 0x9009H ".
It is worth noting, all RAM concurrent testings on supporting pieces of the present invention, hence for the RAM of different pieces of information width, capacity, it is possible to simplify testing procedure, reduces the detection time, reduces testing cost, improves testing efficiency.
Present invention also offers RAMBIST device on a kind of sheet, can referring to shown in Fig. 1, in described device, RAMBIST module receives information by input/output interface, and communicate with RAM connection, RAM passes through system bus and CPU interactive information, there is Rom and Flash, CPU by system bus from Rom and Flash fetching, decoding and execution in instruction；Described device pre-sets write-in functions pattern Pattern and test function Pattern, said write function Pattern and includes instruction and end mark, and described test function Pattern includes instruction, test initial address and end mark；
When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to described value address；
When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address and test, and output test result.
Concrete ins and outs in a kind of upper RAMBIST device provided by the present invention corresponding with in a kind of upper RAMBIST method ins and outs similar, therefore be not repeated herein.
In the present invention, on sheet, RAMBIST achieves support instruction write RAM operating instruction function, and support initial address can be joined, mistake address exports, full sheet parallel detection function；Additionally, support instruction write RAM operating instruction, full sheet parallel detection, it is achieved that efficiently, the RAMBist detection scheme of high fault coverage.
Device embodiment described above is merely schematic, the wherein said unit illustrated as separating component can be or may not be physically separate, the parts shown as unit can be or may not be physical location, namely may be located at a place, or can also be distributed on multiple NE.Some or all of module therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.Those of ordinary skill in the art, when not paying performing creative labour, are namely appreciated that and implement.
Through the above description of the embodiments, those skilled in the art is it can be understood that can add the mode of required general hardware platform by software to each embodiment and realize, naturally it is also possible to pass through hardware.Based on such understanding, the part that prior art is contributed by technique scheme substantially in other words can embody with the form of software product, this computer software product can store in a computer-readable storage medium, such as ROM/RAM, magnetic disc, CD etc., including some instructions with so that a computer equipment (can be personal computer, server, or the network equipment etc.) perform the method described in some part of each embodiment or embodiment.
Last it is noted that above example is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. random access memory ram built-in self-test BIST approach on a sheet, it is characterised in that including:
Pre-setting write-in functions pattern Pattern and test function Pattern, said write function Pattern and include instruction and end mark, described test function Pattern includes instruction, test initial address and end mark；
When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to described value address；
When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address and test, and output test result.
2. method according to claim 1, it is characterised in that the instruction in said write function Pattern is 8bits command word, end mark is 1bit low level；
Described method also includes: said write function Pattern sends out data at test clock BIST_clk trailing edge, and write-in functions Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs command function.
3. method according to claim 1, it is characterised in that the instruction in described test function Pattern is 8bits command word, test initial address is 20bits command word, and end mark is 1bit low level；
Described test function Pattern sends out data at test clock BIST_clk trailing edge, and test function Pattern hardware, in test clock rising edge sampled data, is decoded by RAMBIST module, performs function.
4. method according to claim 1, it is characterized in that, it is described when RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and the instruction in write-in functions Pattern is write RAM, value address is mapped to the RAM of correspondence by CPU, and reads instruction according to described value address, particularly as follows:
When RAMBIST module passes through I/O interface to write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, write-in functions Pattern hardware is decoded, after decoding is correct, RAM selects to enable, RAM write request signal is effective, and instruction, from value address, is write RAM from DIN by RAMBIST module；
After write RAM completes, value address is mapped to the RAM of correspondence, system reset by CPU, and RAM selects to enable, and RAM write request signal is effective, and CPU, from value address, reads instruction from DOUT.
5. method according to claim 4, it is characterized in that, described when RAMBIST module receives test function Pattern, based on MarchLR algorithm, from described test initial address begin at RAM perform instruction test, and output test result particularly as follows:
When RAMBIST module receives test function Pattern, obtaining the instruction in test function Pattern, test initial address and end mark, RAM selects to enable, and based on MarchLR algorithm, begins at RAM execution instruction from test initial address and tests；
If being not detected by mistake in test process, after waiting that test completes, exporting correct test result, described correct test result includes accurate indication；
If mistake being detected in test process, after waiting that test completes, output error test result, described false test result includes error identification and mistake address.
6. the method according to any one of Claims 1 to 5, it is characterised in that described method also includes: the RAM for different pieces of information width on sheet, capacity carries out concurrent testing.
7. random access memory ram built-in self-test BIST device on a sheet, it is characterized in that, in described device, RAMBIST module receives information by input/output interface, and communicate with RAM connection, RAM passes through system bus and CPU interactive information, there is Rom and Flash, CPU by system bus from Rom and Flash fetching, decoding and execution in instruction；
Described device pre-sets write-in functions pattern Pattern and test function Pattern, said write function Pattern and includes instruction and end mark, and described test function Pattern includes instruction, test initial address and end mark；
When RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and value address is mapped to by instruction write RAM, the CPU in write-in functions Pattern corresponding RAM, and read instruction according to described value address；
When RAMBIST module receives test function Pattern, based on MarchLR algorithm, begin at RAM execution instruction from described test initial address and test, and output test result.
8. device according to claim 7, it is characterised in that the instruction in said write function Pattern is 8bits command word, end mark is 1bit low level；
Instruction in described test function Pattern is 8bits command word, and test initial address is 20bits command word, and end mark is 1bit low level.
9. device according to claim 7, it is characterised in that described RAM_BIST module interface signal is divided into input signal and output signal, wherein:
Described input signal, is clock signal including clk, and rst_n is low reset signal, and en is that work enables signal, and all_en is that the work of full sheet concurrent testing enables, and addr_max is the maximum address value of test RAM；
Described output signal, it is that RAM reads data including BIST_rd_data, BIST_cen is that RAM selects to enable, BIST_addr is address ram, BIST_we is RAM write request signal, BIST_oe is that RAM output enables signal, and BIST_wr_data is that RAM write enters data, and IO_out is correct/error mark and mistake address output IO.
10. device according to claim 7, it is characterized in that, it is described when RAMBIST module receives write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, and the instruction in write-in functions Pattern is write RAM, value address is mapped to the RAM of correspondence by CPU, and reads instruction according to described value address, particularly as follows:
When RAMBIST module passes through I/O interface to write-in functions Pattern, self is switched to RAM write to enter program state by RAMBIST module, write-in functions Pattern hardware is decoded, after decoding is correct, RAM selects to enable, RAM write request signal is effective, and instruction, from value address, is write RAM from DIN by RAMBIST module；
After write RAM completes, value address is mapped to the RAM of correspondence, system reset by CPU, and RAM selects to enable, and RAM write request signal is effective, and CPU, from value address, reads instruction from DOUT.
11. device according to claim 10, it is characterized in that, described when RAMBIST module receives test function Pattern, based on MarchLR algorithm, from described test initial address begin at RAM perform instruction test, and output test result particularly as follows:
When RAMBIST module receives test function Pattern, obtaining the instruction in test function Pattern, test initial address and end mark, RAM selects to enable, and based on MarchLR algorithm, begins at RAM execution instruction from test initial address and tests；
If being not detected by mistake in test process, after waiting that test completes, exporting correct test result, described correct test result includes accurate indication；
If mistake being detected in test process, after waiting that test completes, output error test result, described false test result includes error identification and mistake address.
12. the device according to any one of claim 7～11, it is characterised in that described RAMBIST module carries out concurrent testing for the RAM of different pieces of information width on sheet, capacity.
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Cited By (12)
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| CN106646191A (en) * | 2016-11-25 | 2017-05-10 | 天津津航计算技术研究所 | Functional test method for SiP (system in package) embedded memory |
| CN106653096A (en) * | 2016-12-21 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | NVM testing reading acceleration method and circuit |
| CN108899061A (en) * | 2018-07-20 | 2018-11-27 | 北京嘉楠捷思信息技术有限公司 | Memory built-in self-test method and system in power supply normally-open chip |
| CN109192239A (en) * | 2018-07-25 | 2019-01-11 | 上海交通大学 | The on-chip test circuit and test method of SRAM memory |
| CN110427292A (en) * | 2019-07-29 | 2019-11-08 | 深圳忆联信息系统有限公司 | The method and device that FLASH is tested using embedded ROM |
| CN111273156A (en) * | 2020-02-24 | 2020-06-12 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN111707890A (en) * | 2020-06-01 | 2020-09-25 | 恒大恒驰新能源汽车研究院(上海)有限公司 | Detection method, electronic equipment, storage medium, and anti-theft key writing method and device |
| CN112053732A (en) * | 2020-05-20 | 2020-12-08 | 深圳市宏旺微电子有限公司 | DRAM (dynamic random Access memory) fault detection method, device and system based on March algorithm optimization |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
| CN113656310A (en) * | 2021-08-19 | 2021-11-16 | 厦门壹普智慧科技有限公司 | Built-in self-test system of neural network tensor processor |
| CN115236485A (en) * | 2022-06-24 | 2022-10-25 | 无锡芯领域微电子有限公司 | Rapid detection device and method based on-chip self-built test |
| CN118609635A (en) * | 2024-08-07 | 2024-09-06 | 博越微电子(江苏)有限公司 | ONFI TESTCHIP built-in self-test method and device based on LFSR design |
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| CN106646191A (en) * | 2016-11-25 | 2017-05-10 | 天津津航计算技术研究所 | Functional test method for SiP (system in package) embedded memory |
| CN106653096A (en) * | 2016-12-21 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | NVM testing reading acceleration method and circuit |
| CN108899061B (en) * | 2018-07-20 | 2021-03-09 | 嘉楠明芯(北京)科技有限公司 | Memory built-in self-test method and system in power supply normally-open chip |
| CN108899061A (en) * | 2018-07-20 | 2018-11-27 | 北京嘉楠捷思信息技术有限公司 | Memory built-in self-test method and system in power supply normally-open chip |
| CN109192239A (en) * | 2018-07-25 | 2019-01-11 | 上海交通大学 | The on-chip test circuit and test method of SRAM memory |
| CN110427292A (en) * | 2019-07-29 | 2019-11-08 | 深圳忆联信息系统有限公司 | The method and device that FLASH is tested using embedded ROM |
| CN111273156A (en) * | 2020-02-24 | 2020-06-12 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN111273156B (en) * | 2020-02-24 | 2022-01-11 | 江苏传艺科技股份有限公司 | Online test system for GaN millimeter wave power amplifier chip |
| CN112053732A (en) * | 2020-05-20 | 2020-12-08 | 深圳市宏旺微电子有限公司 | DRAM (dynamic random Access memory) fault detection method, device and system based on March algorithm optimization |
| CN111707890A (en) * | 2020-06-01 | 2020-09-25 | 恒大恒驰新能源汽车研究院(上海)有限公司 | Detection method, electronic equipment, storage medium, and anti-theft key writing method and device |
| CN112630622A (en) * | 2020-12-17 | 2021-04-09 | 珠海芯网测控有限公司 | Method and system for pattern compiling and downloading test of ATE (automatic test equipment) |
| CN112630622B (en) * | 2020-12-17 | 2022-05-31 | 珠海芯业测控有限公司 | Method and system for pattern compiling, downloading and testing of ATE (automatic test equipment) |
| CN113656310A (en) * | 2021-08-19 | 2021-11-16 | 厦门壹普智慧科技有限公司 | Built-in self-test system of neural network tensor processor |
| CN113656310B (en) * | 2021-08-19 | 2023-07-14 | 厦门壹普智慧科技有限公司 | Built-in self-test system of neural network tensor processor |
| CN115236485A (en) * | 2022-06-24 | 2022-10-25 | 无锡芯领域微电子有限公司 | Rapid detection device and method based on-chip self-built test |
| CN115236485B (en) * | 2022-06-24 | 2023-11-03 | 无锡芯领域微电子有限公司 | Rapid detection device and method based on-chip built-in test |
| CN118609635A (en) * | 2024-08-07 | 2024-09-06 | 博越微电子(江苏)有限公司 | ONFI TESTCHIP built-in self-test method and device based on LFSR design |
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