CN202075651U - High-order curvature compensation band-gap resistance voltage source - Google Patents
High-order curvature compensation band-gap resistance voltage source Download PDFInfo
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Abstract
The utility model discloses a high-order curvature compensation band-gap resistance voltage source, which specifically comprises a start-up circuit, an auxiliary reference circuit, an index number curvature compensating circuit, a logarithm curvature compensating circuit and a current superposed circuit. The reference voltage source realizes index number curvature compensation in a low-temperature region by the aid of the auxiliary reference circuit and the index number curvature compensating circuit, realizes logarithm curvature compensation in a high-temperature region by the aid of the logarithm curvature compensating circuit, leads temperature drift to be reduced effectively within a total temperature range, has better temperature stability and PSRR (power supply rejection ratio) performance, and can normally operate under the condition that input voltage is reduced to 1.6V. The high-order curvature compensation band-gap resistance voltage source reduces power consumption of a circuit while realizing low temperature drift, and has lower work voltage.
Description
Technical Field
The utility model belongs to the technical field of the power, concretely relates to band gap reference voltage source's design.
Background
In the application of a plurality of analog circuits, digital circuits and digital-analog mixed circuits, the precise reference circuit plays an important role due to the characteristics of high precision and low temperature drift. The reference voltage is required to remain stable over variations in input voltage and temperature and needs to be compatible with standard manufacturing processes. Low voltage and low power consumption are two important properties now considered in the design of many systems, particularly for battery powered products.
The conventional bandgap reference circuit proposed by Widlar and Brokaw is a first order temperature compensated reference. Due to VBEThe temperature coefficient of the first order temperature compensation reference is typically limited to 20 to 100 ppm/deg.C, depending on the temperature non-linearity. Therefore, many methods of higher order temperature compensation are used to overcome the limitations of first order temperature compensation. The higher order temperature compensation methods proposed by Song et al and Lee et al can achieve very small temperature coefficients, but at power consumptionAnd less than optimal in terms of minimum operating voltage.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the problem that current reference voltage source exists, provided a band gap reference voltage source of high-order curvature compensation.
The technical scheme of the utility model is that: a high-order curvature compensated band-gap reference voltage source comprises a starting circuit, an auxiliary reference circuit, an index curvature compensation circuit, a logarithmic curvature compensation circuit and a current superposition circuit, wherein the input ends of the auxiliary reference circuit and the index curvature compensation circuit are respectively connected with the output end of the starting circuit, the output ends of the auxiliary reference circuit and the index curvature compensation circuit are respectively connected with the logarithmic curvature compensation circuit and the current superposition circuit, the output end of the logarithmic curvature compensation circuit is connected with the current superposition circuit, and the output end of the current superposition circuit is a reference voltage.
The auxiliary reference circuit and the exponential curvature compensation circuit comprise PMOS tubes MP6, MP7 and MP8, resistors R2, R3 and R4 and NPN tubes Q4 and Q5, wherein the sources and the substrates of the PMOS tubes MP7 and MP6 are connected with an external power supply, and the gate-drain of the MP7 is in short circuit and is connected with the gate of the MP6 to form a current mirror; an NPN tube Q5 is connected with the base electrode of Q4, and the collector electrode of Q5 is connected with the drain electrode of MP 7; the collector of Q4 is connected with the drain of MP6, the emitter of Q4 is connected with the emitter of Q5 after being connected with resistor R2 and is connected to the ground through resistor R3; the source electrode of the PMOS pipe MP8 is shorted with the substrate and connected to a power supply voltage, the grid electrode is connected with the drain electrode of the MP6, and the drain electrode is connected to the ground through a resistor R4; the drains of the PMOS transistors MP7 and MP6 are two output terminals of the auxiliary reference circuit and the exponential curvature compensation circuit, respectively.
The logarithmic curvature compensation circuit comprises PMOS tubes MP1, MP2, MP3, NMOS tubes MN1, MN2, NPN tubes Q1, Q2 and a resistor R1, wherein sources and substrates of the PMOS tubes MP1, MP2 and MP3 are respectively connected to an external power supply, gates of the MP1 and MP2 are respectively connected with two output ends of the auxiliary reference circuit and the exponential curvature compensation circuit, namely drains of the PMOS tubes MP6 and MP7, bases of the NPN tubes Q1 and Q2 are connected together, an emitter of the Q2 is grounded, and an emitter of the Q1 is grounded through a resistor R1; the drain of the PMOS tube MP1 is connected to the collector of Q1, and the drain of MP2 is connected to the collector of Q2; the gate of the NMOS transistor MN1 is connected to the collector of Q1, the drain is connected to an external power supply, the source is connected to the bases of Q1 and Q2, and the substrate is grounded; the gate of the NMOS transistor MN2 is connected with the collector of Q2, the source is connected with the emitter of Q1, the drain is connected with the drain of MP3, and the substrate is grounded; the drain electrode of the gate of the PMOS transistor MP3 is shorted, and the gate is the output end of the logarithmic curvature compensation circuit.
The current superposition circuit comprises resistors R5 and R6, PMOS tubes MP4, MP5 and MP9, wherein the sources and the substrates of MP4, MP5 and MP9 are connected with an external power supply, and the grid is connected with the output end of the logarithmic curvature compensation circuit; the drain electrode of the PMOS tube MP4 is connected with the drain electrode of MP5, the grid electrode is connected with the drain electrode of MP6, and the drain electrode is grounded through a resistor R6; the grid electrode of the PMOS tube MP9 is connected with the drain electrode of the MP6, the drain electrode is connected with the drain electrodes of the MP4 and the MP5 through a resistor R5, and the drain electrode voltage of the MP9 is the voltage converted after current superposition, namely the output voltage of the reference voltage source.
The utility model has the advantages that: the utility model provides a band gap reference voltage source of high-order curvature compensation has adopted index curvature compensation in the low temperature district through supplementary reference circuit and index curvature compensation circuit, has adopted the logarithm curvature compensation in the high temperature district through logarithm curvature compensation circuit for the temperature drift has obtained reducing effectively in the full temperature range, has better temperature stability and PSRR performance, can normally work under the state of input voltage low to 1.6V moreover. The utility model discloses when realizing that the low temperature floats, reduced the consumption of circuit consumption, lower operating voltage has.
Drawings
Fig. 1 is a schematic structural diagram of a high-order curvature compensated bandgap reference voltage source according to the present invention.
Fig. 2 is a complete circuit diagram of a high-order curvature compensated bandgap reference voltage source of the present invention.
Fig. 3 is a temperature characteristic curve of logarithmic curvature compensation according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of simulated temperature characteristics of a reference voltage source according to an embodiment of the present invention.
Fig. 5 is a graph showing a test temperature characteristic of a reference voltage source according to an embodiment of the present invention.
Fig. 6 is a graph showing the temperature characteristics of five sample wafers after trimming of the reference voltage source of the embodiment of the present invention.
Fig. 7 is a schematic diagram of a relationship between the output voltage PSRR and the frequency according to an embodiment of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and specific embodiments.
Base-emitter voltage V of NPN tube biased in forward active regionBEThe relationship with the collector current can be expressed by the following equation:
VBE(T)＝VG0-mVT-(η-ζ)VTlnT formula (1)
Where m is a constant independent of temperature, ζ is the order of the collector current dependent on temperature, VTIs the thermal voltage kT/q, k is the Boltzmann constant, q is the charge of an electron, VG0Is the bandgap voltage of silicon at 0K, η is 4-n, n is the temperature dependent order of carrier mobility, η is usually between 3 and 4, and typically 3.54. VTlnT items represent VBEThe higher order non-linearity with temperature, the first order compensation involves canceling the term associated with T, and the higher order compensation involves canceling the term associated with the higher order T.
The utility model discloses a band gap reference voltage source's of high-order curvature compensation structure schematic diagram is shown in FIG. 1, including starting circuit 100, supplementary reference circuit and index curvature compensation circuit 200, logarithm curvature compensation circuit 300 and electric current stack circuit 400, supplementary reference circuit and index curvature compensation circuit 200's input respectively with starting circuit 100's output is connected, supplementary reference circuit and index curvature compensation circuit 200's output respectively with logarithm curvature compensation circuit 300 with electric current stack circuit 400 is connected, logarithm curvature compensation circuit 300's output with electric current stack circuit 400 is connected, electric current stack circuit 400's output is voltage reference promptly.
After the circuit is started, the auxiliary reference circuit and the exponential curvature compensation circuit 200 generate a PTAT current IPTATAnd a first order temperature compensated reference voltage VREF_AUXThen using VREF_AUXGenerating an exponential curvature compensated temperature independent current ITI。IPTATAnd ITICurrent is injected into the logarithmic curvature compensation circuit 300 to generate a current IPiecewise_LCC. This current is zero in the low temperature region and proportional to the logarithmic term in the high temperature region. Finally, the three currents related to the temperature are superposed according to a certain proportion, and then the superposed currents are converted into voltages to obtain the reference voltage V of the high-order temperature compensationREF。
The resistors involved in the circuit are all of the same type of resistor. For convenience of description, the temperature coefficient of the resistor is temporarily ignored, and the influence of the temperature coefficient of the resistor on the reference voltage is finally analyzed.
As shown in fig. 2, the Auxiliary reference circuit and index curvature compensation circuit 200 (auxiary BGR and ECC) includes PMOS transistors MP6, MP7, MP8, resistors R2, R3, R4, and NPN transistors Q4, Q5, wherein the sources and the substrates of the PMOS transistors MP7 and MP6 are both connected to an external power supply VDD, MP7 is gate-drain shorted and connected to the gate of MP6 to form a current mirror, Q5 is connected to the base of Q4, the collector of Q387q 5 is connected to the drain of MP7, the collector of Q4 is connected to the drain of MP6, the emitter of Q4 is connected to R2 and then to the emitter of Q5 and connected to ground through resistor R3, the source of MP8 is shorted to the substrate to a power supply voltage, the gate of MP8 is connected to the drain of MP6, the drain of MP8 is connected to ground through R4, and the drains of MP7 and MP6 are connected to the two output terminals of the Auxiliary reference circuit.
The voltage at point A is the reference voltage of first-order temperature compensation, VREF_AUX＝VBE5+2R3VTlnN/R2Also, I can be obtainedPTAT＝VTlnN/R2Where N is the ratio of the emitter areas of Q4 and Q5. The exponential curvature compensation can be realized by a simple circuit consisting of the MP8 and the resistor R4. Exponential curvature compensated current ITIComprises the following steps:
Wherein beta (T) is common emitter current gain of the triode, 2R4VTlnN/[R2β(T)]This term represents the effect of the base currents of Q4 and Q5, resulting in exponentially compensated powerAnd (4) streaming. Beta (T) is exponential with temperature T and reciprocal of exponential function with emitter doping concentration. The above relationship may be expressed as β (T) ═ β∞exp[-ΔEG/(kT)]In which Δ EGIs the amount by which the band gap of silicon narrows with the emitter doping concentration, beta∞Is the maximum value of the gain of the common emitter current of the triode, and beta∞Is temperature independent. Therefore, ITICan be expressed as:
Wherein,
high order curvature compensation is achieved. At TrIt is Taylor expanded at temperature:
Wherein, a0，a1，a2And a3Are constant independent of temperature. Consider equation (3) and equation(4) The curvature compensation term shows a complex functional relationship with temperature, and since it has many high-order terms, it can only cancel VBE5The effect of curvature of (a). By setting the appropriate R4/R2，R3/R2And the value of the parameter N, I compensated by exponential curvatureTICan be optimized, then ITIThe temperature coefficient of (a) may reach zero at some temperature points. This causes ITISimilar to a temperature independent current.
In order to improve the PSRR and linear regulation of the present invention, the circuit includes a negative feedback loop consisting of MP8 and resistor R4. After the size of the MP8 is reasonably set, the voltage difference at the node B, C can be greatly reduced, and the effect of stabilizing the output can also be achieved. When V isDDThe change results in VREF_AUXAfter rising, the voltage at node B will also rise, and the reverse amplification of MP8 will be VREF_AUXAnd vice versa.
As shown in fig. 2, the logarithmic curvature compensation circuit 300 (pietwist Lcc) includes PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, NPN transistors Q1, Q2 and resistor R1, wherein the sources and the substrates of MP1, MP2 and MP3 are connected to the external power VDD, the gates of MP1 and MP2 are connected to the auxiliary reference circuit and the drains of the two outputs of the exponential curvature compensation circuit, i.e., PMOS transistors MP6 and MP7, the bases of Q1 and Q2 are connected together, the emitter of Q2 is grounded, the emitter of Q1 is grounded via resistor R1, the drain of MP1 is connected to the collector of Q1, the drain of MP2 is connected to the collector of Q2, the gate of MN2 is connected to the collector of Q2, the drain of MN2 is connected to the power voltage, the source of MN2 is connected to the bases of Q2 and Q2, the drain of MN2 is connected to the drain of MN2, the drain of MN2 is connected to the drain of, the gate of MP3 is the output of the logarithmic curvature compensation circuit. Here, the current flowing through MP1 is an exponentially compensated current, and the current flowing through MP2 is a PTAT current.
The MN1 transistor is used for reducing errors introduced by base currents of Q1 and Q2. Combining formula (1)) And (3) to obtain IPiecewise_LCCThe expression of (a) is:
IPiecewise_LCC＝[VTln(AT/C)-BC]/R1formula (5)
Wherein A ═ γ kR4lnN/(αqR2) α and γ are temperature independent constants, and B ═ α R1/R4， <math><mrow>
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</mrow></math> A and B are temperature independent constants, and C is similar to the output of a reference subjected to exponential curvature compensation and can be approximately regarded as a parameter of zero temperature coefficient. Thus, IPiecewise_LCCIs proportional to the logarithmic term. The above conclusion is established at VTln (AT/C) ≥ BC, and when VTWhen ln (AT/C) < BC, there will be no output current. Suppose that at a temperature point T1Therein is provided with
If true, then the piecewise logarithmic curvature compensation current can be represented by the following equation:
IPiecewise_LCCAs shown in fig. 4, the temperature characteristic of (a) is zero in the low temperature region and is proportional to the logarithmic term in the high temperature region. If all the tubes in fig. 3 are operated in the forward active region, then the logarithmic curvature compensation current V is applied in the low temperature regionTln(AT/C)/R1Is less than ITI. The logarithmic curvature compensation current in the high temperature region is larger than ITI. Thus, the output current IPiecewise_LCCNon-linear, zero in the low temperature region, and non-zero in the high temperature region.
As shown in fig. 2, the current superposition circuit 400(I-V converter) includes resistors R5, R6, and PMOS transistors MP4, MP5, and MP9, wherein the sources and the substrates of MP4, MP5, and MP9 are connected to the external power supply VDD, and the gates are connected to the output of the logarithmic curvature compensation circuit; the drain of MP4 is connected with the drain of MP5, the grid is connected with the drain of MP6, the drain is earthed through resistance R6, the grid of MP9 is connected with the drain of MP6, the drain is connected to the drains of MP4 and MP5 through resistance R5, the drain voltage of MP9 is the voltage converted after current superposition, namely the output reference voltage of the circuit. Here, the current flowing through MP4 is a segmented logarithmic curvature compensation current, the current flowing through MP5 is an exponentially compensated current, the current flowing through MP9 is an exponentially compensated current,
such a resistive current superposition circuit increases the flexibility of temperature compensation. In conjunction with equation (3) and equation (6), the reference voltage can be expressed as:
Wherein D ═ α R6/R4+δ(R5+R6)/R4，E＝R6/R1，F＝δ(R5+R6)/R4δ is a constant independent of temperature, and D, E, and F are also constants independent of temperature. Alpha ITIThe current is used to generate a log curvature compensated current in the high temperature region to eliminate the BC term in equation (5). This may make the process of designing and trimming more convenient. Therefore, the utility model discloses a high-order curvature compensation's benchmark is realized through simple circuit, does not have additional more circuit, and output voltage's temperature coefficient can be zero at a plurality of temperature points moreover. In the low temperature region, T < T1Output voltage VREFExponential curvature compensation, T ≧ T in the high-temperature region1Logarithmic curvature compensation term EVTln (AT/C) reduces V AT high temperaturesBE5Is not linear. Therefore, the various temperature-related components of the present invention can be optimized by trimming respectively.
As can be seen from equation (7), all resistances in the circuit are in the form of a ratio of resistances. Therefore, the influence of the temperature coefficient of resistance on the output reference voltage can be greatly reduced by adopting the same type of resistance, the temperature coefficient of resistance only has a slight influence on the order of the collector current of the Q5, which is related to the temperature, and the temperature coefficient of resistance has a slight influence on VBE5The effect of (c) can be compensated by trimming.
Trimming of the reference must be considered in order to guarantee the temperature characteristics. The structure of fig. 2 has greater flexibility for temperature compensation than the strict current-mode and voltage-mode structures. The output voltage and the temperature coefficient of each temperature component can be corrected by simply changing the resistance ratio. The temperature compensation can be corrected over the full temperature range. The utility model discloses a trimming designs two aspects: one is the trimming of the exponential curvature compensation and the other is the trimming of the logarithmic curvature compensation. Exponential curvature compensation can be achieved by varying R3/R2，R4/R2And R5/R4Trimming is performed, and logarithmic curvature compensation can be performed by changing R6/R1Trimming is carried out. Thus, the first trimming step is to select a suitable R3/R2Let V beREF_AUXFor first order temperature compensation. The second trimming step is to select the appropriate R4/R2And optimizing exponential curvature compensation. The third step is to find the appropriate R5/R4To output a voltage VREFSet to the desired value. The last step is to find the appropriate R6/R1And optimizing logarithmic curvature compensation. The utility model discloses in, in order to reach the trimming effect, R3Using 4-position, R4Adopt 6 position, R5Using 2-position, R1Adopts 5 bits to carry out trimming, R2And R6Are all fixed values.
When the input is powered up and the circuit begins to operate, the voltage at node a is low and the voltage at node B is high, MS3 is on. Next, the node B voltage drop is pulled low and MP8 begins to have current flowing through it. The a node voltage then rises. Therefore, the utility model discloses the benchmark just breaks away from and merges the attitude, gets into required steady operation state. When the a-node voltage exceeds a certain value, the MS3 will be turned off. The start-up circuit has no effect on the normal operating state of the reference circuit.
The lowest working voltage of the auxiliary reference circuit and the exponential curvature compensation circuit consists of a gate-source voltage, a triode saturation voltage and a resistor R3The sum of the upper voltages.
Wherein, VSG(MP7)，VTH(MP7)And VOV(MP7)Representing the gate-source voltage, the threshold voltage and the overdrive voltage of MP7, respectively. VCE-SAT(Q5)Is the saturated pressure drop of Q5,
is a resistance R3Pressure drop over the pressure drop. The lowest operating voltage of the piecewise logarithmic curvature compensation circuit is:
VDD≥VSG(MN1)+|VOV(MP1)|+VBE(Q2)≈|VTH(MN1)|+|VOV(MP1)|+VBE(Q2)formula (9)
Wherein, VTH(MN1)Is the threshold voltage, V, of MN1OV(MP1)Is the overdrive voltage, V, of MP1BE(Q2)Is the base emitter voltage of Q2. Because MN1 is biased near the subthreshold region, VSG(MN1)Close to VTH(MN1)。VDDAt the output node:
VDD≥VREF+|VOV(MP9)equation (10)
Wherein, VOV(MP9)Is the overdrive voltage, V, of MP9REFIs the output reference voltage of the present invention, the minimum input voltage required by the circuit is the maximum value among the above three limits. The overdrive voltage of the MOSFET is typically set between 100mV and 200mV, and the saturation drop of Q5 is approximately 150mV to 300 mV. VREFAnd VREF_AUXAre all set at around 1.2V. At 0 ℃ VTHNAnd | VTHPAnd | is about 0.596V and 0.6618V respectively. Therefore, the lowest input voltage is about 1.5V. The lowest input voltage may be selected to be 1.6V, taking into account the variations in actual process and temperature.
Fig. 4 is a diagram showing simulated temperature characteristics of a reference voltage source. VREF_AUXIs first order temperature compensated, temperature coefficientIs 66.3 ppm/DEG C. V subjected to ECCREF_AUXThe combined effect of exponential curvature compensation and first order temperature compensation is shown. The segmented LCC curves in the figure show the effect of segmented logarithmic curvature compensation. The entire temperature range can be divided into two parts by a dashed line. In the low temperature region, the exponential curvature compensation and VREF_AUXIt has its main function. In the high temperature region, logarithmic curvature compensation is added to further reduce VBE5Is not linear. Simulation results show that when the input voltage is 3.6V and the temperature range is-40 ℃ to 110 ℃, the peak value of the output voltage is 1.12mV and the temperature coefficient is 6.2 ppm/DEG C. V compensated with first order temperatureREF_AUXIn contrast, the temperature drift is reduced by about 10 times. VREF_AUXThe difference from the other voltage averages is mainly due to the difference in test methods. V in FIG. 4REF_AUXThe voltage being directly from VREF_AUXThe node test results, while the other voltages in FIG. 4 are converted from current to voltage, including the ratio of resistors R5 and R6.
Fig. 5 is a curve of the output voltage with temperature after trimming. When the input voltage is 3.6V and the temperature range is-40 ℃ to 100 ℃, the output voltage V isREFThere was only a 0.07% change. When the input voltage is changed from 1.6V to 5V, the minimum temperature coefficient is 5 ppm/DEG C, and the maximum temperature coefficient is 7.2 ppm/DEG C. But the output reference voltage does not vary much. This is mainly due to the advanced compensation techniques proposed by the present invention. FIG. 6 shows 5 calibrated benchmarks with minimum temperature coefficients. The 5 benchmarks have a maximum to minimum peak-to-peak voltage difference of only 1.3mV over the temperature range of-40 ℃ to 100 ℃.
Fig. 7 is a graph of Power Supply Rejection Ratio (PSRR) versus frequency (Hz) at 3.6V input voltage, room temperature, and no output filter capacitance. The utility model discloses there is 70 dB's PSRR at the frequency below 1KHz, has the PSRR that is greater than 55dB at the frequency below 10 KHz. The performance of the PSRR may also be improved when a cascode current mirror is used. However, the minimum input voltage will increase, which is not compatible with the design requirement of low input voltage reference, and the PSRR at high frequency can be improved by adding a filter capacitor at the reference output terminal.
The band gap reference voltage source of the utility model adopts index curvature compensation in the circuit at low temperature; at high temperature, the circuit adopts a V-based circuitTlnT logarithmic curvature compensation. The standard has good temperature stability, and the Temperature Coefficient (TC) is 5 ppm/DEG C within the temperature range of-40 ℃ to 125 ℃ when the input voltage is 3.6V; the circuit meets the requirement of low-voltage operation and can realize normal operation under the power supply voltage as low as 1.6V; meanwhile, the circuit has lower power consumption, and the maximum quiescent current is 25 muA; the circuit is simple to realize, and an operational amplifier structure is not used, so that the offset influence of the operational amplifier is avoided; the influence of the temperature coefficient of the resistor on the output is small, and trimming of the reference output is convenient.
The band gap reference voltage source of the utility model can be realized by adopting a standard 0.5-mum BiCMOS process. The high-order temperature curvature compensation is realized by combining exponential curvature compensation and segmented logarithmic curvature compensation through a simple circuit. The circuitry required for this compensation approach is very simple and can be easily implemented. And simultaneously, the utility model discloses also be applicable to general trimming process. Because the precision is high, the performance is good, has low quiescent current and low operating voltage, the utility model discloses a reference source can be applied to a lot of mixed signal system.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention, and it is to be understood that the scope of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the teachings of the present invention without departing from the spirit of the invention, and such modifications and combinations are still within the scope of the invention.
Claims (4)
1. A high-order curvature compensated band-gap reference voltage source is characterized by comprising a starting circuit, an auxiliary reference circuit, an exponential curvature compensation circuit, a logarithmic curvature compensation circuit and a current superposition circuit, wherein the input ends of the auxiliary reference circuit and the exponential curvature compensation circuit are respectively connected with the output end of the starting circuit, the output ends of the auxiliary reference circuit and the exponential curvature compensation circuit are respectively connected with the logarithmic curvature compensation circuit and the current superposition circuit, the output end of the logarithmic curvature compensation circuit is connected with the current superposition circuit, and the output end of the current superposition circuit is a reference voltage source.
2. The high-order curvature compensated bandgap reference voltage source according to claim 1, wherein the auxiliary reference circuit and the exponential curvature compensation circuit comprise PMOS transistors MP6, MP7, MP8, resistors R2, R3, R4 and NPN transistors Q4, Q5, wherein the sources and the substrates of the PMOS transistors MP7 and MP6 are connected to an external power supply, and the gate drain of MP7 is shorted and connected to the gate of MP6 to form a current mirror; an NPN tube Q5 is connected with the base electrode of Q4, and the collector electrode of Q5 is connected with the drain electrode of MP 7; the collector of Q4 is connected with the drain of MP6, the emitter of Q4 is connected with the emitter of Q5 after being connected with resistor R2 and is connected to the ground through resistor R3; the source electrode of the PMOS pipe MP8 is shorted with the substrate and connected to a power supply voltage, the grid electrode is connected with the drain electrode of the MP6, and the drain electrode is connected to the ground through a resistor R4; the drains of the PMOS transistors MP7 and MP6 are two output terminals of the auxiliary reference circuit and the exponential curvature compensation circuit, respectively.
3. The high-order curvature compensated bandgap reference voltage source according to claim 2, wherein the logarithmic curvature compensation circuit comprises PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, NPN transistors Q1, Q2 and a resistor R1, wherein the sources and the substrates of the PMOS transistors MP1, MP2 and MP3 are respectively connected to the external power supply, the gates of MP1 and MP2 are respectively connected to the two outputs of the auxiliary reference circuit and the exponential curvature compensation circuit, i.e. the drains of the PMOS transistors MP6 and MP7, the bases of the NPN transistors Q1 and Q2 are connected together, the emitter of Q2 is connected to ground, and the emitter of Q1 is connected to ground through a resistor R1; the drain of the PMOS tube MP1 is connected to the collector of Q1, and the drain of MP2 is connected to the collector of Q2; the gate of the NMOS transistor MN1 is connected to the collector of Q1, the drain is connected to an external power supply, the source is connected to the bases of Q1 and Q2, and the substrate is grounded; the gate of the NMOS transistor MN2 is connected with the collector of Q2, the source is connected with the emitter of Q1, the drain is connected with the drain of MP3, and the substrate is grounded; the drain electrode of the gate of the PMOS transistor MP3 is shorted, and the gate is the output end of the logarithmic curvature compensation circuit.
4. The high-order curvature compensated bandgap reference voltage source according to claim 2 or 3, wherein the current superposition circuit comprises resistors R5, R6 and PMOS transistors MP4, MP5 and MP9, wherein the sources of MP4, MP5 and MP9 are connected with the substrate to an external power supply, and the gates are connected with the output end of the logarithmic curvature compensation circuit; the drain electrode of the PMOS tube MP4 is connected with the drain electrode of MP5, the grid electrode is connected with the drain electrode of MP6, and the drain electrode is grounded through a resistor R6; the grid electrode of the PMOS tube MP9 is connected with the drain electrode of the MP6, the drain electrode is connected with the drain electrodes of the MP4 and the MP5 through a resistor R5, and the drain electrode voltage of the MP9 is the voltage converted after current superposition, namely the output voltage of the reference voltage source.
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| CN2011201471757U CN202075651U (en) | 2011-05-11 | 2011-05-11 | High-order curvature compensation band-gap resistance voltage source |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN117093049A (en) * | 2023-10-19 | 2023-11-21 | 上海芯龙半导体技术股份有限公司 | Reference voltage source circuit and parameter adjusting method |
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2011
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102193574A (en) * | 2011-05-11 | 2011-09-21 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN102193574B (en) * | 2011-05-11 | 2013-06-12 | 电子科技大学 | Band-gap reference voltage source with high-order curvature compensation |
| CN117093049A (en) * | 2023-10-19 | 2023-11-21 | 上海芯龙半导体技术股份有限公司 | Reference voltage source circuit and parameter adjusting method |
| CN117093049B (en) * | 2023-10-19 | 2023-12-22 | 上海芯龙半导体技术股份有限公司 | Reference voltage source circuit and parameter adjusting method |
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