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CN209561400U - 一种smt兼容替代sot563的封装 - Google Patents

一种smt兼容替代sot563的封装 Download PDF

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CN209561400U
CN209561400U CN201920602529.9U CN201920602529U CN209561400U CN 209561400 U CN209561400 U CN 209561400U CN 201920602529 U CN201920602529 U CN 201920602529U CN 209561400 U CN209561400 U CN 209561400U
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package
chip
metal framework
encapsulation
package casing
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胡明强
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Chengdu Ruiyuan Semiconductor Technology Co.,Ltd.
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Chengdu Ruiyuan Semiconductor Technology Co Ltd
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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Abstract

本实用新型涉及一种SMT兼容替代SOT563的封装，该封装通过设置封装管脚端面与封装外壳表面平齐，内腔容积更大，使得封装外壳中能够容纳更大尺寸的芯片，进而容纳更大尺寸的晶圆；本封装在封装过程中，无需将芯片进行倒装，减少芯片安装的步骤，封装成本低，封装时间更短，进一步提高了封装产能，可以替代现有行业内较为昂贵的SOT563封装形式的直流转直流的电源芯片。

Description

一种SMT兼容替代SOT563的封装
技术领域
本实用新型涉及芯片封装领域，更具体地说，涉及一种SMT兼容替代SOT563的封装。
背景技术
电子设备的小型化引导了更小型的半导体装置的设计和制造。半导体装置一般被封装用于各种电子产品。集成电路封装不仅直接影响着集成电路、电子模块乃至整机的性能，而且还制约着整个电子系统的小型化、低成本和可靠性。
现有的一些用户在设计时使用了SOT563的封装，由于SOT563的封装技术仅被一些行业内寡头掌握，封装成本过高，且SOT563封装采用的是芯片倒装的方式进行封装，封装的产能不足。SOT563封装后，封装管脚部分外露，由于线路板的设计已经定型，芯片封装内部空间小，无法融入更大尺寸的晶圆，不利于客户进行使用。
实用新型内容
本实用新型要解决的技术问题在于，针对现有技术的上述缺陷，提供一种SMT兼容替代SOT563的封装，该封装成本较低，封装内部空间较大。
本实用新型解决其技术问题所采用的技术方案是：
提供一种SMT兼容替代SOT563的封装，包括：
封装外壳，所述封装外壳尺寸为1.6mm*1.6mm*0.75mm；所述封装外壳底部设有用于作为基板使用的金属框架；
端面与所述封装外壳侧面平齐、且用于提高更大内腔容积的多个封装管脚；多个所述封装管脚设置于封装外壳底部靠近金属框架的两侧，并阵列状地配置；
所述芯片固定在所述金属框架中部、且位于封装外壳中；
用于进行芯片表面电极及封装管脚电连接的多条键合线，多条所述键合线通过绑定方式焊接于所述芯片表面电极及所述封装管脚上；
所述封装管脚宽度为0.2mm-0.3mm，所述封装管脚长度为0.23mm-0.33mm；所述封装管脚的封装高度为0.5mm-1.0mm；
所述封装外壳任意边缘处设有一方向标识线。
进一步地，所述绑定方式为通过超声波加热的方式焊接。
进一步地，所述金属框架截面呈长方形；所述金属框架为铜框架，所述金属框架的厚度为0.17mm-0.25mm。
进一步地，所述金属框架远离芯片一面设有镀锡层。
进一步地，所述键合线为银金钯合金线或镀钯铜线，所述键合线的直径为25μm-35μm。
进一步地，所述封装还包括导电银浆，所述导电银浆填充于所述芯片与所述金属框架之间，且填满所述芯片与所述金属框架之间的间隙。
进一步地，所述方向标识线为激光镭射线。
进一步地，所述封装外壳表面设有标识处。
本实用新型还提供一种芯片尺寸封装结构的制备方法，所述芯片尺寸封装结构的制备方法包括如下步骤：
1)提供一封装外壳，所述封装外壳内设有用于作为基板使用的金属框架；
2)提供一种芯片，进行晶圆测试后，对芯片进行划片，在金属框架上点上导电银浆后，将芯片安装到金属框架上；
3)采用绑定方式，将芯片与金属框架上的封装管脚进行绑定键合；
4)将安装好的芯片及金属框架进行塑封、高温固化以及电镀；
5)封装完成后进行切割成型，测试打印编带。
优选地，步骤1)中金属框架为铜框架，所述金属框架的厚度为0.17mm-0.25mm；步骤2)中芯片固定到金属框架上，导电银浆填充于所述芯片与所述金属框架之间，且填满所述芯片与所述金属框架之间的间隙；步骤3)中封装管脚个数为六个，分布在芯片两侧，并阵列状地配置，采用绑定方式于所述芯片上形成多条键合线，键合线用于芯片表面电极与封装管脚的电连接，采用超声波加热的方式焊接在芯片表面及封装管脚上。
本实用新型的有益效果在于：通过设置封装管脚端面与封装外壳表面平齐，内腔容积更大，使得封装外壳中能够容纳更大尺寸的芯片，进而容纳更大尺寸的晶圆；本封装在封装过程中，无需将芯片进行倒装，减少芯片安装的步骤，封装成本低，封装时间更短，进一步提高了封装产能，可以替代现有行业内较为昂贵的SOT563封装形式的直流转直流的电源芯片。
附图说明
为了更清楚地说明本实用新型实施例或现有技术中的技术方案，下面将结合附图及实施例对本实用新型作进一步说明，下面描述中的附图仅仅是本实用新型的部分实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他附图：
图1为本实施例中一种SMT兼容替代SOT563的封装的内部结构示意图；
图2为本实施例中一种SMT兼容替代SOT563的封装的内部俯视示意图；
图3为本实施例中一种SMT兼容替代SOT563的封装尺寸的俯视示意图；
图4为本实施例中一种SMT兼容替代SOT563的封装尺寸的仰视示意图；
图5为本实施例中一种SMT兼容替代SOT563的封装尺寸的侧视示意图；
图6为本实施例中一号封装管脚与金属框架连接的结构示意图；
图7为本实施例中二号封装管脚与金属框架连接的结构示意图；
图8为本实施例中三号封装管脚与金属框架连接的结构示意图；
图9为本实施例中四号封装管脚与金属框架连接的结构示意图；
图10为本实施例中五号封装管脚与金属框架连接的结构示意图；
图11为本实施例中六号封装管脚与金属框架连接的结构示意图；
图12为本实施例中金属框架与封装管脚无连接的结构示意图。
具体实施方式
为了使本实用新型实施例的目的、技术方案和优点更加清楚，下面将结合本实用新型实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本实用新型的部分实施例，而不是全部实施例。基于本实用新型的实施例，本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本实用新型的保护范围。
本实用新型实施例提供一种SMT兼容替代SOT563的封装，结合图1至图2可得，包括：
封装外壳1，封装外壳1尺寸为1.6mm*1.6mm*0.75mm；封装外壳1底部设有用于作为基板使用的金属框架4；
端面与封装外壳1表面平齐、且用于提高更大内腔容积的多个封装管脚3；多个封装管脚3设置于封装外壳1底部靠近金属框架4的两侧，并阵列状地配置；
封装外壳1内靠近相对的封装管脚3之间设有可容纳更大尺寸的芯片2的内部腔槽；芯片2固定在金属框架4中部、且位于封装外壳1中；多个封装管脚3与芯片2表面电极之间通过多条键合线6电连接；
封装管脚3宽度为0.2mm-0.3mm，封装管脚3长度为0.23mm-0.33mm；封装管脚3的封装高度为0.5mm-1.0mm；
结合图3至图5，下表内数据为图3至图5各项标注数据范围：
尺寸位置 最小 标准 最大 单位
A 1.50 1.60 1.70 mm
B 1.50 1.60 1.70 mm
C 0.50 0.70 1.20 mm
D 0.25 0.30 0.35 mm
E 0.20 0.25 0.30 mm
F 0.15 0.20 0.25 mm
G 0.50 mm
H 0 0.05 mm
该封装将封装管脚3内置在封装外壳1中，并且通过绑定方式对芯片2表面电极与封装管脚3进行电连接，封装管脚3端面与封装外壳1侧面平齐，与SOT563封装的封装管脚3外露相比，本封装的内腔更大，封装外壳1中能够容纳更大尺寸的芯片2；采用本封装，芯片在封装时无需倒装，节省了大量封装时间，进一步提高封装产能，降低用户的封装成本。
上述实施例中，结合图3至图5以及表格所得，相邻的封装管脚3之间以间距为0.5mm进行阵列状排布；且本实施例中封装管脚3的宽度限制在0.2mm-0.3mm之内，封装管脚3的长度限制在0.23mm-0.33mm之内。
上述实施例中，结合图6至图12所示，封装管脚3与金属框架4中间部分的组合形式有多种，例如一号封装管脚31与金属框架4中部连接、二号封装管脚32与金属框架4中部连接、三号封装管脚33与金属框架4中部连接、四号封装管脚34与金属框架4中部连接、五号封装管脚35与金属框架4中部连接以及六号封装管脚36与金属框架5中部连接，或者是金属框架5中部与六个封装管脚3之间均无联系；
多条用于芯片表面电极与封装管脚3电连接的键合线6，键合线6通过绑定方式焊接于芯片与封装管脚3上；
封装外壳1任意边缘处设有一方向标识线11，设置方向标识线11可用于在安装芯片封装时，可以对芯片方向做出辨别，因芯片封装尺寸为1.6mm*1.6mm，为正方形，所以方向标识线11不可设置在芯片中部。
提供一个尺寸为1.6mm*1.6mm*0.75mm的封装外壳1，封装外壳1内设有用于作为基板使用的金属框架4，提供一种晶圆2，在进行晶圆测试后，对晶圆2进行划片，在金属框架4上点上导电银浆5后，将晶圆2固定在金属框架4上；采用绑定方式，将芯片与金属框架4上的封装管脚3通过键合线6进行绑定键合，将安装好的芯片2及金属框架4进行塑封、高温固化以及电镀；封装完成后进行切割成型，测试打印编带。
在进一步的实施例中，结合图1至图2所示，绑定方式为通过超声波加热的方式焊接。
在进一步的实施例中，结合图2所示，金属框架4截面呈长方形；金属框架4为铜框架，金属框架4的厚度为0.17mm-0.25mm，金属框架4选用铜框架，铜的导电性能较好，金属框架4与芯片2接触部分厚度为0.1-0.12mm。
在进一步的实施例中，金属框架4远离芯片2一面设有镀锡层，镀锡层可以使得芯片封装避免外界环境的影响，使得元器件在线路板上容易焊接以及提高导电性。
在进一步的实施例中，结合图2所得，键合线6为银金钯合金线或镀钯铜线，键合线6的直径为25μm-35μm，键合线6为半导体生产中必不可少的一种材料，键合线6用于替代传统金线，更为廉价。
在进一步的实施例中，结合图1所得，封装还包括导电银浆5，导电银浆5填充于晶圆2与金属框架4之间，且填满晶圆2与金属框架4之间的间隙，导电银浆5用于晶圆2与金属框架4之间的固定，型号可选择永固的S260或者其它组份及性能相近的导电银浆。
在进一步的实施例中，结合图2可得，方向标识线11为激光镭射线，用于辨别芯片2的方向，防止安装芯片封装时方向错误，损坏芯片。
在进一步的实施例中，结合图3可得，封装外壳1表面设有标识处12，用于将芯片封装的代号或名称打印在封装外壳1表面标识处。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本实用新型所附权利要求的保护范围。

Claims (8)

1.一种SMT兼容替代SOT563的封装，其特征在于：包括：
封装外壳，所述封装外壳尺寸为1.6mm*1.6mm*0.75mm；所述封装外壳底部设有用于作为基板使用的金属框架；
端面与所述封装外壳侧面平齐、且用于提高更大内腔容积的多个封装管脚；多个所述封装管脚设置于封装外壳底部靠近金属框架的两侧，并阵列状地配置；
芯片，所述芯片固定在所述金属框架中部、且位于封装外壳中；
用于进行芯片表面电极及封装管脚电连接的多条键合线，多条所述键合线通过绑定方式焊接于所述芯片表面电极及所述封装管脚上；
所述封装管脚宽度为0.2mm-0.3mm，所述封装管脚长度为0.23mm-0.33mm；所述封装管脚的封装高度为0.5mm-1.0mm；
所述封装外壳任意边缘处设有一方向标识线。
2.根据权利要求1所述的封装，其特征在于，所述绑定方式为通过超声波加热的方式焊接。
3.根据权利要求1所述的封装，其特征在于，所述金属框架截面呈长方形；所述金属框架为铜框架，所述金属框架的厚度为0.17mm-0.25mm。
4.根据权利要求3所述的封装，其特征在于：所述金属框架远离芯片一面设有镀锡层。
5.根据权利要求1所述的封装，其特征在于，所述键合线为银金钯合金线或镀钯铜线，所述键合线的直径为25μm-35μm。
6.根据权利要求1所述的封装，其特征在于，所述封装还包括导电银浆，所述导电银浆填充于所述芯片与所述金属框架之间，且填满所述芯片与所述金属框架之间的间隙。
7.根据权利要求1所述的封装，其特征在于，所述方向标识线为激光镭射线。
8.根据权利要求1所述的封装，其特征在于，所述封装外壳表面设有标识处。
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