CN205986799U - Heterogeneous non - overlap clock generation circuit - Google Patents
Heterogeneous non - overlap clock generation circuit Download PDFInfo
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- CN205986799U CN205986799U CN201620808827.XU CN201620808827U CN205986799U CN 205986799 U CN205986799 U CN 205986799U CN 201620808827 U CN201620808827 U CN 201620808827U CN 205986799 U CN205986799 U CN 205986799U
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Abstract
The utility model discloses a heterogeneous non - overlap clock generation circuit produces heterogeneous non - overlap clock signal by logic gate, utilize delay element to generate a time delay clock signal with the time delay of main clock signal to produce heterogeneous non - overlap clock through devices such as NAND gate, NOR gate and not gates, the time delay td through delay element adjusts, and td adjusts and adjusts through mode able to programme, has enlarged the range of application of circuit. Characteristics such as this circuit compares that traditional non - overlap clock signal circuit has simple structure, low power dissipation, the area occupied is little, the reliability is high, able to programme, portable.
Description
Technical field
This utility model belongs to design field in semiconductor integrated circuit, and more particularly, to a kind of multiphase non-overlapping clock produces
Circuit.
Background technology
In the circuit such as switching capacity and charge pump, requisite unit is non-overlapping clock signal generating circuit.Opening
Close and be frequently necessary in condenser network not overlap, using biphase, the work that clock carrys out control circuit, this clock phase has difference, is used for
Control different switches in out of phase work.
The function of non-overlapping clock signal generating circuit is to produce the clock signal not overlapped mutually, it is to avoid clock signal control
The switch of system is opened simultaneously, also due to a phase clock is more another mutually turning off in advance, decreases the shadow of the Charge injection effect of switch
Ring.Traditional non-overlapping clock signal generating circuit has that structure is relative complex, power consumption compared with high, area occupied is big, reliability is low,
Not transplantation, the defect such as non-programmable.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of multiphase non-overlapping clock generation circuit, structure letter
Single, low in energy consumption, area occupied is little, reliability is high, programmable, transplantation.
For solving above-mentioned technical problem, this utility model provides a kind of multiphase non-overlapping clock generation circuit, it is characterized in that,
Multiphase non-overlapping clock signal is produced by logic gates.
It is made up of the biphase non-overlapping clock signal generating circuit producing biphase non-overlapping clock signal, bag logic gates
Include first with door and1, the first not gate inv1, the second not gate inv2, the first phase inverter INV1, the 3rd phase inverter INV3, second with
Door and2, the 4th not gate inv4, the 5th not gate inv5 and the second phase inverter INV2；
, as a road input of first and door and1, first to be connected first non-with the output out1 of door and1 for input signal IN
The input of door inv1, the outfan of the first not gate inv1 connects the input of the second not gate inv2, and the second not gate inv2's is defeated
Go out end to be connected and another road input signal in4 simultaneously as second and door and2 with the input of the first phase inverter INV1, the
One phase inverter INV1 is output as the first clock signal CC0；
Input signal IN through signal after anti-phase for the 3rd phase inverter INV3 as second and door and2 a road input signal
in3；Second is connected the input of the 4th not gate inv4 with the output out2 of door and2, and the outfan of the 4th not gate inv4 connects the
The input of five not gate inv5, the outfan of the 5th not gate inv5 be connected with the input of the second phase inverter INV2 and simultaneously as
First and door and1 another road input signal in2, the second phase inverter INV2 is output as second clock signal CC1；
First clock signal CC0 and second clock signal CC1 are biphase non-overlapping clock signal.
It is made up of the four phase non-overlapping clock signal generating circuits producing four phase non-overlapping clock signals, bag logic gates
Include the first NAND gate G1, the second not gate G2, the 3rd NAND gate G3, four nor gate G4, the 5th nor gate G5 and the 6th not gate G6；
The signal of input includes master clock signal CLKA,
Ratio the first delay clock signal CLKB of master clock signal CLKA time delay the first setting time,
Ratio the second delay clock signal CLKC of first delay clock signal CLKB time delay the second setting time,
The 3rd delay clock signal CLKD than the second delay clock signal CLKC time delay the 3rd setting time；
Master clock signal CLKA and the 3rd delay clock signal CLKD is input to the input of the first NAND gate G1, first with
The outfan of not gate G1 is connected to the input of the second not gate G2, and the output end signal of the second not gate G2 is the first clock signal
CLKOUT1；
Second delay clock signal CLKC and the first delay clock signal CLKB is input to the input of the 3rd NAND gate G3,
The output end signal of the 3rd NAND gate G3 is second clock signal CLKOUT2；
3rd delay clock signal CLKD and master clock signal CLKA are input to the input of four nor gate G4, the 4th or
The output end signal of not gate G4 is the 3rd clock signal clk OUT3；
Second delay clock signal CLKC and the first delay clock signal CLKB is input to the input of the 5th nor gate G5,
The outfan of the 5th nor gate G5 is connected to the input of the 6th not gate G6, and the output end signal of the 6th not gate G6 is the 4th clock
Signal CLKOUT4；
When the first clock signal clk OUT1, second clock signal CLKOUT2, the 3rd clock signal clk OUT 3 and the 4th
Clock signal CLKOUT4 is four phase non-overlapping clock signals.
Master clock signal CLKA generates the first delay clock signal through first delay unit D1 time delay the first setting time
CLKB.
First delay clock signal CLKB is when second delay unit D2 time delay the second setting time generates the second time delay
Clock signal CLKC.
Second delay clock signal CLKC is when the second delay unit D3 time delay the 3rd setting time generates three time delays
Clock signal CLKD.
The beneficial effect that this utility model is reached：
Master clock signal time delay is generated one using delay unit by multiphase non-overlapping clock generation circuit of the present utility model
Individual delay clock signal, and multiphase non-overlapping clock is produced by devices such as NAND gate, nor gate and not gates, by delay unit
Time delay Td be adjusted, Td adjust adjusted by programmable mode, expand the range of application of circuit.
This circuit is compared traditional non-overlapping clock signal circuit and is had that structure is simple, low in energy consumption, area occupied is little, reliability
The features such as high, programmable, transplantation.
Brief description
Fig. 1 is biphase non-overlapping clock generation circuit described in the utility model.
Fig. 2 is NAND gate described in the utility model and clock.
Fig. 3 is biphase non-overlapping clock simulation result described in the utility model and partial enlarged drawing.
Fig. 4 is four phase non-overlapping clock signal generating circuit schematic diagrams described in utility model.
Fig. 5 is four phase non-overlapping clock signal generating circuit oscillograms described in the utility model.
Specific embodiment
Below in conjunction with the accompanying drawings this utility model is further described.Following examples are only used for this is clearly described
The technical scheme of utility model, and protection domain of the present utility model can not be limited with this.
Combine accompanying drawing below this utility model is entered taking the biphase and four phase non-overlapping clock signal generating circuits of one kind as a example
Row describes in detail.
Embodiment 1
A kind of biphase non-overlapping clock signal generating circuit.Circuit structure is as shown in Figure 1.
Switched-capacitor circuit is frequently necessary to do not overlap the work that clock carrys out control circuit, this two clocks using biphase
Phase is slightly larger than 180 degree, for controlling different switches in out of phase work.
The principle that non-overlapping clock produces is very simple, and for a NAND gate, its circuit structure is as shown in Figure 2.
To with door and1 for,
When with door output level by high step-down, input in1 and in2 need to simultaneously be high level can, be simultaneously entered in1 with
In2 due to feedback effect there is certain delay when, therefore level overturn when the t1 moment.
When with door output level by low uprising, it is that low level overturns that input in1 and in2 only needs one end, upset
Time is calculated as the t2 moment.
Input signal IN is as the road input in1 with door and1.With the output out1 of door and1 through not gate inv1 and non-
Signal in4 after door inv2, exports the first clock signal CC0, synchronous signal in4 is as with door and2's after inverted device INV1
Another road input signal.
To with door and2 for,
, there is certain delay, time delay is through not gate inv1 and inv2 in the signal of input in4 and output out1 homophase
Time, input in3 be the signal through one-level phase inverter INV3 for input signal IN, analysis process with door and1.
With the output out2 of the door and2 signal in2 after not gate inv4 and not gate inv5, export after inverted device INV2
Second clock signal CC1, synchronous signal in2 are as another road input in2 with door and2.
Sequential chart therefore from Fig. 2 understands, clock signal creates non-overlapping.
This circuit mainly realizes non-overlapping using the characteristic of NAND gate, and the non-overlapping time then by with, non-behind the door anti-
Phase device INV1, INV2 are determining.
Circuit result is as shown in figure 3, from the figure, it can be seen that this circuit structure can be very good to realize the non-friendship of clock
Folded.
Embodiment 2
As shown in figure 4, a kind of four phase non-overlapping clock signal generating circuits, this circuit include the first delay unit D1,
Two delay unit D2, the 3rd delay unit D3, NAND gate G1, not gate G2, NAND gate G3, nor gate G4, nor gate G5 and not gate
G6.
Wherein, master clock signal CLKA generates delay clock signal CLKB through the first delay unit D1,
Delay clock signal CLKB generates delay clock signal CLKC through the second delay unit D2,
Delay clock signal CLKC generates delay clock signal CLKD through the second delay unit D3.
Master clock signal CLKA and delay clock signal CLKD is input to the input of NAND gate G1, the output of NAND gate G1
End is connected to the input of not gate G2, and the output end signal of not gate G2 is the first clock signal clk OUT1；
Delay clock signal CLKC and delay clock signal CLKB are input to the input of NAND gate G3, NAND gate G3 defeated
Go out end signal and be second clock signal CLKOUT2；
Delay clock signal CLKD and master clock signal CLKA is input to the input of nor gate G4, the output of nor gate G4
End signal is the 3rd clock signal clk OUT3；
Delay clock signal CLKC and delay clock signal CLKB is input to the input of nor gate G5, and nor gate G5's is defeated
Go out the input that end is connected to not gate G6, the output end signal of not gate G6 is the 4th clock signal clk OUT4；
When the first clock signal clk OUT1, second clock signal CLKOUT2, the 3rd clock signal clk OUT 3 and the 4th
Clock signal CLKOUT4 is four phase non-overlapping clock signals.
It is adjusted by the time delay Td of the first delay unit D1, the second delay unit D2, the 3rd delay unit D3, Td adjusts
Section is adjusted by programmable mode, expands the range of application of circuit.
In conjunction with Fig. 5 oscillogram, the circuit diagram shown in Fig. 4 is specifically described.
1. master clock signal CLKA and delay clock signal CLKD are input to the input of NAND gate G1, NAND gate G1 defeated
Go out the input that end is connected to not gate G2, the output end signal of not gate G2 is the first clock signal clk OUT1.
Two input nand gate G1 truth tables are as shown in table 1.
When two inputs of two input nand gate G1 are all 1, it is output as 0；
When two inputs of two input nand gate G1 are all 0, it is output as 1；
When two inputs of two input nand gate G1 are 0 and 1 respectively, it is output as 1.
Table 1 NAND gate G1 truth table
Not gate G2 truth table is as shown in table 2.
When two input nand gate G1 are output as 1, not gate G2 is output as 0；
When two input nand gate G1 are output as 0, not gate G2 is output as 1.
Table 2 not gate G2 truth table
| Y | CLKOUT1 |
| 1 | 0 |
| 0 | 1 |
Therefore, the first clock signal clk OUT1 waveform is as shown in Figure 5.
2. delay clock signal CLKC and delay clock signal CLKB is input to the input of NAND gate G3, NAND gate G3
Output end signal is second clock signal CLKOUT2.
Two input nand gate G3 truth tables are as shown in table 3.
When two inputs of two input nand gate G3 are all 1, it is output as 0；
When two inputs of two input nand gate G3 are all 0, it is output as 1；
When two inputs of two input nand gate G3 are 0 and 1 respectively, it is output as 1.
Table 3 NAND gate G3 truth table
Therefore, second clock signal CLKOUT2 waveform is as shown in Figure 5.
3. delay clock signal CLKD and master clock signal CLKA is input to the input of nor gate G4, and nor gate G4's is defeated
Go out end signal and be the 3rd clock signal clk OUT3.
Two input nor gate G4 truth tables are as shown in table 4.
When two inputs of two input nor gate G4 are all 1, it is output as 0；
When two inputs of two input nor gate G4 are all 0, it is output as 1；
When two inputs of two input nor gate G4 are respectively 0 and 1, it is output as 0.
Table 4 nor gate G4 truth table
Therefore, the 3rd clock signal clk OUT3 waveform is as shown in Figure 5.
4. delay clock signal CLKC and delay clock signal CLKB is input to the input of nor gate G5, nor gate G5's
Outfan is connected to the input of not gate G6, and the output end signal of not gate G6 is the 4th clock signal clk OUT4.
Two input nor gate G5 truth tables are as shown in table 5.
When two inputs of two input nor gate G5 are all 1, it is output as 0；
When two inputs of two input nor gate G5 are all 0, it is output as 1；
When two inputs of two input nor gate G5 are 0 and 1 respectively, it is output as 0.
Table 5 nor gate G5 truth table
Not gate G6 truth table is as shown in table 6.
When two input nand gate G5 are output as 1, not gate G6 is output as 0；
When two input nand gate G5 are output as 0, not gate G6 is output as 1.
Table 6 not gate G6 truth table
| Y | CLKOUT4 |
| 1 | 0 |
| 0 | 1 |
Therefore, the 4th clock signal clk OUT4 waveform is as shown in Figure 5.
The above is only preferred implementation of the present utility model it is noted that common skill for the art
For art personnel, on the premise of without departing from this utility model know-why, some improvement can also be made and deform, these change
Enter and deform also to should be regarded as protection domain of the present utility model.
Claims (4)
1. a kind of multiphase non-overlapping clock generation circuit, is characterized in that, produces multiphase non-overlapping clock signal by logic gates；
It is made up of the biphase non-overlapping clock signal generating circuit producing biphase non-overlapping clock signal logic gates, including the
One and door and1, the first not gate inv1, the second not gate inv2, the first phase inverter INV1, the 3rd phase inverter INV3, second and door
And2, the 4th not gate inv4, the 5th not gate inv5 and the second phase inverter INV2；
As a road input of first and door and1, first is connected the first not gate with the output out1 of door and1 to input signal IN
The input of inv1, the outfan of the first not gate inv1 connects the input of the second not gate inv2, the output of the second not gate inv2
End is connected and another road input signal in4 simultaneously as second and door and2 with the input of the first phase inverter INV1, and first
Phase inverter INV1 is output as the first clock signal CC0；
Input signal IN through signal after anti-phase for the 3rd phase inverter INV3 as second and door and2 road input signal in3；
Second is connected the input of the 4th not gate inv4 with the output out2 of door and2, and the outfan connection the 5th of the 4th not gate inv4 is non-
The input of door inv5, the outfan of the 5th not gate inv5 is connected with the input of the second phase inverter INV2 and simultaneously as first
With another road input signal in2 of door and1, the second phase inverter INV2 is output as second clock signal CC1；
First clock signal CC0 and second clock signal CC1 are biphase non-overlapping clock signal；
Or, be made up of the four phase non-overlapping clock signal generating circuits producing four phase non-overlapping clock signals logic gates, bag
Include the first NAND gate G1, the second not gate G2, the 3rd NAND gate G3, four nor gate G4, the 5th nor gate G5 and the 6th not gate G6；
The signal of input includes master clock signal CLKA,
Ratio the first delay clock signal CLKB of master clock signal CLKA time delay the first setting time,
Ratio the second delay clock signal CLKC of first delay clock signal CLKB time delay the second setting time,
The 3rd delay clock signal CLKD than the second delay clock signal CLKC time delay the 3rd setting time；
Master clock signal CLKA and the 3rd delay clock signal CLKD is input to the input of the first NAND gate G1, the first NAND gate
The outfan of G1 is connected to the input of the second not gate G2, and the output end signal of the second not gate G2 is the first clock signal
CLKOUT1；
Second delay clock signal CLKC and the first delay clock signal CLKB is input to the input of the 3rd NAND gate G3, and the 3rd
The output end signal of NAND gate G3 is second clock signal CLKOUT2；
3rd delay clock signal CLKD and master clock signal CLKA is input to the input of four nor gate G4, four nor gate
The output end signal of G4 is the 3rd clock signal clk OUT3；
Second delay clock signal CLKC and the first delay clock signal CLKB is input to the input of the 5th nor gate G5, and the 5th
The outfan of nor gate G5 is connected to the input of the 6th not gate G6, and the output end signal of the 6th not gate G6 is the 4th clock signal
CLKOUT4；
First clock signal clk OUT1, second clock signal CLKOUT2, the 3rd clock signal clk OUT3 and the 4th clock signal
CLKOUT4 is four phase non-overlapping clock signals.
2. a kind of multiphase non-overlapping clock generation circuit according to claim 1, is characterized in that, master clock signal CLKA warp
Cross first delay unit D1 time delay the first setting time and generate the first delay clock signal CLKB.
3. a kind of multiphase non-overlapping clock generation circuit according to claim 1, is characterized in that, the first delay clock signal
CLKB generates the second delay clock signal CLKC through second delay unit D2 time delay the second setting time.
4. a kind of multiphase non-overlapping clock generation circuit according to claim 1, is characterized in that, the second delay clock signal
CLKC generates the 3rd delay clock signal CLKD through the second delay unit D3 time delay the 3rd setting time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620808827.XU CN205986799U (en) | 2016-07-28 | 2016-07-28 | Heterogeneous non - overlap clock generation circuit |
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|---|---|---|---|
| CN201620808827.XU CN205986799U (en) | 2016-07-28 | 2016-07-28 | Heterogeneous non - overlap clock generation circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108233899A (en) * | 2018-02-06 | 2018-06-29 | 深圳骏通微集成电路设计有限公司 | The non-overlapping clock generation circuit of two-phase |
| CN110417412A (en) * | 2019-08-19 | 2019-11-05 | 苏州迅芯微电子有限公司 | A kind of clock generation method, sequence circuit and analog-digital converter |
| CN111865271A (en) * | 2020-07-14 | 2020-10-30 | 江苏应能微电子有限公司 | Delay circuit, method, circuit for preventing signal from false triggering and integrated circuit |
| CN112953467A (en) * | 2019-11-26 | 2021-06-11 | 杭州可靠性仪器厂 | Waveform generation method and system of data signal |
-
2016
- 2016-07-28 CN CN201620808827.XU patent/CN205986799U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108233899A (en) * | 2018-02-06 | 2018-06-29 | 深圳骏通微集成电路设计有限公司 | The non-overlapping clock generation circuit of two-phase |
| CN110417412A (en) * | 2019-08-19 | 2019-11-05 | 苏州迅芯微电子有限公司 | A kind of clock generation method, sequence circuit and analog-digital converter |
| CN110417412B (en) * | 2019-08-19 | 2023-03-28 | 苏州迅芯微电子有限公司 | Clock generation method, time sequence circuit and analog-digital converter |
| CN112953467A (en) * | 2019-11-26 | 2021-06-11 | 杭州可靠性仪器厂 | Waveform generation method and system of data signal |
| CN111865271A (en) * | 2020-07-14 | 2020-10-30 | 江苏应能微电子有限公司 | Delay circuit, method, circuit for preventing signal from false triggering and integrated circuit |
| CN111865271B (en) * | 2020-07-14 | 2023-08-18 | 江苏应能微电子有限公司 | Delay circuit, delay method, signal false triggering prevention circuit and integrated circuit |
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Address after: 233040 No.10 Caiyuan Road, Bengbu City, Anhui Province Patentee after: Anhui North Microelectronics Research Institute Group Co.,Ltd. Address before: 233040 No.10 Caiyuan Road, Bengbu City, Anhui Province Patentee before: NORTH ELECTRON RESEARCH INSTITUTE ANHUI Co.,Ltd. |
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