CN108233899A - The non-overlapping clock generation circuit of two-phase - Google Patents
The non-overlapping clock generation circuit of two-phase Download PDFInfo
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- CN108233899A CN108233899A CN201810118872.6A CN201810118872A CN108233899A CN 108233899 A CN108233899 A CN 108233899A CN 201810118872 A CN201810118872 A CN 201810118872A CN 108233899 A CN108233899 A CN 108233899A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks
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- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The present invention provides a kind of non-overlapping clock generation circuit of two-phase, the circuit includes：For the signal input part of input clock signal, connection input terminal is for modulating the clock signal to obtain the first clock circuit of First partial signal, connection input terminal is for modulating the clock signal to obtain the second clock circuit of the second local signal, the first clock circuit is connected for exporting the first output terminal of First partial signal, connection second clock circuit is used to export the second output terminal of the second local signal.Present invention superposition circuit is less, and a clock signal just exports four sub-clock signals later merely through disagreement twice, one-shot change, and the output time delay of four sub-clock signals is had nothing in common with each other, aspect is being switched on-off for control circuit, node can be made not driven in synchronization by two voltage sources, and it provides and turns off clock in advance, reduce the influence with the relevant Charge injection effect of signal.
Description
Technical field
The present invention relates to clock or timing circuit more particularly to a kind of non-overlapping clock generation circuits of two-phase.
Background technology
In current IC design system, it is required for a kind of or even different multi-frequency clock signal (Clock
Signal)；And the action sequence and operating rate of IC system, all depend on the clock signal on the IC system
As benchmark, when the clock signal frequency in circuit system is faster, the operating rate of the circuit system is generally also opposite to get over
Soon, therefore, the quality of clock signal is considerable for circuit system, if in circuit system clock signal quality
It is not given special heed to and is handled with care, the lighter may cause the speed of circuit system that can not increase, and severe one will cause entire electricity
Road system can not act.
And in the clock signal quality on handling IC system, in addition to the accuracy of clock signal frequency is special
Outside paying attention to, the duty ratio (Duty Cycle) of also clock signal is also required to give special heed to.
With the progress of IC design technology, circuit design becomes to become increasingly complex, and circuit system is also relatively pass by more
Come huger, and the clock signal used on IC system must then be pluralized branch by disagreement, by the clock
Signal is sent to the position of each needs on IC system, as the foundation of the circuit system action sequence, however these
Branch is typically all overlapping；In well known technology, a clock signal by after multiple disagreement, clock signal
By by destruction in a way, this may cause the speed of circuit system that can not increase or even will cause entire electricity quality
Road system can not work well.
Invention content
The present invention is directed to the shortcomings that existing way, proposes a kind of non-overlapping clock generation circuit of two-phase, existing to solve
The above problem existing for technology.
According to an aspect of the invention, there is provided a kind of non-overlapping clock generation circuit of two-phase, includes at least：
Signal input part, for input clock signal；
First clock circuit, connection signal input terminal is for modulating the clock signal to obtain First partial signal；
Second clock circuit, connection signal input terminal is for modulating the clock signal to obtain the second local signal；
First output terminal, the first clock circuit of connection are used to export First partial signal；
Second output terminal, connection second clock circuit is for the second local signal of output.
Further, first clock circuit includes at least Delay Element, logic door component, the first delay unit and delays
Rush device.
Further, the Delay Element includes the first Delay Element, the second Delay Element and third Delay Element；
The logic door component includes the first logic gate and the second logic gate；
The buffer includes the first buffer and the second buffer；
The First partial signal includes second clock signal and third clock signal；
First output terminal includes the first clock signal output terminal and second clock signal output end；
The signal input part connects the input terminal of the first Delay Element to generate the first clock signal, the first Delay Element
Output terminal connect the first input end of the first logic gate, the output terminal of the first logic gate connects the input of the first delay unit
It holds, the input terminal of the output terminal of the first delay unit the second Delay Element of connection, the output terminal connection third of the second Delay Element
The input terminal of Delay Element, the output terminal of third Delay Element connect the first input end of the second logic gate, the second logic gate
First output terminal connects the input terminal of the first buffer, and the output terminal of the first buffer connects the first clock signal output terminal with defeated
Go out second clock signal；
The second input terminal connection second clock circuit of first logic gate simultaneously intersects at the first tie point；
The output terminal of first delay unit connects the second input terminal of the second logic gate；
The output terminal of second Delay Element connects the input terminal of the second buffer, the output terminal connection of the second buffer
Second clock signal output end is to export third clock signal；
The second clock circuit connects the second tie point between first Delay Element and the second buffer.
Preferably, the Delay Element is phase inverter.
Preferably, the logic door component is NAND gate.
Further, the second clock circuit includes at least Delay Element, logic door component, the second delay unit and delays
Rush device.
Further, the Delay Element includes the 4th Delay Element and the 5th Delay Element；
The logic door component includes third logic gate and the 4th logic gate；
The buffer includes third buffer, the 4th buffer and the 5th buffer；
Second local signal includes the 5th clock signal and the 6th clock signal；
The second output terminal includes third clock signal output terminal and the 4th clock signal output terminal；
The input terminal of signal input part connection third buffer to generate the 4th clock signal, third buffer it is defeated
Outlet connects the first input end of third logic gate, and the output terminal of third logic gate connects the input terminal of the second delay unit, the
The output terminal of two delay units connects the input terminal of the 4th Delay Element, and the output terminal of the 4th Delay Element connects the 5th delay group
The input terminal of part, the output terminal of the 5th Delay Element connect the first input end of the 4th logic gate, and the second of the 4th logic gate is defeated
Outlet connects the input terminal of the 4th buffer, and the output terminal of the 4th buffer connects third clock signal output terminal to export the 5th
Clock signal；
Second input terminal of the third logic gate connects the first clock circuit and intersects at the second tie point；Described second
The output terminal of delay unit connects the second input terminal of the 4th logic gate；
The output terminal of 4th Delay Element connects the input terminal of the 5th buffer, the output terminal connection of the 5th buffer
4th clock signal output terminal is to export the 6th clock signal；
First clock circuit connects the second tie point between the 5th Delay Element and the second buffer.
Preferably, the Delay Element is phase inverter.
Preferably, the logic door component is NAND gate.
According to another aspect of the present invention, a kind of non-overlapping clock generation circuit of two-phase is provided, including at least input
End, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, the first NAND gate, second with it is non-
Door, the first buffer, the second buffer, third buffer, the 4th buffer, the 5th buffer, the first delay unit, second prolong
Shi Danyuan, the first clock signal output terminal, second clock signal output end, third clock signal output terminal, the 4th clock signal
Output terminal：
The signal input part connects the input terminal of the first phase inverter to generate the first clock signal, the first phase inverter it is defeated
Outlet connects the first input end of the first NAND gate, and the output terminal of the first NAND gate connects the input terminal of the first delay unit, the
The output terminal of one delay unit connects the input terminal of the second phase inverter, and the output terminal of the second phase inverter connects the defeated of third phase inverter
Enter end, the output terminal of third phase inverter connects the first input end of the second NAND gate, the first output terminal connection of the second NAND gate
The input terminal of first buffer, the output terminal of the first buffer connect the first clock signal output terminal to export second clock letter
Number；
The output terminal of first delay unit connects the second input terminal of the second NAND gate；
The output terminal of second phase inverter connects the input terminal of the second buffer, the output terminal connection of the second buffer the
Two clock signal output terminals are to export third clock signal；
The second clock circuit connects the second tie point between first phase inverter and the second buffer；
The input terminal of signal input part connection third buffer to generate the 4th clock signal, third buffer it is defeated
Outlet connects the first input end of third NAND gate, and the output terminal of third NAND gate connects the input terminal of the second delay unit, the
The output terminal of two delay units connects the input terminal of the 4th phase inverter, and the output terminal of the 4th phase inverter connects the defeated of the 5th phase inverter
Enter end, the output terminal of the 5th phase inverter connects the first input end of the 4th NAND gate, the second output terminal connection of the 4th NAND gate
The input terminal of 4th buffer, the output terminal connection third clock signal output terminal of the 4th buffer are believed with exporting the 5th clock
Number；
Second input terminal of the third NAND gate connects the first clock circuit and intersects at the second tie point；Described second
The output terminal of delay unit connects the second input terminal of the 4th NAND gate；
The output terminal of 4th phase inverter connects the input terminal of the 5th buffer, the output terminal connection of the 5th buffer the
Four clock signal output terminals are to export the 6th clock signal；First clock circuit connects the 5th phase inverter and second and delays
Rush the second tie point between device.
Compared with prior art, the beneficial effects of the invention are as follows：Present invention superposition circuit is less, and a clock signal is only
Four sub-clock signals are just exported after disagreement twice, one-shot change, and the output time delay of four sub-clock signals respectively has
Difference is switching on-off aspect for control circuit, node can be made not driven in synchronization by two voltage sources, and
And provide and turn off clock in advance, reduce the influence with the relevant Charge injection effect of signal.
The additional aspect of the present invention and advantage will be set forth in part in the description, these will become from the following description
It obtains significantly or is recognized by the practice of the present invention.
Description of the drawings
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Significantly and it is readily appreciated that, wherein：
Fig. 1 is the non-overlapping clock generation circuit schematic diagram of a kind of two-phase in the embodiment of the present invention；
Fig. 2 is the sequence diagram one of the signal in the embodiment of the present invention；
Fig. 3 is the sequence diagram two of the signal in the embodiment of the present invention.
Specific embodiment
In order to which those skilled in the art is made to more fully understand the present invention program, below in conjunction in the embodiment of the present invention
The technical solution in the embodiment of the present invention is clearly and completely described in attached drawing.
In some flows of description in description and claims of this specification and above-mentioned attached drawing, contain according to
Particular order occur multiple operations, but it should be clearly understood that these operation can not herein occur according to it is suitable
Sequence is performed or is performed parallel, and the serial number such as 101,102 etc. of operation is only used for distinguishing each different operation, serial number
It itself does not represent and any performs sequence.In addition, these flows can include more or fewer operations, and these operations can
To perform or perform parallel in order.It should be noted that the descriptions such as " first " herein, " second ", are for distinguishing not
Same message, equipment, module etc., does not represent sequencing, it is different types also not limit " first " and " second ".
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only a part of example of the present invention, is implemented instead of all the embodiments.It is based on
Embodiment in the present invention, the every other implementation that those skilled in the art are obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
Those skilled in the art of the present technique are appreciated that unless otherwise defined all terms used herein are (including technology art
Language and scientific terminology), there is the meaning identical with the general understanding of the those of ordinary skill in fields of the present invention.Should also
Understand, those terms such as defined in the general dictionary, it should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless by specific definitions as here, the meaning of idealization or too formal otherwise will not be used
To explain.
Embodiment
As shown in Figure 1, providing a kind of non-overlapping clock generation circuit of two-phase of the embodiment of the present invention, include at least：
Signal input part, for input clock signal CLKIN；
First clock circuit, connection signal input terminal is for modulation clock signal CLKIN to obtain First partial signal；
Second clock circuit, connection signal input terminal is for modulation clock signal CLKIN to obtain the second local signal；
First output terminal, the first clock circuit of connection are used to export First partial signal；
Second output terminal, connection second clock circuit is for the second local signal of output.
Further, the first clock circuit includes at least Delay Element, logic door component, the first delay unit and buffering
Device.
Further, there are three Delay Elements, respectively the first Delay Element 1, the second Delay Element 4 and third delay group
Part 5；
There are two logic door components, respectively the first logic gate 2 and the second logic gate 6；
There are two buffers, respectively the first buffer 7 and the second buffer 15；
There are two First partial signals, respectively second clock signal PHIE and third clock signal PH1；
There are two first output terminals, respectively the first clock signal output terminal and second clock signal output end；
Signal input part connects the input terminal of the first Delay Element 1 to generate the first clock signal clk 1, the first delay group
The output terminal of part 1 connects the first input end of the first logic gate 2, and the output terminal of the first logic gate 2 connects the first delay unit 3
Input terminal, the first delay unit 3 output terminal connect the input terminal of the second Delay Element 4, the output terminal of the second Delay Element 4 connects
Connecing the input terminal of third Delay Element 5, the output terminal of third Delay Element 5 connects the first input end of the second logic gate 6, and second
The output terminal of logic gate 6 connects the input terminal of the first buffer 7, and the first clock signal of output terminal connection of the first buffer 7 is defeated
Outlet is to export second clock signal PH1E；
The second input terminal connection second clock circuit of first logic gate 2 simultaneously intersects at the second tie point B；
The output terminal of first delay unit 3 connects the second input terminal of the second logic gate 6；
The output terminal of second Delay Element 4 connects the input terminal of the second buffer 15, and the output terminal of the second buffer 15 connects
Second clock signal output end is connect to export third clock signal PH1；
Second clock circuit connects the second tie point A between third Delay Element 5 and the second logic gate 6.
Preferably, Delay Element is phase inverter.
Preferably, logic door component is NAND gate.
Further, second clock circuit includes at least Delay Element, logic door component, the second delay unit and buffering
Device.
Further, there are two Delay Elements, respectively the 4th Delay Element and the 5th Delay Element；
There are two logic door components, respectively 9 and the 4th logic gate 13 of third logic gate；
There are three buffers, respectively third buffer 8, the 4th buffer 14 and the 5th buffer 16；
There are two second local signals, respectively the 5th clock signal PH2E and the 6th clock signal PH2；
There are two second output terminals, respectively third clock signal output terminal and the 4th clock signal output terminal；
Signal input part connects the input terminal of third buffer 8 to generate the 4th clock signal clk 2, third buffer 8
The first input end of output terminal connection third logic gate 9, the output terminal of third logic gate 9 connect the input of the second delay unit 10
It holds, the input terminal of the output terminal of the second delay unit 10 the 4th Delay Element 11 of connection, the output terminal of the 4th Delay Element 11 connects
The input terminal of the 5th Delay Element 12 is connect, the output terminal of the 5th Delay Element 12 connects the first input end of the 4th logic gate 13,
The output terminal of 4th logic gate 13 connects the input terminal of the 4th buffer 14, the output terminal connection third clock of the 4th buffer 14
Signal output end is to export the 5th clock signal PH2E；
Second input terminal of third logic gate 9 connects the first clock circuit and intersects at the second tie point A；
The output terminal of second delay unit 10 connects the second input terminal of the 4th logic gate 13；
The output terminal of 4th Delay Element 11 connects the input terminal of the 5th buffer 16, and the output terminal of the 5th buffer 16 connects
The 4th clock signal output terminal is connect to export the 6th clock signal PH2；
First clock circuit connects the first tie point B between the 5th Delay Element 12 and the 4th logic gate 13.
Preferably, Delay Element is phase inverter.
Preferably, logic door component is NAND gate.
A kind of non-overlapping clock generation circuit of two-phase, including at least input terminal, the first phase inverter B1, the second phase inverter B2,
Third phase inverter B4, the 4th phase inverter B3, the 5th phase inverter B5, the first NAND gate G1, the second NAND gate G3, third NAND gate
G2, the second NAND gate G4, the first buffer BUF1, the second buffer BUF2, third buffer BUF0, the 4th buffer BUF4,
5th buffer BUF3, the first delay unit DLY1, the second delay unit DLY2, the first clock signal output terminal, second clock
Signal output end, third clock signal output terminal, the 4th clock signal output terminal：
Signal input part connects the input terminal of the first phase inverter B1 to generate the first clock signal clk, the first phase inverter B1
Output terminal connect the first input end of the first NAND gate G1, the output terminal of the first NAND gate G1 connects the first delay unit DLY1
Input terminal, the first delay unit DLY1 output terminal connect the second phase inverter B2 input terminal, the output of the second phase inverter B2
The input terminal of end connection third phase inverter B4, the output terminal of third phase inverter B4 connect the first input end of the second NAND gate G3,
The first output terminal of second NAND gate G3 connects the input terminal of the first buffer BUF1, the output terminal connection of the first buffer BUF1
First clock signal output terminal is to export second clock signal PH1E；
The second input terminal connection second clock circuit of first NAND gate 2 simultaneously intersects at the first tie point B；
The output terminal of first delay unit DLY1 connects the second input terminal of the second NAND gate G3；
The output terminal of second phase inverter B2 connects the input terminal of the second buffer BUF2, the output terminal of the second buffer BUF2
Second clock signal output end is connected to export third clock signal PH1；
Second clock circuit connects the second tie point A between third phase inverter B4 and the second NAND gate 6；
Signal input part connects the input terminal of third buffer BUF0 to generate the 4th clock signal clk 2, third buffer
The first input end of the output terminal connection third NAND gate G2 of BUF0, the output terminal of third NAND gate G2 connect the second delay unit
The input terminal of DLY2, the second delay unit DLY2 output terminal connect the 4th phase inverter B3 input terminal, the 4th phase inverter B3's
Output terminal connects the input terminal of the 5th phase inverter B5, and the output terminal of the 5th phase inverter B5 connects the first input of the 4th NAND gate G4
End, the output terminal of the 4th NAND gate G4 connect the input terminal of the 4th buffer BUF4, the output terminal connection of the 4th buffer BUF4
Third clock signal output terminal is to export the 5th clock signal PH2E；
The second input terminal of third NAND gate G2 connects the first clock circuit and intersects at the second tie point A；
The output terminal of second delay unit DLY2 connects the second input terminal of the 4th NAND gate G4；
The output terminal of 4th phase inverter B3 connects the input terminal of the 5th buffer BUF3, the output terminal of the 5th buffer BUF3
The 4th clock signal output terminal is connected to export the 6th clock signal PH2；First clock circuit connects the 5th phase inverter B5 and the
The first tie point B between four logic gates 13.
Wherein, above-mentioned buffer is made of two phase inverters.
From the above mentioned, input terminal input clock signal, IN points of clock signal clk are two-way, wherein anti-by first all the way
Enter the first input end of the first NAND gate G1 after phase device B1 reversions, generate CLK1 clock signals；Pass through third buffer all the way
BUF0 generates CLK2 clock signals.CLK1 clock signals are by the first NAND gate G1, and the first time delay circuit unit DLY1, second is anti-
Signal A, signal A feedback access third NAND gates G2 are generated after phase device B2, third phase inverter B4.Similarly, CLK2 clock signals
By third NAND gate G2, signal B, letter are generated after the second time delay circuit unit DLY2, the 4th phase inverter B3, the 5th phase inverter B5
The first NAND gate G1 of number B feedback access.The output difference of first time delay circuit unit DLY1 and the second time delay circuit unit DLY2
For signal C and signal D.Signal A and signal C access the second NAND gate G3, using obtaining first after the second buffer BUF2
Non-overlapping clock PH1.After signal B and signal D access the 4th NAND gate G4, using obtaining second after the 5th buffer BUF3
Non-overlapping clock PH2.The output of second phase inverter B2 obtains first non-overlapping clock in advance after the first buffer BUF1
PH1E；The output of 4th phase inverter B3 obtains second non-overlapping clock PH2E in advance after the 4th buffer BUF4.
If the delay time of signal CLK1 to signal A is TD1, the delay time of signal CLK2 to signal B is TD2, then
The sequence diagram of signal CLK1, CLK2, A, B, PH1, PH2 are as shown in Figure 2.The pulse width of PH1 is T/2-TD2, and the pulse of PH2 is wide
It spends for T/2-TD1, wherein T is the period for inputting 50% duty cycle clock.
If the delay time of signal C to signal A is TDe, then the sequence diagram of signal C, A, PH1E, PH1 as shown in figure 3,
The failing edge of PH1E shifts to an earlier date TDe than PH1, but rising edge be while.Equally, if the delay time of signal D to signal B is TDe,
The failing edge of PH2E shifts to an earlier date TDe than PH2, but rising edge be while.
The non-overlapping clock generation circuit of two-phase is one of significant element module of analog circuit, is widely used in various switches
In condenser network.The non-overlapping clock of two-phase is used in control circuit switch on-off, and makes node in synchronization not by two electricity
The driving of potential source, and provide and turn off clock in advance, reduce the influence with the relevant Charge injection effect of signal.Two-phase is non-overlapping
Clock circuit can be widely used for the design of the switched-capacitor circuits such as sigma-delta modulator, pipeline ADC, wave filter.
In embodiment provided herein, it should be understood that disclosed circuit and component, it can be by other
Mode realize.For example, embodiment of the method described above is only schematical, for example, the clock letter of input terminal input
Number, only a kind of functional statement can have other form of presentation, such as multiple components or circuit can in actual implementation
To combine or be desirably integrated into together or some features can be ignored.Institute's circuit can also be or may not be physics
It is upper separated, you can be located at an integrated system or can also be distributed in multiple systems.It can be according to the actual needs
Some or all of unit therein is selected to realize the purpose of this embodiment scheme.The above is only that the part of the present invention is real
Apply mode, it is noted that for those skilled in the art, without departing from the principle of the present invention,
Several improvements and modifications can also be made, these improvements and modifications also should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of non-overlapping clock generation circuit of two-phase, which is characterized in that include at least：
Signal input part, for input clock signal；
First clock circuit, connection signal input terminal is for modulating the clock signal to obtain First partial signal；
Second clock circuit, connection signal input terminal is for modulating the clock signal to obtain the second local signal；
First output terminal, the first clock circuit of connection are used to export First partial signal；
Second output terminal, connection second clock circuit is for the second local signal of output.
2. circuit according to claim 1, which is characterized in that first clock circuit includes at least Delay Element, patrols
Collect door component, the first delay unit and buffer.
3. circuit according to claim 2, which is characterized in that the Delay Element prolongs including the first Delay Element, second
Slow component and third Delay Element；
The logic door component includes the first logic gate and the second logic gate；
The buffer includes the first buffer and the second buffer；
The First partial signal includes second clock signal and third clock signal；
First output terminal includes the first clock signal output terminal and second clock signal output end；
The signal input part connects the input terminal of the first Delay Element to generate the first clock signal, the first Delay Element it is defeated
Outlet connects the first input end of the first logic gate, and the output terminal of the first logic gate connects the input terminal of the first delay unit, the
The output terminal of one delay unit connects the input terminal of the second Delay Element, the output terminal connection third delay group of the second Delay Element
The input terminal of part, the output terminal of third Delay Element connect the first input end of the second logic gate, the output terminal of the second logic gate
The input terminal of the first buffer is connected, the output terminal of the first buffer connects the first clock signal output terminal to export second clock
Signal；
The second input terminal connection second clock circuit of first logic gate simultaneously intersects at the first tie point；
The output terminal of first delay unit connects the second input terminal of the second logic gate；
The output terminal of second Delay Element connects the input terminal of the second buffer, the output terminal connection second of the second buffer
Clock signal output terminal is to export third clock signal；
The second clock circuit connects the second tie point between the third Delay Element and the second logic gate.
4. the circuit according to Claims 2 or 3, which is characterized in that the Delay Element is phase inverter.
5. the circuit according to Claims 2 or 3, which is characterized in that the logic door component is NAND gate.
6. circuit according to claim 1, which is characterized in that the second clock circuit includes at least Delay Element, patrols
Collect door component, the second delay unit and buffer.
7. circuit according to claim 6, which is characterized in that the Delay Element prolongs including the 4th Delay Element and the 5th
Slow component；
The logic door component includes third logic gate and the 4th logic gate；
The buffer includes third buffer, the 4th buffer and the 5th buffer；
Second local signal includes the 5th clock signal and the 6th clock signal；
The second output terminal includes third clock signal output terminal and the 4th clock signal output terminal；
The signal input part connects the input terminal of third buffer to generate the 4th clock signal, the output terminal of third buffer
The first input end of third logic gate is connected, the input terminal of output terminal the second delay unit of connection of third logic gate, second prolong
The output terminal of Shi Danyuan connects the input terminal of the 4th Delay Element, and the output terminal of the 4th Delay Element connects the 5th Delay Element
Input terminal, the output terminal of the 5th Delay Element connect the first input end of the 4th logic gate, the output terminal connection of the 4th logic gate
The input terminal of 4th buffer, the output terminal connection third clock signal output terminal of the 4th buffer are believed with exporting the 5th clock
Number；
Second input terminal of the third logic gate connects the first clock circuit and intersects at the second tie point；
The output terminal of second delay unit connects the second input terminal of the 4th logic gate；
The output terminal of 4th Delay Element connects the input terminal of the 5th buffer, the output terminal connection the 4th of the 5th buffer
Clock signal output terminal is to export the 6th clock signal；
First clock circuit connects the first tie point between the 5th Delay Element and the 4th logic gate.
8. the circuit described according to claim 6 or 7, which is characterized in that the Delay Element is phase inverter.
9. the circuit described according to claim 6 or 7, which is characterized in that the logic door component is NAND gate.
10. a kind of non-overlapping clock generation circuit of two-phase, which is characterized in that including at least input terminal, the first phase inverter, second instead
Phase device, third phase inverter, the 4th phase inverter, the 5th phase inverter, the first NAND gate, the second NAND gate, the first buffer, second are delayed
Rush device, third buffer, the 4th buffer, the 5th buffer, the first delay unit, the second delay unit, the first clock signal
Output terminal, second clock signal output end, third clock signal output terminal, the 4th clock signal output terminal：
The signal input part connects the input terminal of the first phase inverter to generate the first clock signal, the output terminal of the first phase inverter
The first input end of the first NAND gate is connected, the input terminal of output terminal the first delay unit of connection of the first NAND gate, first prolong
The output terminal of Shi Danyuan connects the input terminal of the second phase inverter, the input of the output terminal connection third phase inverter of the second phase inverter
End, the output terminal of third phase inverter connect the first input end of the second NAND gate, the first output terminal connection of the second NAND gate the
The input terminal of one buffer, the output terminal of the first buffer connect the first clock signal output terminal to export second clock signal；
The second input terminal connection second clock circuit of first NAND gate simultaneously intersects at the first tie point；
The output terminal of first delay unit connects the second input terminal of the second NAND gate；
The output terminal of second phase inverter connects the input terminal of the second buffer, when the output terminal of the second buffer connects second
Clock signal output end is to export third clock signal；
The second clock circuit connects the second tie point between the third phase inverter and the second NAND gate；
The signal input part connects the input terminal of third buffer to generate the 4th clock signal, the output terminal of third buffer
The first input end of third NAND gate is connected, the input terminal of output terminal the second delay unit of connection of third NAND gate, second prolong
The output terminal of Shi Danyuan connects the input terminal of the 4th phase inverter, and the output terminal of the 4th phase inverter connects the input of the 5th phase inverter
End, the output terminal of the 5th phase inverter connect the first input end of the 4th NAND gate, and the output terminal connection the 4th of the 4th NAND gate is slow
The input terminal of device is rushed, the output terminal of the 4th buffer connects third clock signal output terminal to export the 5th clock signal；
Second input terminal of the third NAND gate connects the first clock circuit and intersects at the second tie point；
The output terminal of second delay unit connects the second input terminal of the 4th NAND gate；
The output terminal of 4th phase inverter connects the input terminal of the 5th buffer, when the output terminal of the 5th buffer connects the 4th
Clock signal output end is to export the 6th clock signal；First clock circuit connects the 5th phase inverter and the second buffer
Between the first tie point.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810118872.6A CN108233899A (en) | 2018-02-06 | 2018-02-06 | The non-overlapping clock generation circuit of two-phase |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810118872.6A CN108233899A (en) | 2018-02-06 | 2018-02-06 | The non-overlapping clock generation circuit of two-phase |
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| CN108233899A true CN108233899A (en) | 2018-06-29 |
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| CN201810118872.6A Pending CN108233899A (en) | 2018-02-06 | 2018-02-06 | The non-overlapping clock generation circuit of two-phase |
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| CN113193859A (en) * | 2021-04-23 | 2021-07-30 | 深圳市时代速信科技有限公司 | Negative pressure generating circuit |
| CN119232138A (en) * | 2024-12-05 | 2024-12-31 | 中茵微电子(南京)有限公司 | Digital-analog hybrid LDO (low dropout regulator) suitable for high-speed signal interface circuit and FinFet process |
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Application publication date: 20180629 |