CN205265662U - Pipeline type adc - Google Patents

Abstract

The utility model provides a pipeline type adc, including a plurality of flowing water levels, wherein, at least one flowing water level structure does: the series connection has mutual parallel connection's a plurality of sub - DAC between sub - ADC and amplifier, a plurality of sub - DAC still dispose a plurality of gating wares, each respectively the configuration of gating ware does: when during gating ware gating, rather than the correspondence sub - DAC is in mode, when when the gating ware cuts out, rather than the correspondence sub - DAC is in the wait mode. The utility model discloses a pipeline type adc, the adoption time domain technique of interweaving improves adc's sampling rate, has still remain the advantage of pipeline type adc's high accuracy simultaneously.

Description

Flow-line modulus converter

Technical field

The utility model relates to a kind of flow-line modulus converter, particularly a kind of based on timeThe flow-line modulus converter of territory interleaving technology.

Background technology

Analog-digital converter (ADC), for transferring analog signal to data signal, is widely used in eachPlant in data acquisition and communication system, and the sampling rate of ADC directly determines to processSignal bandwidth. Along with the continuous increase of data bandwidth, the requirement of the sampling rate to ADC alsoDay by day improve.

Existing ADC has multiple framework, as streamline (pipelined) type ADC, successively forceClosely (SAR) type ADC, quick flashing (flash) type ADC, time domain interweave (interleaved)Type ADC etc. In these frameworks, pipelined ad C can realize higher precision simultaneouslyAnd speed, thereby be used widely.

And time domain interweaves, framework is to utilize the ADC of multiple low sampling rates to form a high samplingThe ADC of speed, it is to improving the sampling rate successful of ADC. Such as, N is adoptedSample rate is that the low speed ADC of fs carries out after time domain interweaves, and can reach the sample rate of N × fs. SoAnd this framework has two significant problems: first, it is logical that it has comprised multiple (such as N) sonRoad, so power consumption and area are N times of each subchannel; Secondly, this N son is interchannelGain error (gainerror), offset voltage (offsetvoltage), sample time offset (timmingEtc. skew) factor can be introduced a lot of spuious (spur) in output spectrum, has greatly limitedThe precision of ADC, and in these all error sources, belong to again sample time offset the most difficult (because ofIts amplitude, frequency and manufacturing process and temperature with input signal is strongly relevant).

Therefore,, utilizing time domain to interweave in framework improves the sampling rate of ADC, needReduce various errors, to ensure sampling precision.

Utility model content

For this reason, the utility model provides a kind of flow-line modulus converter, comprises multiple streamWater level, wherein, described at least one, pipelining-stage is configured to: between sub-ADC and amplifier, go here and thereConnection is connected with the multiple sub-DAC of connection parallel with one another, and described multiple sub-DAC are configuration respectively alsoHave multiple gates, each described gate is configured to: in the time of described gate gating, right with itThe described sub-DAC answering is in mode of operation; In the time that described gate is closed, the institute corresponding with itState sub-DAC in standby mode.

Further, described at least one, pipelining-stage also comprises random number generator, at least oneDescribed pipelining-stage is controlled described multiple gating according to the random number of described random number generator outputThe gating of device and closing, the frequency of described random number generator output random number is each describedA random number of sampling period output of flow-line modulus converter. The value of described random numberNumber identical with the number of the described sub-DAC in standby mode, the value of described random numberCorresponding one by one with the described sub-DAC in standby mode, when described random number generator is exported certainWhen individual random number, described at least one pipelining-stage control corresponding with described certain random number described inThe described gate gating that sub-DAC configures is controlled other in described in standby mode simultaneouslyThe described gate that sub-DAC configures is closed.

Preferably, described random number generator is configured to adopt DEM algorithm to generate random number, instituteStating amplifier is operation transconductance amplifier.

Flow-line modulus converter of the present utility model, adopts time domain interleaving technology to improve mouldThe sampling rate of number converter has also retained the high-precision of flow-line modulus converter simultaneouslyAdvantage.

Brief description of the drawings

Fig. 1 is the structural representation of existing flow-line modulus converter;

Fig. 2 is a reality of a pipelining-stage of flow-line modulus converter of the present utility modelExecute routine structural representation;

Fig. 3 is the schematic diagram of an example of the work schedule of Fig. 2.

Detailed description of the invention

Below in conjunction with the drawings and specific embodiments to pipeline-type analog-to-digital conversion of the present utility modelDevice is described in further detail, but not as to restriction of the present utility model.

As shown in Figure 1, be the structural representation of existing flow-line modulus converter. Its bagDraw together pipelining-stage (for example, the first pipelining-stage 10, the second of input buffer 40, multiple cascadesWater level 20 etc.) and the FLASHADC30 of afterbody, the output letter of each pipelining-stageNumber VADC outputs to figure adjustment module 50, is finally spliced to form the numeral of this analog-digital converterSignal Vout output. The figure place of each pipelining-stage can be carried out value according to required precision, for example,The flow-line modulus converter that comprises 6 pipelining-stages, its first pipelining-stage 10 can be 4 ratiosSpy, the second pipelining-stage 20 is to the 6th pipelining-stage (not shown) and FLASHADC30Be 3 bits, the data signal Vout of final output is 16 bits.

Flow-line modulus converter of the present utility model, it is mainly characterized in that, at least oneThe structure of individual pipelining-stage has been made improvement. Figure 2 shows that a stream after the utility model improvesThe structural representation of an embodiment of water level. Be understandable that flowing water of the present utility modelLine style analog-digital converter can have part pipelining-stage to adopt this structure, and also all pipelining-stage is equalAdopt this structure. Preferably, each flowing water of flow-line modulus converter of the present utility modelLevel all adopts this structure.

As shown in Figure 2, be at least one stream of flow-line modulus converter of the present utility modelThe structural representation of water level. Between sub-ADC1 and amplifier 3, be connected in series with parallel with one anotherThe multiple sub-DAC connecting, Figure 2 shows that 3, i.e. sub-DAC2a, 2b, 2c. Each heightDAC2a, 2b, 2c receive respectively the signal of sub-ADC1 output, and by output separately respectivelySend into amplifier 3, the signal Vo after amplifier 3 amplifies outputs to next pipelining-stage. SonThe output signal of ADC1 is also sent into encoder 4, and the signal VADC after coding outputs to numeralCorrection module 50.

Multiple sub-DAC2a, 2b, 2c also dispose respectively multiple gates, as 2 be depicted as manyIndividual gating switch sw1, sw2, sw3. Each gate is configured to: when (the i.e. choosing of gate gatingOpen up and close sw1, sw2, sw3 closure) time, sub-DAC2a, 2b, the 2c place corresponding with itIn mode of operation; In the time that gate is closed (being that gating switch sw1, sw2, sw3 disconnect),Sub-DAC2a, the 2b corresponding with it, 2c are in standby mode (idlemode).

Each sub-DAC2a, 2b, 2c, in the time of mode of operation, within a work period, all comply withFollowing four the work phase places of inferior process: DAC reset phase (DACresetphase), DAC adoptSample phase (samplingphase), amplifier reset phase (OTAresetphase) and amplifier are builtVertical phase (OTAsettlingphase). Wherein, continuing of DAC reset phase and DAC sampling phaseThe summation of time and amplifier reset mutually and amplifier is set up the summation of the duration of phase,Be a sampling period of flow-line modulus converter, i.e. the mode of operation of every sub-DACContinue two sampling periods.

Wherein, DAC resets in order to remove residual on a upper phason DAC capacitor arrayStay electric charge, to reduce the distortion (distortion) in sampling process; In DAC sampling phase time,The electric capacity of sub-DAC is followed input signal, and finishes moment in sampling and " freeze " input voltage;Amplifier resets in order to know a upper phase place residual on OTA and feedback capacity CFBElectric charge, to reduce distortion; In the time that amplifier is set up phase (OTAsettlingphase), sonDAC array above transmits corresponding electric charge according to the Output rusults of sub-ADC to feedback capacity CFB,Set up output by OTA.

For each sub-DAC, once leaving standby mode, it enters mode of operation, necessaryWill be sequentially through above-mentioned four work phase places, these four work phase places have formed a complete workDo the cycle.

Further, this pipelining-stage also comprises random number generator 5, and this random number generator 5 is everyA random number of individual sampling period output, each sampling period of this pipelining-stage is random according to outputNumber is controlled the gating of multiple gates and is closed. It is corresponding with gate for the ease of random number,The number of the value of random number is identical with the number of the sub-DAC in standby mode, random numberMultiple values are corresponding one by one with the sub-DAC in standby mode, when random number generator 5 is exportedWhen certain random number, that choosing that the pipelining-stage control sub-DAC corresponding with this random number configuresLogical device gating, controls other gates that configure in the sub-DAC of standby mode simultaneously and closes.Preferably, random number generator 5 adopts dynamic random coupling (DEM) algorithm to generate random number.

In one embodiment, sub-ADC1 is multiple comparators and resistance string composition, sub-DAC2a, 2b, 2c are capacitor array respectively, and amplifier 3 is operation transconductance amplifier (OTA).

Be understandable that, although the number of the sub-DAC providing in the present embodiment is 3,Its number can be any more than one multiple.

So, each pipelining-stage of flow-line modulus converter of the present utility model comprises manyIndividual sub-DAC has formed multiple service aisles in each pipelining-stage, can select randomly at every turnSelect the service aisle that needs use, can be by spuious the beating being caused by sample time offset equal errorFall apart to the ground of making an uproar, thus the SFDR (SFDR) of raising analog-digital converter.

In addition, owing to having shared sub-ADC1 and amplifier 3 between multiple service aisles, thereforeArea and the power consumption of analog-digital converter are greatly reduced.

Each flowing water of flow-line modulus converter of the present utility model is described referring to Fig. 3Operation principle and the sequential of level. Wherein, the master clock that ADCclock is analog-digital converter, it is frequentlyRate equals the sample frequency of analog-digital converter. In figure, dash area represents that this sub-DAC is in waiting forPattern. Sub-ADC in Fig. 2 samples while being high at ADCclock, at ADCClock compares while being low, and Output rusults is to corresponding sub-DAC passage and encoder 4.

As shown in Figure 3, at sampling period T1, supposing sub-DAC<0>2a resets in DACMutually and DAC sampling phase, sub-DAC<1>2b sets up phase in reset phase and amplifier of amplifier,Sub-DAC<2>2c is in standby mode.

At sampling period T2, sub-DAC<0>2a enters amplifier reset mutually and amplifier is set up phaseIn the stage, it,, also in mode of operation, therefore can not be selected at when the sampling period, T2 startedIn the T2 cycle, carry out sampling task; And sub-DAC<1>2b is owing to executing a work weekPhase, thus its at sampling period T2 at first in standby mode, can be strobedCarry out sampling task; Sub-DAC<2>2c is due to always in standby mode, and therefore it also canTo be strobed to carry out sampling task. Analog-digital converter can produce according to random number generator 5Which sub-DAC is random number select carry out sampling. In this example, analog-digital converter is selectedSub-DAC<1>2b carries out the sampling task of sampling period T2, it enters DAC reset phaseWith the DAC sampling phase stage; Sub-DAC<2>2c keeps standby mode.

In like manner, in the time that the sampling period, T3 started, due to sub-DAC<0>2a completed a workDoing the cycle, therefore in idle pulley, sub-DAC<0>2a is the state that can be strobed; SonDAC<1>2b enters amplifier reset mutually and amplifier is set up the phase stage, and it is also in workPattern therefore can not be strobed within the T3 cycle; Meanwhile, sub-DAC<2>2c still inIdle pulley, can be strobed. In this example, in sampling period T3, sub-DAC<2>2c is strobed and starts to enter DAC reset mutually and the DAC sampling phase stage, and sub-DAC<0>2aIn standby mode.

In the time that the sampling period, T4 started, due to sub-DAC<0>2a is always in idle pulley,Its state for being strobed; Sub-DAC<1>2b executes a work period, enters skyNot busy pattern, the also state for being strobed; Sub-DAC<2>2c start to enter amplifier resetPhase and amplifier are set up the phase stage, and it, therefore can not be within the T4 cycle also in mode of operationBe strobed. In this example, in sampling period T3, sub-DAC<0>2a is strobed beginningEntering that DAC resets mutually and the DAC sampling phase stage, sub-DAC<1>2b is in wait mouldFormula.

The rest may be inferred, and said process has formed the complete work of a pipelining-stage of analog-digital converterMake sequential.

Although only comprise 3 service aisles in the embodiment shown in Fig. 2 and 3, comprise 3Sub-DAC, but be understandable that, can add more service aisle, introduce moreRedundant channel, has more service aisle for you to choose when each sampling period is started.So, just better to the interweave spuious inhibition that causes of time domain, but correspondingly, work is logicalRoad is more, just larger to expending of area and power consumption.

Above detailed description of the invention is only illustrative embodiments of the present utility model, can not be used forLimit the utility model, protection domain of the present utility model is defined by the claims. This areaTechnical staff can, in essence of the present utility model and protection domain, make the utility modelVarious amendments or be equal to replacement, these amendments or be equal to replacement and also should be considered as dropping on the utility modelProtection domain in.

Claims (5)

1. a flow-line modulus converter, comprises multiple pipelining-stages, it is characterized in that,

Described at least one, pipelining-stage is configured to: between sub-ADC and amplifier, be connected in series withThe multiple sub-DAC of connection parallel with one another, described multiple sub-DAC also dispose respectively multiple choosingsLogical device,

Each described gate is configured to: in the time of described gate gating, and the described son corresponding with itDAC is in mode of operation; In the time that described gate is closed, the described sub-DAC corresponding with itIn standby mode.

2. flow-line modulus converter according to claim 1, is characterized in that, extremelyA few described pipelining-stage also comprises random number generator, and described at least one, pipelining-stage is according to instituteState the random number of random number generator output and control the gating of described multiple gates and close,The frequency of described random number generator output random number is each described pipeline-type analog-to-digital conversionA random number of sampling period output of device.

3. flow-line modulus converter according to claim 2, is characterized in that, instituteThe number of value of stating random number is identical with the number of the described sub-DAC in standby mode, instituteState the value of random number corresponding one by one with the described sub-DAC in standby mode, when described randomNumber makers are while exporting certain random number, described at least one pipelining-stage control and described certain withThe described gate gating that the described sub-DAC that machine number is corresponding configures, control simultaneously other inThe described gate that the described sub-DAC of standby mode configures is closed.

4. flow-line modulus converter according to claim 2, is characterized in that, instituteStating random number generator is configured to adopt DEM algorithm to generate random number.

5. flow-line modulus converter according to claim 1, is characterized in that, instituteStating amplifier is operation transconductance amplifier.