CN1711637A - 包含由焊接凸起结构连接的电路元件的设备 - Google Patents
包含由焊接凸起结构连接的电路元件的设备 Download PDFInfo
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- CN1711637A CN1711637A CNA2003801028682A CN200380102868A CN1711637A CN 1711637 A CN1711637 A CN 1711637A CN A2003801028682 A CNA2003801028682 A CN A2003801028682A CN 200380102868 A CN200380102868 A CN 200380102868A CN 1711637 A CN1711637 A CN 1711637A
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- 239000010931 gold Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052737 gold Inorganic materials 0.000 claims abstract description 18
- 239000010936 titanium Substances 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000005496 eutectics Effects 0.000 claims abstract description 10
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 5
- 238000003466 welding Methods 0.000 claims description 29
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- 239000000470 constituent Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 9
- 238000000151 deposition Methods 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 4
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910015363 Au—Sn Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 3
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Abstract
一种电子设备,包括由焊接凸起结构连接的第一电路元件和第二电路元件,所述焊接凸起结构包括:一个小尺寸的焊接凸起(1),该电子设备具有形成在电路元件(10)上的金底座部分(2),形成在底座部分(2)上的镍阻挡层(3),以及形成在阻挡层(3)上的焊接部分(5)。该焊接部分(5)包括第一(6)和第二(8)金层,以及夹在它们中间的中间锡层(7)。第一、第二和中间层(6-8)中金和锡的相对质量为焊接部分(5)提供了符合低共熔金-锡组成物的组成物。可以通过以下步骤来制造焊接凸起(1):在电路元件(10)上沉积钛种子层,除去位于电路元件(10)上的接触衬垫(P)上的钛层部分,对构成焊接凸起(1)的层和构成焊接凸起的部分(2-8)进行电镀,以及除去种子层的剩余部分。这种焊接粘接剂的技术用于连接电子设备中的连接电路元件。这种电子设备适于在电信中使用,例如在移动终端中。
Description
发明领域
本发明涉及凸起焊接领域,特别是一种新的焊接凸起结构、一种形成新的焊接凸起结构的方法、一种使用新的焊接凸起结构来连接两个电路元件的方法、以及一种包含由所述焊接凸起结构连接的电路元件的设备。本发明在电信领域中发现一种特殊的应用,用于制造移动终端。
可以理解,本文中使用的词语“电路元件”是广义的,特别地,它包含组装基片等,和支承有效部件的元件。当将本发明应用于焊接微波电路元件时,本发明提供了特殊的优势。通过专利EP 1 024 531已经获知使用焊接凸起结构来连接电路。该专利涉及在微波频率中运行的电路。这些电路中正在越来越广泛的消费品中使用。大量微波电路的主要部件是单片微波集成电路MMIC。这种集成电路在其一面上具有所有的有效电路,称为“有效面”。当连接MMIC到其他元件时,例如,当将MMIC安装在基片上时,必须小心以确保寄生电容和电感很小。这促进了凸起焊接技术的使用。
在凸起焊接技术中,由导电材料制成的凸起形成在例如MMIC的第一电路元件上的接触垫上,使得第一电路元件与第二电路元件形成面对关系,典型地是一个安装基片,如电路板,以便凸起与第二电路元件上的各个导电轨或导电垫对准。将第一和第二电路元件聚集在一起,并通过施加压力或使用更常用的加热将凸起材料软化(通常采用在320℃的温度下维持10到20秒)来进行焊接。
传统的,用于焊接的凸起是球形或半球形。但也已经提议在柱状物的顶端提供一个半球状凸起或多层凸起,使用该柱状物确保了焊接的电路元件间的某个最小间隔。
当电路的集成度变得更高时,诸如MMIC之类的电路元件上的导电轨/垫的组装密度也相应变高。因此焊接凸起的尺寸应足够小以避免两个相邻导体/接触垫的意外连接,这也很重要。已知焊接凸起技术不总是允许形成足够小尺寸的凸起。
此外,用于形成焊接凸起的技术可以导致在其上形成凸起的电路元件的性质严重退化。该技术可能在所述电路元件的基片中产生缺陷,例如半导体基片,该缺陷还可能进一步扩展到基片上的电路层。同时,只要在设备中有一个不合格的焊接凸起就能够完全阻止设备进行工作。因此,焊接步骤是非常精密的操作。
由于上述缺陷,本发明设法提供一种改进的焊接凸起结构,该结构具有很小的尺寸并且可以保护下面电路元件特性的制造方法。
更特别的,本发明提供一种焊接凸起结构,其包括:形成在电路元件上、含有金的底座部分;形成在底座部分上的阻挡层;形成在阻挡层上的焊接部分,该焊接部分包括含有金的第一层、含有金的第二层,以及位于第一层和第二层之间含有锡的中间层;其中焊接部分中金和锡的相对质量被形成为使焊接部分的组成物符合低共熔的金-锡组成物。
使用根据本发明的焊接凸起结构能够使电路元件的所有触点同时焊接。此外,当将本发明的焊接凸起结构用于焊接微波电路元件时,可由此产生较低的寄生电感,并可以改进电路元件的耐热性。
典型地,焊接凸起的底座部分具有大约30μm的高度。有利地,阻挡层具有大约0.2μm的厚度。可以将能够通过电镀沉积的各种金属用于形成阻挡层;但用于此用途的优选材料为Ni。
为确保焊接部分的组成物符合低共熔的金-锡组成物,有利地,该第一层应为具有1.0到1.3μm厚的金层,第二层应为具有0.7到0.8μm厚的金层,以及中间层应为具有1.5到1.8μm范围厚的锡层。优选的,由金制成的第一层应约为1.15μm厚,由金制成的第二层应约为0.75μm厚,以及中间锡层应约为1.65μm厚。
使用上述焊接凸起结构可以形成极小尺寸的焊接凸起,特别是具有大约35μm的高度和大约60μm的直径。
具有上述结构的焊接凸起特别适于用在将MMIC凸起焊接到其他电路元件。
本发明还提供一种形成上述焊接凸起的方法,以及一种用这种焊接凸起来连接第一和第二电路元件的方法。
通过接下来由举例给出的优选实施例的详细描述以及通过附图的说明,本发明的上述和其他特征、功能及优点将变得更加清楚,其中:
图1示意性地示出根据本发明优选实施例的焊接凸起结构;
图2举例说明在根据优选方法的图1中焊接凸起结构的制作中包含的各步骤;以及
图3举例说明优选凸起焊接方法包含的各步骤,该方法用于使用本发明优选实施例的焊接凸起结构连接两个电路元件。
现在将参照图1描述根据本发明的焊接凸起结构优选实施例。
根据该优选实施例,根据本发明的焊接凸起1包括由金(Au)制成的圆柱或底座2,由镍(Ni)制成的阻挡层3,以及具有多层结构的焊接部分5。为了便于相关的光刻处理,Au圆柱2优选具有25到35μm的高度(例如30μm),特别是为了在圆柱2的电镀过程中保持光致抗蚀剂的完整性,Au圆柱2优选具有55到65μm的直径(例如50μm)。Ni阻挡层3优选很薄,约为0.2μm。然而,Ni层3的存在很重要,因为它将Au圆柱2从焊接部分5分开,确保在使用焊接凸起时在焊接处理中不包含Au圆柱2。
有利地,焊接部分5由下部Au层6、中间锡(Sn)层7和顶部Au层8的夹层结构组成。为了确保合适的可靠度,所有这些金属层都优选是纯的(纯度≥99.9%)。选择组成焊接部分5的层6、7、8的尺寸,使得焊接部分5中的Au和Sn的相对质量被认为是完全符合低共熔的Au-Sn组成物,也就是说具有较低并可靠可重现的熔点(280℃)。通过向凸起1的顶部提供相应于低共熔的Au-Sn组成物的具有夹层结构的焊接部分5,在相对低温下进行凸起焊接变得可能,因此避免了对所连接的电路元件造成损害。
层6、7和8的优选尺寸如下:
第一Au层(6): 1.0到1.3μm
中间Sn层(7): 1.5到1.8μm
第二Au层(8): 0.7到0.8μm
然而,应理解到也可以采取其它的尺寸,假设这些尺寸能够使多层焊接部分5符合低共熔组成物。
现在根据图2描述形成图1的焊接凸起结构的优选方法。在该描述中,假设在MMIC 10的有效表面9上形成一个焊接凸起1。该有效表面9具有一个接触衬垫P,该衬垫将用于通过焊接凸起1连接MMIC 10到另一个电路元件上。(当然,实际上,MMIC将具有大量接触衬垫,和同时为所有这些衬垫P形成焊接凸起1。)
参照图2A,通过任何合适的技术(溅射法、物理蒸发沉积等)将钛层(Ti)12沉淀在MMIC 10的有效表面9上。该Ti层12优选地具有0.5μm的厚度。但,Ti层12的厚度可以是从0.3到1.0μm。如果该层的厚度低于0.3μm,则电镀可能不均匀。另一方面,如果该层的厚度大于1.0μm,则Ti层可能被过度的过腐蚀。Ti层12将作为用于随后电镀处理的导电(种子(seed))层。有利的,使用仅由一种金属构成的种子层以使在凸起形成处理结束时简单地去除该层(所需要的仅是一个单独的蚀刻步骤)。由于钛可以轻松地从MMIC的有效表面9被腐蚀掉,而不会对该表面上的金轨产生损坏,因此钛是用于这种种子层的优选材料。而且,Ti具有到MMIC的有效表面的良好粘接。
接下来,如图2B所举例说明的,使用已知技术例如旋涂技术在Ti种子层12上提供一个厚的光致抗蚀剂层13,并通过已知的光刻法和腐蚀技术在光致抗蚀剂13中确定出开口(图2B中所示的单一开口15)。开口15设定将要形成的焊接凸起的直径。光致抗蚀剂层13通常具有40μm±3μm的厚度,以此使得光致抗蚀剂和Ti种子层12的合并厚度接近于40μm。如从图2B中所看到的,构图步骤使Ti种子层12的一部分在每个开口15的底部露出。通过任何适当的技术将Ti种子层的这些暴露部分除去,例如使用稀释的氢氟酸(HF)或者EDTA-H2O2(乙二胺四乙酸-过氧化氢)的组成物来进行腐蚀。由于HF的快速腐蚀速度以及它良好的选择性(在腐蚀过程中光致抗蚀剂可以保持完整性),因此优选HF。
在将开口15中暴露的Ti种子层部分除去之后,现在MMIC 10的接触衬垫P暴露出来,如图2C所示。接着可以使用已知的电镀方法控制在开口15中将多个金属层电镀到接触衬垫P上。首先,将相对厚的Au层2镀到接触衬垫P上,接下来是很薄的Ni阻挡层3、下部Au层6、中间Sn层7、以及上部Au层8。可选的,可使用其它技术进行沉积,例如上部Au层(物理蒸发沉积通常可适用于沉积上部Au层8)。最后所得到的结构如图2D所示。如上所述,控制下部Au层6、中间Sn层7和上部Au层8的尺寸,以使在考虑到全部夹层结构5时,其中的Au和Sn相对质量符合低共熔Au-Sn组成物。
一旦电镀完成,就除去光致抗蚀剂层13,例如通过剥落工艺以产生如图2E所示的结构。最后,通过使用稀释的HF或EDTA-H2O2进行腐蚀,再次除去Ti种子层的剩余部分。使用钛作为种子层12的显著优点是,腐蚀剂对MMIC的有效表面上的金轨基本上没有影响。此外,由于将种子层12整个移除,在形成焊接凸起之后的MMIC的属性符合它的设计值,而没有因为焊接凸起形成过程而产生实质的退化。经该工艺完成得到的焊接凸起结构如图2F所示。
现在将根据图3来描述优选的方法,该方法使用根据本发明优选实施例的焊接凸起1将MMIC 10连接到基片20上。
作为该工艺的第一步骤,在MMIC 10中提供一个具有图1所示结构的焊接凸起1。优选的,通过使用根据图2所述的焊接凸起制作过程来完成该步骤。
参照图3,使用上述焊接凸起来制造包括两个电路元件的设备,这两个电路元件由所述焊接凸起连接。图3A示意性说明了由MMIC 10构成的第一电路元件,该MMIC 10的有效表面9上具有两个焊接凸起1,以及MMIC 10将要连接到的基片20。图3中,为了提高清晰度,焊接凸起的高度是过度夸大的。虚线22示出了面向MMIC 10将要连接的基片20的区域。基片20上有终止于触点25的导电轨23。实际上,接触衬垫P、焊接凸起1以及触点25的数量要大于被简化以便于理解的图3中所示的数量。该基片也可以是集成电路。
如图3B中所示,在优选的凸起焊接工艺的开始,将MMIC 10的有效表面9转向面对基片20的表面。MMIC 10相对基片20放置,以使凸起1对准并接触基片上的触点25。可以采取常规的对准工艺。
采取加热处理,以使凸起的焊接部分5的层6、7、8熔化并混合,形成具有低共熔Au-Sn组成物的焊料5’,如图3C所示。该焊料5’形成了在触点25和焊接凸起1的主体(层2和3)之间的粘接剂。由于构成焊料部分5的层6-8的性质和厚度,为了在凸起主体2、3和触点25之间形成适合的粘接剂,施加280℃-320℃的温度便足够了。通常,用户施加该温度10到20秒。因此,避免了可能对MMIC或基片产生损害的更高温度。
以上,尽管根据本发明的优选实施例对本发明进行了描述,但应理解在不脱离如附加权利要求所定义的本发明的情况下,可以对优选实施例进行许多改变和发展。
例如,本发明不局限于包括在MMIC上形成焊接凸起的技术,该焊接凸起可以形成在其他电路元件上。此外,本发明不特别局限于对可以用于在带有焊接凸起1的电路元件上形成Ti种子层12的处理的考虑,或者是关于用于形成、构图、以及除去光致抗蚀剂层13的方法的考虑。此外,众所周知,可以在各种金属层2、3、6、7和8的电镀过程中使用各种操作条件。
相对于使用现有技术制造的设备,上述设备具有改进了的性能。特别是由于它们的性能同时被改进并更加均匀,因此它们更加可靠。它们显示出较低的寄生电容和改进的低电阻。因此,它们更适于制造移动终端,如移动电话或WAP终端,或者其它新的复杂的移动终端。终端越复杂,电子设备和由此焊接凸起的效率就越高和越可靠。同时,MMIC是特别适于在电信中使用的集成电路。因此,具有电子设备的移动终端,其中该电子设备包含使用本发明的焊接凸起连接到基片或其他集成电路上的MMIC,同时显示了优越的性能和可靠性。
Claims (11)
1、一种包括由焊接凸起结构连接的第一电路元件和第二电路元件的电子设备,所述焊接凸起结构包括:
形成在电路元件上并含有金的底座部分;
形成在底座部分上的阻挡层;
形成在阻挡层上的焊接部分,该焊接部分包括含有金的第一层、含有金的第二层,以及位于第一层和第二层之间含有锡的中间层;
其中焊接部分中金和锡的相对质量使得焊接部分的组成物符合低共熔金-锡组成物。
2、如权利要求1的设备,其中底座部分具有大约30μm的高度。
3、如权利要求1或2的设备,其中焊接部分的第一层的厚度在1.0到1.3μm的范围内,焊接部分的第二层的厚度在0.7到0.8μm厚的范围内,以及焊接部分的中间层的厚度在1.5到1.8μm的范围内。
4、如权利要求1、2或3的设备,其中焊接部分的第一层的厚度约为1.15μm,焊接部分的第二层的厚度约为0.75μm,以及焊接部分的中间层的厚度约为1.65μm。
5、根据权利要求1-4中任何一个的设备,其中焊接凸起的高度约为35μm,并且其直径约为60μm。
6、根据权利要求1-5中任何一个的设备,其中该凸起结构形成在单片微波集成电路上。
7、一种为根据权利要求1-5中任何一个设备形成焊接凸起结构的方法,该方法包括步骤:
(a)在电路元件上形成一个钛种子层;
(b)在对应于电路元件上的触点(P)的位置处除去种子层的一部分;
(c)在对应于电路元件上的触点、底座部分、阻挡层、含金的第一层、含锡的中间层、以及含金的第二层的位置上,执行可控的电镀处理以便相继电镀;
(d)除去钛种子层的剩余部分。
8、根据权利要求7的焊接凸起形成方法,其中步骤(b)包括:
在钛种子层上形成一个掩膜层,并对该掩膜层构图以定义至少一个开口;以及
除去暴露在该至少一个开口中的钛种子层部分。
9、一种连接第一和第二电路元件的凸起焊接方法,该方法包括步骤:
在第一电路元件的表面上形成根据权利要求1-6的任何一个的至少一个焊接凸起;
通过将该至少一个焊接凸起接触到第二电路元件的表面,使第一和第二电路元件形成面对关系;以及
在相应于金-锡低共熔温度的温度下进行加热处理。
10、如权利要求1-6之一的电子设备,其中由一个集成电路构成该第一电路元件,由一个第二集成电路或一个基片构成该第二电路元件,其中该第一和第二电路元件通过根据权利要求9的焊接凸起连接。
11、一种移动终端,包括如权利要求10的电子设备。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298719A (zh) * | 2016-09-13 | 2017-01-04 | 江苏纳沛斯半导体有限公司 | 金属凸块结构及其形成方法 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2009971B1 (en) * | 2006-04-17 | 2015-01-07 | DOWA Electronics Materials Co., Ltd. | Solder layer, substrate for device junction utilizing the same, and process for manufacturing the substrate |
JP5526336B2 (ja) | 2007-02-27 | 2014-06-18 | Dowaエレクトロニクス株式会社 | 半田層及びそれを用いたデバイス接合用基板並びにその製造方法 |
US8293587B2 (en) | 2007-10-11 | 2012-10-23 | International Business Machines Corporation | Multilayer pillar for reduced stress interconnect and method of making same |
US8240545B1 (en) | 2011-08-11 | 2012-08-14 | Western Digital (Fremont), Llc | Methods for minimizing component shift during soldering |
US9070387B1 (en) | 2013-08-23 | 2015-06-30 | Western Digital Technologies, Inc. | Integrated heat-assisted magnetic recording head/laser assembly |
US9042048B1 (en) | 2014-09-30 | 2015-05-26 | Western Digital (Fremont), Llc | Laser-ignited reactive HAMR bonding |
US9257138B1 (en) | 2014-10-28 | 2016-02-09 | Western Digital (Fremont), Llc | Slider assembly and method of manufacturing same |
KR102534735B1 (ko) | 2016-09-29 | 2023-05-19 | 삼성전자 주식회사 | 필름형 반도체 패키지 및 그 제조 방법 |
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Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197654A (en) * | 1991-11-15 | 1993-03-30 | Avishay Katz | Bonding method using solder composed of multiple alternating gold and tin layers |
US5559817A (en) * | 1994-11-23 | 1996-09-24 | Lucent Technologies Inc. | Complaint layer metallization |
US6007349A (en) * | 1996-01-04 | 1999-12-28 | Tessera, Inc. | Flexible contact post and post socket and associated methods therefor |
US6175287B1 (en) * | 1997-05-28 | 2001-01-16 | Raytheon Company | Direct backside interconnect for multiple chip assemblies |
US5990560A (en) * | 1997-10-22 | 1999-11-23 | Lucent Technologies Inc. | Method and compositions for achieving a kinetically controlled solder bond |
TW444288B (en) * | 1999-01-27 | 2001-07-01 | Shinko Electric Ind Co | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device |
GB0001918D0 (en) * | 2000-01-27 | 2000-03-22 | Marconi Caswell Ltd | Flip-chip bonding arrangement |
US20020146919A1 (en) * | 2000-12-29 | 2002-10-10 | Cohn Michael B. | Micromachined springs for strain relieved electrical connections to IC chips |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6740577B2 (en) * | 2002-05-21 | 2004-05-25 | St Assembly Test Services Pte Ltd | Method of forming a small pitch torch bump for mounting high-performance flip-flop devices |
-
2003
- 2003-10-31 CN CNA2003801028682A patent/CN1711637A/zh active Pending
- 2003-10-31 JP JP2004549471A patent/JP2006505935A/ja not_active Withdrawn
- 2003-10-31 EP EP03758525A patent/EP1563538A1/en not_active Withdrawn
- 2003-10-31 AU AU2003274550A patent/AU2003274550A1/en not_active Abandoned
- 2003-10-31 WO PCT/IB2003/004900 patent/WO2004042819A1/en active Application Filing
- 2003-10-31 US US10/561,577 patent/US20070273025A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106298719A (zh) * | 2016-09-13 | 2017-01-04 | 江苏纳沛斯半导体有限公司 | 金属凸块结构及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070273025A1 (en) | 2007-11-29 |
AU2003274550A1 (en) | 2004-06-07 |
EP1563538A1 (en) | 2005-08-17 |
JP2006505935A (ja) | 2006-02-16 |
WO2004042819A1 (en) | 2004-05-21 |
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