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CN1406452A - A method of forming an opening or cavity in a substrate for receiving an electronic component - Google Patents

A method of forming an opening or cavity in a substrate for receiving an electronic component Download PDF

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Publication number
CN1406452A
CN1406452A CN 01805707 CN01805707A CN1406452A CN 1406452 A CN1406452 A CN 1406452A CN 01805707 CN01805707 CN 01805707 CN 01805707 A CN01805707 A CN 01805707A CN 1406452 A CN1406452 A CN 1406452A
Authority
CN
China
Prior art keywords
substrate
perforate
depression
layer
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 01805707
Other languages
Chinese (zh)
Other versions
CN100366132C (en
Inventor
约翰·格里高利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stsatl
STS ATL Corp
Original Assignee
STS ATL Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0012754.8A external-priority patent/GB0012754D0/en
Application filed by STS ATL Corp filed Critical STS ATL Corp
Publication of CN1406452A publication Critical patent/CN1406452A/en
Application granted granted Critical
Publication of CN100366132C publication Critical patent/CN100366132C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0397—Tab
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Laser Beam Processing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A method of forming an opening or cavity in a substrate, for receiving an electronic component, consists of or includes providing a patterned opaque masking layer on or adjacent a first major surface of the substrate, the masking layer having an opening overlying the position where the cavity is to be made, removing material from the substrate by laser ablation through the opening thereby forming an opening or cavity of a suitable size for receiving said electronic component.

Description

Be used for holding the substrate formation perforate of electronic component or the method for depression
Technical field
The present invention relates to a kind of method that in substrate, forms perforate or depression.This substrate is preferably the substrate that can comprise electronic component or integrated circuit.An example of this substrate is printed circuit board (PCB) (PCB).
When electronic component when particularly the current densities of integrated circuit increases, with they are connected to printed circuit board (PCB) (PCB) on wiring or the relevant also corresponding increase of problem of conductor.When having a large amount of interconnection line (for example in the situation of microprogramming device), this problem especially severe.
Background technology
Existing welding and circuit joining technique are expensive, and need heavy instrument to obtain high efficiency in production technology.May need this scolding tin of heating in addition twice; At first when preparation PCB, scolding tin need be heated, and scolding tin need be heated once more when PCB goes up when element is installed in.
In the technology that is used for formation perforate on the substrate of electronic component is known, for example referring to U.S. Pat 3,480,836, wherein is disclosed in boring in advance on the substrate, the additional then lead with tap of projection on this depression.This technology is for example in U.S. Pat 4,927, and open in 491, wherein this substrate is a flexible belt.
Japan Patent 10098081 public use carbon gas lasers cut the peripheral groove that is used for perforate in having the substrate that is superimposed upon the Copper Foil on the both sides, remove remaining substrate material in second step.Then by photoetching to this Copper Foil composition, to form the lead-in wire of holding element.
Summary of the invention
The present invention is used for the interconnection line diameter that provides less on PCB, thereby it can do thinlyyer, and does not need to use the leaded chip carrier (PLCC) of synthetic plastic.The present invention can also be used to make the chip carrier with good characteristic and lower cost.
According to an aspect of the present invention, provide the method described in a kind of claim 1-8 at this.Provide a kind of claim 9 described substrate according to second aspect present invention at this.According to another aspect of the present invention, provide the equipment described in the claim 10.
Description of drawings
Illustrate the preferred embodiments of the present invention with reference to the accompanying drawings, wherein:
Fig. 1 illustrates the schematic diagram that is used for an embodiment of the device of formation interconnection line on substrate;
Fig. 2 a and 2b are installed in the cross section and the plan view of on-chip discrete component for using the device manufacturing shown in Fig. 1;
Fig. 3 a to 3c is the plan view that the example of interconnection line is shown; And
Fig. 4 illustrates the method that forms joint by a through hole.
Embodiment
Fig. 1 illustrates the whole diagrammatic sketch that is used for forming the device 10 of interconnection line on basic 12.Device 10 comprises the laser 14 that focuses on by suitable lens combination 16, and in use laser is reflected by minute surface 18.In the present embodiment, use the carbon dioxide laser of the beam diameter of power with 50-500 watt and 480 microns.But,, can use more high power and larger diameter in order to increase output variable.Excimer laser or YAG laser can be used as a kind of laser of replacement.
In order to understand this device fully, need combine with miscellaneous equipment and consider this device.Comprise the device that is used to transmit substrate at this, for example dull and stereotyped platform 24.Be used for removing from first material layer selectively the device of subregion.This can comprise optical image former (not shown) and etching tank (not shown).The device that is used to remove the partial volume of substrate can be a laser 14 or ion beam milling equipment (not shown) or plasma etching machine (not shown).The device that is used for removing from second surface material can be a kind of improved etching tank that can corrode electric conductor.These devices that combine with this device are controlled by a series of microprocessor (not shown).
The power output of laser 14 is controlled by microprocessor 20.Identical with the pulse duration and the energy of control laser 14,20 pairs of minute surfaces of microprocessor 18 are directed and can be used for 16 pairs of lasers of scioptics system 14 and focus on.
By can form the depression of different depth from a large amount of pulses of energy source or duration of increasing each pulse.Similarly, can make the array of a depression, number that caves in this array and size can change, to make different products or to hold different devices.
Substrate 12 is shown in Fig. 2 in further detail adopts lamination or belt form.For example two aspect 21a of the such metal material of copper (or aluminium) and 21b clamp by (PET) such flexible substrate that corrodible polymer constituted 12 of for example polyethylene (tri-thalmate).Because substrate 12 is flexible, so it can transmit on roller or cylinder 22a.Because substrate 12 is flexible, therefore at it with after element is connected, the substrate that comprises element can be on another roller 22b.
Although can adopt the thickness between 100 microns and 600 microns, in the present embodiment, the thickness of substrate is 190 microns.If insert a silicon then more satisfactory, this chip has the thickness similar with this substrate from back ground connection.In addition, select substrate thickness according to the thickness of semiconductor chip.
Can be by using adhesive a slice metal material that on a surface of substrate, superposes, the perhaps catalysis by base material and electroplate a layer thickness and cover the metal of this base material uniformly and cover the such nonmetal base material of PET substrate for example 12 with metal material.
Substrate 12 can be finished or " undressed " form imports with part.If it is unprocessed, then need substrate is handled.This realizes by covering this substrate at first with photoresist.Can or use other prior art to apply this photoresist by thin even spraying method as an interlayer.
Then, on two surfaces, optical imagery is carried out in conductor path, interconnection line and chips welding position.This is a conventional steps in printed circuit board (PCB) is handled.
Use optical imagery and etch processes, on the clad surface of substrate, form circuit pattern.This circuit pattern has additional position 52, and it is corresponding to the bonding pad size and the position that will be inserted into on-chip depression and be connected to the semiconductor element (not shown) of interconnection line.
On the side of the material relative, on zone, has the corresponding bonding pad of circuit pattern corresponding to the size of the semiconductor element that will install with circuit pattern.
In case remove a zone, the lower polymer layer of laser ablation substrate from the top material.Although above be, can use various other materials at as the PET of polymer used in the substrate and description.For example, liquid crystal polymer (LCP), polyamide, PEN/ polyethylene napathalmate, polyvinyl chloride and Mai La (trade mark) can be contained in or form this substrate.Be used to make material that the another kind of chip carrier is fit to and be the laminated material (a random strand aramidreinforced laminate material) that Thermount (trade mark)-a kind of aromatic polyamides at random strengthens from E.I.Du Pont Company, although this material has the edge die mould characteristic of non-constant, it is the material that a kind of very easy quilt melts.
Laser ablation carries out with very high speed, generally between 300 to 800 pulse per seconds.Speed and duration that microprocessor 20 changes from the pulse of laser 14.The evaporation rate for the particular characteristic of substrate material can be controlled and manage to this combination.Consequently melt and appear on the known region on accurate X and the Y position, have the predetermined degree of depth, be used for the given array of the depression of the capable and N row of the M that on the specific region, determines.
Step in manufacturing process is standardized.At first this substrate is applied coating, carry out optical imagery then.Then carry out etching and peel off.Then carry out the laser ablation of perforate or depression.Next procedure is that plasma and/or the wet-chemical of for example using liquor potassic permanganate are removed processing.After this removes step, metal is deposited on the mechanical tap structure (perhaps joint) that has just formed.This is to obtain by the alloy deposition from solution.This is an electrodeless processing, although also can use electro-plating method instead.Selected metal alloy must be compatible mutually with selected application and associated methods.Typical material comprises the material of tin, gold or money base.
In the laser ablation step process, the material that melts from depression can be deposited on the other parts of this substrate again.This deposit is removed in plasma and/or wet method removing step usually.But,, then be difficult to remove if the material that is melted is a polyimides.In order to help to remove this material, can be before the laser ablation step on substrate surface optional sacrifice layer of deposit.This sacrifice layer for example can be a photoresist.After melting, can and easily remove this aspect by plasma and/or wet method removing, and remove the material of any deposit once more simultaneously.
Then, the PCB cutting forming and finish processing.This step of overall modelling can be realized by CNC technological process, pressing mold or YAG laser modeling method.
Deposit is pre-determined by this etch processes.Before dielectric laser ablation, be separated from each other and be set to the corresponding series of finger-like connector that will be inserted in this depression or the mould and form by metal etching process with the joint of element or mould.As a kind of substitute mode, after dielectric substance was melted, this electrode can be by laser-induced thermal etching in the metal level of the bottom of this depression.In addition, by after forming this depression, can change etched in advance pattern (for example end) in this aspect with laser by removing tap or removing narrow structure.
The perforation substrate that is formed on a lip-deep joint is as a depression of shelving that is used to hold electronic component (50).Simple embodiment is the embodiment with one or two joint, and it for example is suitable for holding capacitor, and (Fig. 3 a).Transistor need form three joints, and its schematic diagram is shown in Fig. 3 b.Complex devices more, for example integrated circuit (IC), read-only memory (ROM), random-access memory (ram) or microprocessor need a plurality of joints (51).Its example is shown in Fig. 3 c.
Dual-use function is carried out in the long and narrow metal connection or the tap that form electronic joint.At first, they are as the electron path that leads to element.Secondly, because their mechanical performance, so their holding elements in process for making at least.For example, device can be installed compactly, and wherein the insertion of device causes protruding tap folding, produces the resilient clamp structure and makes this device location.Have been found that silver-plated joint advantageous particularly in should using now.
It is crucial being recorded in each lip-deep each etching area.But, should know the tolerance limit that can allow to a certain degree, and the mould position can be offset, so that the machinery that is fit to that can hold and keep electronic component depression to be provided.
Element for example can join to and caves on the adjacent electrode protrusion by ultra-sonic welded and/or pressurization welding method.In addition, the shrinkage crimping film can be tried out in element is pressed on the electrode, perhaps can use adhesive tape or tap.
The present invention can be used to create an array of depressions.An advantage of this structure is that a plurality of devices can be produced on the single substrate.
This substrate can be flexible, and can curl or folding, thus by reducing volume so that transportation.For example, before making and/or afterwards, this substrate can be kept on the spool.
Element can for example be placed in the preformed depression by air port (vacuum) or with hand by any existing technology.It is convenient especially to produce the structure that reduces air pressure on a surface.This pressure official post electronic component is inhaled in each depression, thereby this element (for example semiconductor chip or mould) can join on the substrate.
If the present invention is used to make the chip carrier circuit, each chip carrier can by die-cut on the relatively large thin slice of substrate or belt, transmit or cut.
Special benefits of the present invention is that it can obtain the chip carrier profile thinner than normal conditions.The typical chip carrier thickness of making according to the present invention is bigger 17 microns than mould thickness.But, the application of the invention, the part of substrate is removed to hold this element, and the carrier profile of gained is thinner than the profile that prior art obtained.
Many dissimilar electronic components can place this substrate perforate or depression.Comprising resistor, capacitor, inductor, integrated circuit, tuner, waveguide, piezoelectric device, coil and/or radiator.In addition, each perforate or depression can be suitable for holding electric-optical appliance, for example liquid crystal device or light-emitting diode.In the later case, for example can using, the such transparent material of indium tin oxide (ITO) is formed on bus on the surface.
In the above-described embodiments, extend through this substrate by the formed perforate of laser ablation.As a kind of alternative method, blank perforate or depression can be made by stopping to melt before being removed at all substrates.This technology is useful for make depression in multi-layer PCB.
Multi-layer PCB has the dielectric layer of semi-solid preparation, is generally 70 micron thickness, replaces with conductive metal layer.Can use laser ablation to handle and remove this material, in subsurface metal level, to expose bonding pad.Flip-chip mould with solder bump can place on this bonding pad, thereby when this assembly was heated, scolding tin flowed and engages this chip.The lower floor that an advantage of this technology is a multi-layer PCB can be used for the signal input and output to chip, and it shortens signal conductor length and reduces transmission delay.
Except the formation of the perforate that is used to install semiconductor or other device or depression, can also melt through hole simultaneously by PCB.In a preferred embodiment, as shown in Figure 4, long and narrow sheet metal or tap (30) are retained in the bottom of through hole (31).The degree of depth of this sheet or tapping ratio through hole is longer, and can have an end of formation jagged edges (32) or barb or burr.Can be by by to through hole air blowing body or liquid, perhaps use pin or similar solid instrument and this sheet or tap are pressed to this through hole.Be crimped into then towards the part of this sheet of the opposite side projection of through hole or tap and form through hole and not have on the bus of opposite side of PCB of common used plating step.In Fig. 4, this jagged edges be illustrated with substrate in can be meshed by laser ablation or formed second perforate of other method or depression (33).When being used for holding the perforate of electronic device or cave in not when this substrate cuts, this technology can also be used for conventional PCB well and make.
Although in the above-described embodiments, by carrying out laser ablation, select as another kind of by the patterned metal layer that substrate carried, can use to have the corresponding separating metal sheet in hole of cutting as the mask adjacent with substrate.
In above-mentioned example, this laser ablation step exposes the long and narrow joint that puts in the gained depression.This long and narrow metal parts is metal joint not necessarily, but it can form the mechanical structure that for example is used for pressure switch.
The present invention only describes by example, and does not for example have concrete disclosed replacement of equal value to make change to described embodiment by use.
At last, the application requires the file of priority to be contained in this for your guidance.

Claims (10)

1. one kind is used for being used to hold the substrate formation perforate of electronic component or the method for depression, and this method comprises the steps:
A) on first first type surface of substrate or near a patterned opaque mask layer is provided, this mask layer has and will form the equitant perforate in position of perforate or depression in substrate,
B) remove material through this perforate from substrate by laser ablation, thereby in this substrate, form perforate or depression with the appropriate size that is used to hold described electronic component.
2. method according to claim 1, wherein this perforate or depression only form by the laser ablation method.
3. method according to claim 1, wherein this substrate comprises insulating material and by mask layer that metal constituted.
4. method according to claim 1, wherein this substrate with the first first type surface facing surfaces on the carrying another patterned layer, described another patterned layer is formed by electric conducting material, this pattern is confirmed as making when perforate or when being recessed to form in this substrate, this another patterned layer keeps unaffected substantially, and at least a portion of described another patterned layer is crossed a side of this perforate or depression.
5. method according to claim 1, wherein this substrate with the first master meter facing surfaces on carry layer of conductive material, in the process that forms perforate or depression or afterwards, the part of this material is handled by laser ablation and removed selectively.
6. according to the described method of one of claim 1-4, wherein this patterned layer forms by being deposited on the substrate and removing from substrate selectively.
7. method according to claim 1, wherein this substrate is long and narrow and flexible.
8. method according to claim 1, wherein in the laser ablation process, provide a sacrifice layer to cover first patterned layer and/or this another patterned layer, make after forming perforate or depression, this sacrifice layer is removed, thereby removes material from perforate on sacrifice layer or depression in ablation procedure.
9. one kind has the substrate that forms according to according to the described method of claim 1-7.
10. one kind comprises the described substrate of claim 8 and is arranged in perforate or the device of the electronic component of depression.
CNB018057071A 2000-02-28 2001-02-26 A method of forming an opening or cavity in a substrate for receiving an electronic component Expired - Fee Related CN100366132C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51425700A 2000-02-28 2000-02-28
US09/514,257 2000-02-28
GBGB0012754.8A GB0012754D0 (en) 2000-02-28 2000-05-26 Apparatus for forming interconnects on a substrate and related method
GB0012754.8 2000-05-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN 200510055975 Division CN1668167A (en) 2000-02-28 2001-02-26 A method of manufacturing an electronic component and electronic component thereof

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Publication Number Publication Date
CN1406452A true CN1406452A (en) 2003-03-26
CN100366132C CN100366132C (en) 2008-01-30

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CN 200510055975 Pending CN1668167A (en) 2000-02-28 2001-02-26 A method of manufacturing an electronic component and electronic component thereof

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EP (1) EP1340414A2 (en)
JP (1) JP2003526205A (en)
CN (2) CN100366132C (en)
AU (1) AU2001242703A1 (en)
WO (1) WO2001065595A2 (en)

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Publication number Priority date Publication date Assignee Title
US8853592B2 (en) 2008-07-09 2014-10-07 Fei Company Method for laser machining a sample having a crystalline structure

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Publication number Priority date Publication date Assignee Title
DE10213881C1 (en) * 2002-03-27 2003-10-02 Infineon Technologies Ag Memory module has two semiconductor chips stacked on top of one another with underlying chip received in recess in surface of electronic circuit board
DE10213879C1 (en) * 2002-03-27 2003-07-10 Infineon Technologies Ag Electronic component has semiconductor chips fitted into respective recesses in surface of electronic circuit board
CN102110866B (en) * 2009-12-24 2013-08-28 深南电路有限公司 Manufacturing process of waveguide slot

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DE3608410A1 (en) * 1986-03-13 1987-09-17 Siemens Ag Production of fine structures for semiconductor contacts
JPH0793485B2 (en) * 1988-05-16 1995-10-09 カシオ計算機株式会社 How to connect IC unit
DE4326424A1 (en) * 1993-08-06 1995-02-09 Ant Nachrichtentech Process for the production of TAB film supports
GB2286787A (en) * 1994-02-26 1995-08-30 Oxford Lasers Ltd Selective machining by dual wavelength laser
GB9420182D0 (en) * 1994-10-06 1994-11-23 Int Computers Ltd Printed circuit manufacture
JP3593234B2 (en) * 1996-04-23 2004-11-24 日立電線株式会社 Method for manufacturing double-sided wiring tape carrier for semiconductor device
JPH1098081A (en) * 1996-09-24 1998-04-14 Hitachi Cable Ltd Tape carrier for mounting semiconductor chip and manufacturing method thereof
JP3506002B2 (en) * 1997-07-28 2004-03-15 松下電工株式会社 Manufacturing method of printed wiring board
FR2766654B1 (en) * 1997-07-28 2005-05-20 Matsushita Electric Works Ltd METHOD FOR MANUFACTURING A CIRCUIT BOARD

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8853592B2 (en) 2008-07-09 2014-10-07 Fei Company Method for laser machining a sample having a crystalline structure
CN102149510B (en) * 2008-07-09 2015-03-11 Fei公司 Method and apparatus for laser machining
US10493559B2 (en) 2008-07-09 2019-12-03 Fei Company Method and apparatus for laser machining

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CN1668167A (en) 2005-09-14
WO2001065595A2 (en) 2001-09-07
JP2003526205A (en) 2003-09-02
CN100366132C (en) 2008-01-30
WO2001065595A3 (en) 2002-01-03
EP1340414A2 (en) 2003-09-03
AU2001242703A1 (en) 2001-09-12

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