CN1231949C - Method for forming grid structure and autoregistered contact hole structure - Google Patents
Method for forming grid structure and autoregistered contact hole structure Download PDFInfo
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- CN1231949C CN1231949C CN 02145842 CN02145842A CN1231949C CN 1231949 C CN1231949 C CN 1231949C CN 02145842 CN02145842 CN 02145842 CN 02145842 A CN02145842 A CN 02145842A CN 1231949 C CN1231949 C CN 1231949C
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- conductive material
- material layer
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- aligned contacts
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Abstract
The present invention relates to a method for forming gate structures and a self-aligned contact hole structure, which comprises following steps that a first conductive layer is deposited on a substrate; a second conductive layer is deposited on the first conductive layer; an insulating layer is deposited on the second conductive layer; a photoengraving process and an etch process are carried out to remove the selecting part of the insulating layer; a part of the second conductive layer is etched without etching to the undersurface of the conductive layer; a part of the residual second conductive layer and the first conductive layer are etched to form a plurality of gate structures; the sidewall of each gate structure is formed with a sidewall spacing layer; a dielectric layer for covering all the gate structures is formed; the selected part of the dielectric layer among the gate structures is removed until the surface of the substrate is exposed to form a self-aligned hole; a metal layer for covering the hole is formed, and contact is formed on the surface of the exposed substrate between the metal layer and the substrate.
Description
Technical field
The present invention relates to a kind of method that forms grid structure and self-aligned contacts pore structure; Particularly, the present invention relates to a kind of removal prior art formed grid conductor/bit line contact hole (gate conductor/bitline contact, GC/CB) method of the technology permissible range (process window) that the shortcoming of short circuit and increase are bigger in semiconductor technology.
Background technology
Generally speaking, metal-oxide semiconductor (MOS) (MOS) device is made of metal level, silicon oxide layer and substrate.Because the tack of metal and oxide is not good, often use the conductive layer of polysilicon substituted metal with the grid structure of formation mos device.Yet, the shortcoming of polysilicon be its resistance than metal for high, though it can be by doping impurity reducing resistance, yet the conductivity that is produced still can't be as favorable conductive layer in the mos device.A kind of common solution is to increase the layer of metal silicide on polysilicon layer, and tungsten silicide (WSi) layer for example is with the conductivity of improvement grid structure.
In the prior art, the method for formation contact hole structure comprises the following steps: to form dielectric layer, forms contact hole (contact window) and forms metal level.When the Metal Contact (metal contact) that forms between metal level and substrate, the most widely used method is the autoregistration engraving method.
Figure 1A to Fig. 1 C is depicted as the conventional method that forms grid structure, and its process is as described below:
With reference to Figure 1A, at first prepare a substrate 2; Then form a plurality of separate gate structures on substrate 2, wherein each grid structure comprises one first conductive material layer 4, one second conductive material layer 6, an insulating barrier 8 and a side wall spacers (spacer) 10.After grid forms, form a dielectric layer 12 and cover entire substrate 2.
With reference to Figure 1B, then on dielectric layer 12, carry out photoetching and etching step and come out until the upper surface of substrate 2 between grid structure, to remove a selected part.This etching step is also effective to insulating barrier 8 and side wall spacers 10, but its rate of etch is slower, therefore has partial insulating layer 8 and side wall spacers 10 also etched.As a result, between grid structure, form contact hole 20, but its autoregistration forms the position of contact area to the substrate 2.As shown in FIG., contact area is formed at the exposed surface place of substrate 2, and its width is X.
With reference to figure 1C, then the upper surface in entire wafer deposits the metal level 14 of a specific thicknesses with the exposed surface that covers dielectric layer 12, the side wall spacers 10 and the substrate 2 of grid structure.Forming a width between metal level 14 and substrate 2 by this in self-aligned contact hole 20 is the Metal Contact of X.
The contact resistance of aforementioned self-aligned contacts (contact resistance) value and the contact area between metal level 14 and substrate 2 (zone that is indicated by width X just) are proportional.Can be in etching process by the method that prolongs etching period to increase contact area.If yet etching period control is improper, this method can cause insulating barrier 8 and side wall spacers 10 by over etching, and second conductive material layer 6 below it is exposed.The part that second conductive material layer 6 is exposed out can contact with metal level 14 and causes short circuit at point 16.
In order to improve above-mentioned traditional handicraft, the prior art United States Patent (USP) provides a kind of modification method (please refer to shown in Fig. 2 A to 2D) that forms the self-aligned contacts pore structure for the 5th, 989, No. 987, and this method is as follows:
With reference to figure 2A, at first prepare a substrate 2, be one first conductive material layer 4, one second conductive material layer 6 and an insulating barrier 8 in regular turn on it.Be etched to the surface of substrate 2 to form a plurality of separate gate structures by dry etching (dry etching).
With reference to figure 2B, then with NH
4OH, H
2O
2And H
2Etchant (etchant) etching second conductive material layer 6 that O is mixed.Though the purpose of this etchant is to be used for etching second conductive material layer 6, also can be with than first conductive material layer 4 of slow rate etching under it.After etching is finished, on each grid structure, form a side wall spacers 10.
With reference to figure 2C, then the upper surface in entire wafer forms a dielectric layer 12, to cover the exposed surface of all grid structures and substrate 2.Then removing the selected part of dielectric layer 12 between grid structure is exposed out until the upper surface of substrate 2.
With reference to figure 2D, then the upper surface in entire wafer deposits the metal level 14 of a specific thicknesses with the exposed surface that covers dielectric layer 12, the side wall spacers 10 and the substrate 2 of grid structure.In self-aligned contact hole 20, between metal level 14 and substrate 2, form a Metal Contact by this.
Above-mentioned prior art United States Patent (USP) the 5th, 989, how the advantage of No. 987 methods that provide has been the etching step at second conductive material layer 6, cause the width of second conductive material layer 6 narrow by this etching step, form big technology permissible range (processwindow) by this to avoid second conductive material layer 6 in point 16 places and metal level 14 short circuits than insulating barrier on it 8.
Yet, United States Patent (USP) the 5th, 989, the method of the formation self-aligned contacts pore structure that is provided for No. 987 has following shortcoming: (1) also can be with slower speed etching first conductive material layer 4 at the etching step of second conductive material layer 6, makes that its critical dimension (critical dimension) reduces, channel length (channel length) reduces and critical voltage (VT) reduces; (2) because the sectional area of second conductive material layer 6 diminishes, cause the resistance value of grid conductor to rise; (3) this etching step can cause the contact area of second conductive material layer 6 and first conductive material layer 4 to reduce, if contact area reduces when too much, then can cause and peel off (peeling) phenomenon.
Summary of the invention
Main purpose of the present invention is to provide a kind of method that forms grid structure and self-aligned contacts pore structure, the formed self-aligned contacts pore structure of this method can form sectional area, the resistance value of big technology permissible range, the critical dimension of keeping first conductive material layer, channel length, critical voltage, tungsten silicide layer and avoid second conductive material layer and first conductive material layer between peel off phenomenon, this method comprises:
(1) deposition one first conductive material layer on the entire upper surface of a substrate;
(2) deposition one second conductive material layer on the entire upper surface of this first conductive material layer;
(3) deposition one insulating barrier on the entire upper surface of this second conductive material layer;
(4) carry out photoetching and etch process to remove the selected part of this insulating barrier;
(5) use rate of etch to second conductive material layer to be higher than a etchant to the rate of etch of this insulating barrier, and the lower surface that is not etched to second conductive material layer as yet promptly stop etching with this second conductive material layer of etching;
(6) this second conductive material layer and this first conductive material layer implementation etch process to substrate are promptly stopped etching, to form a plurality of grid structures;
(7) on the sidewall of each grid structure, form a side wall spacers;
(8) form a dielectric layer that covers all grid structures;
(9) the selected part of removal dielectric layer between grid structure is exposed out to form the autoregistration hole until the surface of substrate; And
(10) metal level of the side wall spacers of the surface that is exposed out of formation covering dielectric layer, grid structure, and the substrate surface that is exposed out between this metal level and this substrate forms self-aligned contacts.
The present invention also provides a kind of method that forms grid structure, comprises the following steps:
(1) deposition one first conductive material layer on the entire upper surface of a substrate;
(2) deposition one second conductive material layer on the entire upper surface of this first conductive material layer;
(3) on the entire upper surface of this second conductive material layer, form a mask layer with this second conductive material layer of expose portion;
(4) use rate of etch to second conductive material layer to be higher than a etchant to the rate of etch of this mask layer, and the lower surface that is not etched to second conductive material layer as yet promptly stop etching with this second conductive material layer of etching; And
(5) this second conductive material layer and this first conductive material layer are carried out etch process to substrate, to form a plurality of grid structures.
The present invention also provides a kind of self-aligned contacts pore structure, comprising:
(1) one substrate;
(2) a plurality of grid structures that are formed on this substrate, wherein each grid structure comprises:
(a) one first conductive material layer that on the surface of this substrate, deposits;
(b) the one second conductive material layer Lower Half that deposits on the surface of this first conductive material layer has the width identical with this first conductive material layer, and its first half has than this first conductive material layer and the narrow width of this insulating barrier; And
(c) insulating barrier that on the entire upper surface of this second conductive material layer, deposits;
(3) one side wall spacers, it is formed on the sidewall of each grid structure;
(4) one dielectric layers, it covers the side that each those grid structures are not used to form the self-aligned contacts pore structure; And
(5) one metal levels, it covers those side wall spacers and this substrate of this dielectric layer, each those grid structures, and wherein this metal level does not contact with this second conductive material layer.
Description of drawings
The present invention describes by embodiment and accompanying drawing, so that technology contents of the present invention, feature and effect are easy to understanding, wherein:
Figure 1A to Fig. 1 C is for forming the conventional method of self-aligned contacts pore structure;
Fig. 2 A to Fig. 2 D is the method that the prior art United States Patent (USP) forms the self-aligned contacts pore structure for the 5th, 989, No. 987;
Fig. 3 A to Fig. 3 F is the structure according to gained after each step of the invention process grid structure and self-aligned contact hole structural approach; And
Fig. 4 is the flow chart of the method for grid structure formed according to the present invention and self-aligned contacts pore structure.
Description of reference numerals in the accompanying drawing is as follows:
2 substrates, 4 first conductive material layers
6 second conductive material layers, 8 insulating barriers
10 side wall spacers, 12 dielectric layers
14 metal levels, 16 points
20 self-aligned contact hole
Embodiment
The preferred embodiment of the present invention is by structure shown in Fig. 3 A to Fig. 3 F and method representation shown in Figure 4.
Preparing a substrate 2 during beginning, is one first conductive material layer 4, one second conductive material layer 6 and an insulating barrier 8 in regular turn on it.As shown in Figure 4, open grid conductor (GC) mask (step 401).With prior art United States Patent (USP) the 5th, 989, the method difference that forms self-aligned contacts for No. 987 is that method of the present invention is not directly to be etched to the surface of substrate 2 to form a plurality of separate gate structures by dry etching, promptly stop (step 402) but be etched to insulating barrier 8 lower surfaces earlier, as shown in Figure 3A.First conductive material layer 4 can be polysilicon (polysilicon) or amorphous silicon (amorphous silicon) layer, and second conductive material layer 6 can be metal silicide layer, as tungsten silicide (WSi) and insulating barrier can be silicon nitride (SiN) layer.And etch process can be dry etching.
As Fig. 3 B and shown in Figure 4, then with the upper surface (step 403) of a kind of etchant with etching second conductive material layer 6, wherein this etchant is higher than rate of etch to insulating barrier 8 to the rate of etch of second conductive material layer 6.Therefore please note that because second conductive material layer 6 is not etched to its lower surface first conductive material layer 4 does not contact with etchant and can be not etched.This etchant is preferably NH
4OH, H
2O
2And H
2The etchant that O is mixed, its temperature are preferably 55 degree Celsius approximately to 85 degree, and etching period is preferably about 5 to 30 minutes.And this is etched to isotropism (isotropic) etching.
As Fig. 3 C and shown in Figure 4, then carry out again etch process with etching second conductive material layer 6 and first conductive material layer 4 up to the upper surface (step 404) that is etched to substrate.Wherein this etch process can be dry etching.
As Fig. 3 D and shown in Figure 4, after etching is finished, then on the sidewall of each grid structure, form a side wall spacers 10 (step 405), this side wall spacers 10 can be silicon nitride (SiN).
As Fig. 3 E and shown in Figure 4, then the upper surface in entire wafer forms a dielectric layer 12, to cover the exposed surface of all self-aligned contacts pore structures and substrate 2.Then remove the dielectric layer 12 of the selected part between grid structure, be exposed out and form self-aligned contact hole 20 (step 406) until the upper surface of substrate 2 by photoetching and etching.
As Fig. 3 F and shown in Figure 4, then deposit the metal level 14 of a specific thicknesses, with the exposed surface that covers dielectric layer 12, the side wall spacers 10 and the substrate 2 of grid structure at the upper surface of entire wafer.In self-aligned contact hole 20, between metal level 14 and substrate 2, form a Metal Contact (step 407) by this.
Can solve conventional method and the prior art United States Patent (USP) the 5th that forms the self-aligned contacts pore structure according to method provided by the present invention, 989, form all shortcomings of the method for self-aligned contacts pore structure No. 987, because: (1) is owing to the first half etching of step 403 at second conductive material layer 6, therefore with the conventional method that forms grid structure relatively, can cause bigger contact aperture and avoid second conductive material layer 6 in point 16 places and metal level 14 short circuits; When (2) using the upper surface of etchant etching second conductive material layer 6, can not be etched to first conductive material layer 4 and make that its critical dimension (criticaldimension) reduces, channel length (channel length) reduces and critical voltage (VT) reduces; (3) owing to the contact area of second conductive material layer 6 and first conductive material layer 4 constant (because second conductive material layer, 6 Lower Halves and first conductive material layer 4 are all not etched), so the resistance value of grid conductor is almost constant; (4) can not cause during etching the contact area of second conductive material layer 6 and first conductive material layer 4 to reduce, therefore can not cause and peel off phenomenon.
Characteristics of the present invention and technology contents are fully open as above, and those skilled in the art can do various replacement or the modifications that do not deviate from spirit of the present invention according to open and instruction of the present invention.Therefore, protection scope of the present invention should not only limit to the disclosed embodiments, and should contain these replacements and modification.
Claims (28)
1. a method that forms grid structure comprises the following steps:
(1) deposition one first conductive material layer on the entire upper surface of a substrate;
(2) deposition one second conductive material layer on the entire upper surface of this first conductive material layer;
(3) on the entire upper surface of this second conductive material layer, form a mask layer with this second conductive material layer of expose portion;
(4) use rate of etch to second conductive material layer to be higher than a etchant to the rate of etch of this mask layer, and the lower surface that is not etched to second conductive material layer as yet promptly stop etching with this second conductive material layer of etching; And
(5) this second conductive material layer and this first conductive material layer are carried out etch process to substrate, to form a plurality of grid structures.
2. the method for formation grid structure as claimed in claim 1, the method that wherein forms this mask layer in the step (3) comprises the following steps:
(a) deposition one insulating barrier on the entire upper surface of this second conductive material layer; And
(b) carry out photoetching and etch process to remove the selected part of this insulating barrier.
3. the method for formation grid structure as claimed in claim 2, wherein the etch process of step (b) is a dry etching.
4. the method for formation grid structure as claimed in claim 1, wherein step (4) is etched to isotropic etching.
5. the method for formation grid structure as claimed in claim 1, wherein the etch process of step (5) is a dry etching.
6. the method for formation grid structure as claimed in claim 1, wherein the etchant of step (4) is NH
4OH, H
2O
2And H
2The O mixture.
7. the method for formation grid structure as claimed in claim 6, wherein this NH
4OH, H
2O
2And H
2The O mixture is carried out etching with temperature 55 degree Celsius to 85 degree.
8. the method for formation grid structure as claimed in claim 7, wherein etching period is 5 to 30 minutes.
9. a method that forms the self-aligned contacts pore structure comprises the following steps:
(1) deposition one first conductive material layer on the entire upper surface of a substrate;
(2) deposition one second conductive material layer on the entire upper surface of this first conductive material layer;
(3) deposition one insulating barrier on the entire upper surface of this second conductive material layer;
(4) carry out photoetching and etch process to remove the selected part of this insulating barrier;
(5) use rate of etch to second conductive material layer to be higher than a etchant to the rate of etch of this insulating barrier, and the lower surface that is not etched to second conductive material layer as yet promptly stop etching with this second conductive material layer of etching;
(6) this second conductive material layer and this first conductive material layer are carried out etch process to substrate, to form a plurality of grid structures;
(7) on the sidewall of each grid structure, form a side wall spacers;
(8) form a dielectric layer that covers all grid structures;
(9) the selected part of removal dielectric layer between grid structure is exposed out to form the autoregistration hole until the surface of substrate; And
(10) metal level of the side wall spacers of the surface that is exposed out of formation covering dielectric layer, grid structure, and the substrate surface that is exposed out between this metal level and this substrate forms self-aligned contacts.
10. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein this first conductive material layer is a polysilicon layer.
11. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein this first conductive material layer is an amorphous silicon layer.
12. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein this second conductive material layer is a metal silicide layer.
13. the method for formation self-aligned contacts pore structure as claimed in claim 12, wherein this metal silicide layer is a tungsten silicide layer.
14. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein this insulating barrier is a silicon nitride layer.
15. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein this side wall spacers is a silicon nitride layer.
16. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein the etch process of step (4) is a dry etching.
17. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein step (5) is etched to isotropic etching.
18. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein the etch process of step (6) is a dry etching.
19. the method for formation self-aligned contacts pore structure as claimed in claim 9, wherein the etchant of step (5) is NH
4OH, H
2O
2And H
2The O mixture.
20. the method for formation self-aligned contacts pore structure as claimed in claim 19, wherein this NH
4OH, H
2O
2And H
2The O mixture is carried out etching with temperature 55 degree Celsius to 85 degree.
21. the method for formation self-aligned contacts pore structure as claimed in claim 20, wherein etching period is 5 to 30 minutes.
22. a self-aligned contacts pore structure comprises:
(1) one substrate;
(2) a plurality of grid structures that are formed on this substrate, wherein each grid structure comprises:
(a) one first conductive material layer that on the surface of this substrate, deposits;
(b) the one second conductive material layer Lower Half that deposits on the surface of this first conductive material layer has the width identical with this first conductive material layer, and its first half has than this first conductive material layer and the narrow width of this insulating barrier; And
(c) insulating barrier that on the entire upper surface of this second conductive material layer, deposits;
(3) one side wall spacers, it is formed on the sidewall of each grid structure;
(4) one dielectric layers, it covers the side that each those grid structures are not used to form the self-aligned contacts pore structure; And
(5) one metal levels, it covers those side wall spacers and this substrate of this dielectric layer, each those grid structures, and wherein this metal level does not contact with this second conductive material layer.
23. self-aligned contacts pore structure as claimed in claim 22, wherein this first conductive material layer is a polysilicon layer.
24. self-aligned contacts pore structure as claimed in claim 22, wherein this first conductive material layer is an amorphous silicon layer.
25. self-aligned contacts pore structure as claimed in claim 22, wherein this second conductive material layer is a metal silicide layer.
26. self-aligned contacts pore structure as claimed in claim 25, wherein this metal silicide layer is a tungsten silicide layer.
27. self-aligned contacts pore structure as claimed in claim 22, wherein this insulating barrier is a silicon nitride layer.
28. self-aligned contacts pore structure as claimed in claim 22, wherein this side wall spacers is a silicon nitride layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02145842 CN1231949C (en) | 2002-10-15 | 2002-10-15 | Method for forming grid structure and autoregistered contact hole structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02145842 CN1231949C (en) | 2002-10-15 | 2002-10-15 | Method for forming grid structure and autoregistered contact hole structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1490846A CN1490846A (en) | 2004-04-21 |
| CN1231949C true CN1231949C (en) | 2005-12-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02145842 Expired - Fee Related CN1231949C (en) | 2002-10-15 | 2002-10-15 | Method for forming grid structure and autoregistered contact hole structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102723294B (en) | 2012-06-20 | 2015-04-22 | 上海华力微电子有限公司 | Method for detecting registration between contact hole and polycrystalline silicon gate |
| CN105575783B (en) * | 2014-10-09 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic device |
| US20200138512A1 (en) * | 2018-11-06 | 2020-05-07 | Biosense Webster (Israel) Ltd. | Attaining Higher Impedances for Large Indifferent Electrodes |
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