CN1146034C - Method for making buried microfine metal conductive wire - Google Patents
Method for making buried microfine metal conductive wire Download PDFInfo
- Publication number
- CN1146034C CN1146034C CNB011160705A CN01116070A CN1146034C CN 1146034 C CN1146034 C CN 1146034C CN B011160705 A CNB011160705 A CN B011160705A CN 01116070 A CN01116070 A CN 01116070A CN 1146034 C CN1146034 C CN 1146034C
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- Prior art keywords
- side wall
- width
- dielectric layer
- manufacture method
- insulation block
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Abstract
The present invention relates to a method for manufacturing buried fine metal connecting lines, wherein a repeated deposited film layer is formed on an insulation zone block which is convex at the surface of a semiconductor substrate; an etching program is carried out to define a side wall clearance wall on the insulation zone block so as to control the thickness of the deposited film layer and adjust the width of the side wall clearance wall, and thus, the side wall clearance wall which is positioned on the semiconductor substrate has the width which far smaller than the smallest tolerant line width of a micro-image process; the side wall clearance wall is used as an etching mask to etch the dielectric layer under the side wall clearance wall and manufacture a ditch structure with a fine width; a metal depositing and grinding program is carried out; a plurality of fine metal connecting lines are formed in a ditch to achieve the efficiency of further reducing the dimensions of elements.
Description
Technical field
The present invention relates to the semiconductor manufacturing, be meant a kind of method of utilizing repetitiousness to make side wall spacer especially, to define the manufacture method of most bar buried microfine metal conductive wires.
Background technology
Along with the progress that semi-conductor industry continues, in the exploitation and design of ultra-large type integrated circuit (ULSI), in order to meet the designer trends of high density integrated circuit, various size of component are all reduced to below the inferior micron.Although, by various size of component in the reduction wafer, can effectively produce the high semiconducter IC element of integrating integration, and further promote the operation usefulness of designed integrated circuit.But because element constantly dwindles, also cause when carrying out the related semiconductor processing procedure, having met with a unprecedented difficult problem, and the complexity of processing procedure also constantly improves.
Generally speaking, in manufacture of semiconductor, the main key of decision element integration is the ability of lithographic process.Wherein, can be to semiconductor substrate by lithographic process with the design transfer on the optical mask plate, with the pattern of each material layer in the decision integrated circuit, and form the framework of whole semiconductor circuit thus.Yet, along with the semiconductor element size continue dwindle, make design producing on the optical mask plate difficulty more that becomes.And, be limited by error, the image transmission of restriction, the exposure focusing of photoetching resolution accuracy, with can utilize dwindling of space, the degree of difficulty when all causing defining fine pattern heightens.
Particularly for integrated circuit, it is often in certain specific region on the wafer, forms millions of elements and is used for connecting the electronics syndeton of these elements.Therefore, on wafer, tend to deposit material layer miscellaneous and functional layer, to pile up required various element.Yet, when the density of element constantly promotes, will become very narrow and small in these interelement spaces.Thus, when making is connected in these interelement metal connecting lines, will meet with difficulty greatly.
In addition, because the granular of integrated circuit size makes operating voltage, the electric current of various element even the resistance value that is allowed all need meet the strict standard that requires.Therefore,, reduced the transmission speed of electric signal, in the design of integrated circuit, tended to the area of increase metal connecting line pattern as far as possible for fear of too high resistance.Thus, metal pattern can occupy most of area of crystal column surface, and hinders the making of other element.Therefore, how in limited space, make large-area metal connecting line,, become important topic anxious to be solved in the present manufacture of semiconductor to improve element operation speed.
Summary of the invention
Purpose of the present invention is providing a kind of manufacture method of buried microfine metal conductive wire, under the line width limit by lithographic process in present manufacture of semiconductor, produce the metal connecting line trickleer, that live width is littler, only need utilize lithographic process one time, define the insulation block that width is about 3X; Can reach the purpose of adjusting the side wall spacer width by the thickness of control depositional coating; By carrying out depositional coating and the program that defines side wall spacer, definable go out width less than the pattern of 3X on semiconductor substrate, make the method for the vertical trickle metal connecting line of most bars in dielectric layer, overcome the drawback of prior art, reach the purpose of further dwindling component size.
The object of the present invention is achieved like this: a kind of manufacture method of buried microfine metal conductive wire is characterized in that: it comprises the following steps:
(1) on semiconductor substrate, forms dielectric layer;
(2) make most insulation blocks in this dielectric layer upper surface, this each insulation block has the width of 3 units, and any two should the insulation block between, have the interval of 5 units of width;
(3) form the first side wall clearance wall on this insulation block sidewall, this first side wall clearance wall has the width of 1 unit;
(4) remove this majority insulation block;
(5) form second side wall spacer on the sidewall of this first side wall clearance wall, this second side wall spacer has the width of 1 unit;
(6) form filler in the space between two these adjacent second side wall spacer, this filler has the width of 1 unit;
(7) remove this second side wall spacer;
(8) use this first side wall clearance wall and this filler as etching mask, this dielectric layer is carried out anisotropic etching, in this dielectric layer, to form most irrigation canals and ditches structures;
(9) in this majority irrigation canals and ditches, fill metal, to form most strip metal lines.
This dielectric layer is made of silica material.This first side wall clearance wall and this filler are to use polycrystalline silicon material to constitute.This second side wall spacer is to use doped silicon oxide material to constitute.This each this irrigation canals and ditches structure has the width of 1 unit.Before making described insulation block, comprise forming silicon nitride layer that this silicon nitride layer uses as etching stopping layer, is positioned at this dielectric layer of below with protection in the step of this dielectric layer upper surface.This insulation block is to use doped silicon oxide material to constitute.This metal connecting line has the width of 1 unit.
Major advantage of the present invention is that method of the present invention can be produced the metal connecting line trickleer, that live width is littler under the line width limit of lithographic process in the present manufacture of semiconductor, only need utilize lithographic process one time, defines the insulation block that width is about 3X; Can pass through the thickness of control depositional coating, and reach the effect of adjusting the side wall spacer width; By carrying out the program of depositional coating and definition side wall spacer, definable go out width less than the pattern of 3X on semiconductor substrate, and reach the effect of further dwindling component size.
Further specify below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 is shown in the correlation step that forms dielectric layer, first insulating barrier, second insulating barrier and photoresist layer on the semiconductor substrate in regular turn for the present invention;
Fig. 2 is shown in the step of deposition first rete on the insulation block surface for the present invention;
Fig. 3 is shown in the step of definition the first side wall clearance wall on the insulation block sidewall for the present invention;
Fig. 4 shows the step that removes the insulation block for the present invention;
Fig. 5 is shown in the step that the first side wall clearance wall surface forms second rete for the present invention;
Fig. 6 is shown in the step of definition second side wall spacer on the first side wall clearance wall for the present invention;
Fig. 7 shows to cover the step that the first side wall clearance wall and second side wall spacer form the tertiary membrane layer for the present invention;
Fig. 8 is shown in the step that defines filler and the 3rd side wall spacer on second side wall spacer for the present invention;
Fig. 9 shows the step that removes second side wall spacer for the present invention;
Figure 10 is etched with most fine irrigation canals and ditches of definition in step wherein for the present invention shows to dielectric layer;
Figure 11 shows the step that removes etching mask on the dielectric layer for the present invention;
Figure 12 is shown in the step of depositing metal layers on the dielectric layer for the present invention;
Figure 13 is shown in the step of definition fine metal line in the dielectric layer for the present invention.
Embodiment
Consult Fig. 1, the invention provides a kind of method of trickle metal connecting line in irrigation canals and ditches that define.Wherein, the depositional coating of repetitiousness on the insulation block that is raised in the semiconductor substrate surface, and carry out etching program with the definition side wall spacer in the insulation block on.And, the thicknesses of layers of deposition is controlled, can effectively adjust the width of made side wall spacer.Thus, the side wall spacer that is positioned on the semiconductor substrate is had much smaller than the minimum width that allows live width of lithographic process.Then, utilize side wall spacer again, the dielectric layer under it is carried out etching, can produce the trickle irrigation canals and ditches structure of width as etching mask.Then, carry out the deposition and the polish process of metal again, definable is gone out to be arranged in the trickle metal wire of these irrigation canals and ditches.Relevant of the present invention be described in detail as follows described.
At first provide semiconductor ground 10 to deposit required rete.Wherein, this semiconductor substrate 10 can use have＜100〉crystal orientation monocrystalline silicon constituted.Generally speaking, the semi-conducting material of other kind also can be used as semiconductor substrate 10 uses as GaAs, germanium or the silicon base material that is positioned on the insulating barrier.In addition because the characteristic on semiconductor substrate 10 surfaces for the purpose of the present invention, can't cause special shadow noon, so its also can select to have＜110 or＜111〉crystal orientation monocrystal silicon structure.
Then, can form a dielectric layer 12 in these semiconductor substrate 10 upper surfaces.In preferred embodiment, this dielectric layer 12 is to be made of the silica material with 3000-12000 dust thickness.What specify is: before forming dielectric layer 12, formed on the surface of this semiconductor substrate 10 and made integrated circuit required various active member, passive device and peripheral circuits or the like.That is, had various required functional layer and material layer on these semiconductor substrate 10 surfaces.As for the deposition of this dielectric layer 12, then can use chemical vapour deposition technique (CVD) with tetraethyl-metasilicate (TEOS) at the about 600-800 of temperature ℃, form required silica between the about 0.1-10torr of pressure.
Subsequently, can form first insulating barrier 14 in dielectric layer 12 upper surfaces.In preferred embodiment, this first insulating barrier 14 can be made of the silicon nitride material with about 300-800 dust thickness.Wherein, can in about 400-450 ℃ stove, feed reacting gas and go out SiH
4, N
2O and NH
3And form required silicon nitride material.This first insulating barrier 14 can be used as etching stopping layer and uses, and to protect the dielectric layer 12 under it, avoids dielectric layer 12 in follow-up etching program, is subjected to corroding improperly.
Then, form second insulating barrier 16 again in above-mentioned first insulating barrier 14 tops.In preferred embodiment, this second insulating barrier 16 can be selected the about 500-3000 dust of thickness, and constitutes through the silica material of ion doping.So, when using hydrofluoric acid solution to be used as etchant, the etch-rate of this second insulating barrier 16 will be far above unadulterated silica material.Then, but painting photoresist layer 18 in these second insulating barrier, 16 upper surfaces, and by photoresist layer 18 is exposed, step such as development, cleaning, and define as shown in fig. 1 block pattern.
Consult Fig. 2, behind the pattern that defines photoresist layer 18, then use photoresist layer 18, second insulating barrier 16 is carried out etching program, till arriving at first insulating barrier, 14 upper surfaces as etching mask.So, the pattern on the photoresist layer 18 can be transferred in second insulating barrier 16, and most insulation blocks 20 among formation Fig. 2.Wherein, each the insulation block 20 have the width (3X) of 3 units approximately, and be positioned at any two the insulation blocks 20 gap widths be about 5 units (5X).Generally speaking, when second insulating barrier 16 is to use silica material to constitute, can select CCl
2F
2, CHF
3/ CF
4, CHF
3/ O
2, CH
3CHF
2, CF
4/ O
2Come as etchant.
Subsequently, can deposit the surface of first rete 22 uniformly in the insulation block 20 and first insulating barrier 14.In preferred embodiment, the optional majority crystal silicon of the material of this first rete 22.As for, the thickness of this first rete 22, then can be with reference to the width unit of above-mentioned insulation block 20, and be set in about 1 unit (1X).Preferable controllable thickness is between the 100-500 dust.
Consult Fig. 3, then, to first rete 22 carry out non-all to the etch-back program, to form the first side wall clearance wall 24 on the sidewall of the block 20 that insulate.Wherein, when the material of first rete 22 is when being made of polysilicon, can use SiCl
4/ Cl
2, BCl
3/ Cl
2, HBr/Cl
2/ O
2, HBr/O
2, Br
2/ SF
6Or SF
6As etchant, and utilize reactive ion etching art (RIE) to come first rete 22 is carried out etching program.
Consult Fig. 4, then carry out optionally etching program, to remove the insulation block 20 that is positioned on the semiconductor substrate 10.Thus, on first insulating barrier, 14 surfaces, will only stay the first side wall clearance wall 24 of about 1 unit of width (1X).And, be about about 3 units (3X) at the interval width of 24 of any two the first side wall clearance walls.Wherein, when the material of insulation block 20 is the silica that mixes, can use diluent hydrofluoric acid solution as etchant.By its high etching selectivity to doped silicon oxide material, can remove insulation during block 20, reduce that possible erosion damages to the first side wall clearance wall 24 and first insulating barrier 14.
Consult Fig. 5, after removing insulation block 20, then deposit second rete 26 uniformly in the outer surface of the first side wall clearance wall 24 and first insulating barrier 14.In preferred embodiment, this second rete 26 can be made of doped silicon oxide material.And the thickness of this second rete 26 of may command makes it be about 1 unit.Preferable thickness can be controlled between the 100-500 dust.
As shown in Figure 6, then second rete 26 is carried out the etch-back program, to form second side wall spacer 28 on the sidewall of each the first side wall clearance wall 24.Thus, owing to the first side wall clearance wall 24 and second side wall spacer 28, all has the width of about 1 unit.Therefore, for two second adjacent side wall spacer 28, gap length therebetween is about 1 unit.In the preferred embodiment, can utilize as the anisotropic etching processing procedure, for example the reactive ion etching art comes second rete 26 is carried out etching.As for the etchant that removes silicon dioxide, then can select CHF
3/ CF
4, CHF
3/ O
2, CF
4/ O
2, C
4F
8/ O
2, CH
2F
2Or C
4F
8
Consult Fig. 7, subsequently, deposit tertiary membrane layer 30 on first insulating barrier 14, the first side wall clearance wall 24 and second side wall spacer 28, and be filled in the space of second side wall spacer, 28 sides.In preferred embodiment, this tertiary membrane layer 30 has the thickness of 100-500 dust approximately, and the optional majority crystal silicon of its material.
As shown in Figure 8, then, tertiary membrane layer 30 is carried out the etch-back program, till arriving at the first side wall clearance wall 24 and second side wall spacer 28, to remove the part tertiary membrane layer 30 that is positioned at the first side wall clearance wall 24 and second side wall spacer, 28 upper surfaces.Thus, can in the space between two adjacent second side wall spacer, form filler 32.And,, form the 3rd side wall spacer 34 being positioned on second side wall spacer 28 at edge.
Consult Fig. 9, carry out an etching program optionally subsequently, to remove second side wall spacer 28 that is positioned at 32 in the first side wall clearance wall 24 and filler.Simultaneously, second side wall spacer 28 that is positioned at 34 of the first side wall clearance wall 24 and the 3rd side wall spacer also can be removed.Wherein, when the material of second side wall spacer 28 is doped silicon oxide, can use hydrofluoric acid vapor as etchant, so that it is removed fully.And,, therefore, optionally in the etching program, will be unlikely suffering erosion at this because the first side wall clearance wall 24, the 3rd side wall spacer 34 and filler 32 are to use polycrystalline silicon material to constitute.So, can form structure as shown in Figure 9.That is, between adjacent the first side wall clearance wall 24 and filler 32 (comprising the 3rd side wall spacer 34), all can have the space of about 1 unit width.
Consult Figure 10, then, use the first side wall clearance wall 24, filler 32 and the 3rd side wall spacer 34, to first insulating barrier 14 and the dielectric layer 12 under it that exposes to the open air as etching mask, carry out non-all to etching program, and form most narrow irrigation canals and ditches 36 in dielectric layer 12.Wherein, can use electric paste etching program, in regular turn first insulating barrier 14 and dielectric layer 12 be removed program as the reactive ion etching art.
Consult shown in Figure 11-12, then, remove the first side wall clearance wall 24, the 3rd side wall spacer 34, filler 32 and the first remaining insulating barrier 14 that are positioned at dielectric layer 12 tops.Then, depositing metal layers 38 and is filled in most the narrow irrigation canals and ditches 36, as shown in figure 12 on dielectric layer 12 again.Consult Figure 13, subsequently, metal level 38 is carried out the cmp program, till arriving at dielectric layer 12, to remove the part metals layer 38 that is positioned at dielectric layer 12 upper surfaces.So, be positioned in can formation figure that most bars of 12 of dielectric layers are atomic to bury metal connecting line 40 under thin, wherein, each bar irrigation canals and ditches metal connecting line 40 all has the width of about 1 unit, and 40 of two adjacent irrigation canals and ditches metal connecting lines, have width and be about the dielectric layer 12 of 1 unit, to provide 40 of metal connecting lines effectively to insulate and to separate effect.
Use method of the present invention, can under the line width limit of lithographic process in the present manufacture of semiconductor, produce the metal connecting line trickleer, that live width is littler 40.For example, in the above description, only need utilize lithographic process one time, define the insulation block 20 that width is about 3X.Then, can pass through the thickness of control depositional coating, and reach the effect of adjusting the side wall spacer width.So, by carrying out the program of depositional coating and definition side wall spacer, definable go out width less than the pattern of 3X on semiconductor substrate, and reach the purpose of further dwindling component size.
Though the present invention illustrates as above with preferred embodiment, so it is not in order to limit the present invention's spirit and invention entity.All modifications of being done in not breaking away from spirit of the present invention and scope all should be included within protection scope of the present invention.
Claims (8)
1, a kind of manufacture method of buried microfine metal conductive wire, it is characterized in that: it comprises the following steps:
(1) on semiconductor substrate, forms dielectric layer;
(2) make most insulation blocks in this dielectric layer upper surface, this each insulation block has the width of 3 units, and any two should the insulation block between, have the interval of 5 units of width;
(3) form the first side wall clearance wall on this insulation block example wall, this first side wall clearance wall has the width of 1 unit;
(4) remove this majority insulation block;
(5) form second side wall spacer on the sidewall of this first side wall clearance wall, this second side wall spacer has the width of 1 unit;
(6) form filler in the space between two these adjacent second side wall spacer, this filler has the width of 1 unit;
(7) remove this second side wall spacer;
(8) use this first side wall clearance wall and this filler as etching mask, this dielectric layer is carried out anisotropic etching, in this dielectric layer, to form most irrigation canals and ditches structures;
(9) in this majority irrigation canals and ditches, fill metal, to form most strip metal lines.
2, manufacture method as claimed in claim 1 is characterized in that: this dielectric layer is made of silica material.
3, manufacture method as claimed in claim 1 is characterized in that: this first side wall clearance wall and this filler are to use polycrystalline silicon material to constitute.
4, manufacture method as claimed in claim 1 is characterized in that: this second side wall spacer is to use doped silicon oxide material to constitute.
5, manufacture method as claimed in claim 1 is characterized in that: this each this irrigation canals and ditches structure has the width of 1 unit.
6, manufacture method as claimed in claim 1 is characterized in that: before making described insulation block, comprise forming silicon nitride layer in the step of this dielectric layer upper surface that this silicon nitride layer uses as etching stopping layer, is positioned at this dielectric layer of below with protection.
7, manufacture method as claimed in claim 1 is characterized in that: this insulation block is to use doped silicon oxide material to constitute.
8, manufacture method as claimed in claim 1 is characterized in that: this metal connecting line has the width of 1 unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011160705A CN1146034C (en) | 2001-05-14 | 2001-05-14 | Method for making buried microfine metal conductive wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011160705A CN1146034C (en) | 2001-05-14 | 2001-05-14 | Method for making buried microfine metal conductive wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1385889A CN1385889A (en) | 2002-12-18 |
| CN1146034C true CN1146034C (en) | 2004-04-14 |
Family
ID=4662369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011160705A Expired - Lifetime CN1146034C (en) | 2001-05-14 | 2001-05-14 | Method for making buried microfine metal conductive wire |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1146034C (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7291560B2 (en) * | 2005-08-01 | 2007-11-06 | Infineon Technologies Ag | Method of production pitch fractionizations in semiconductor technology |
| KR100744683B1 (en) | 2006-02-27 | 2007-08-01 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| JP4551913B2 (en) * | 2007-06-01 | 2010-09-29 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US9153440B2 (en) * | 2012-03-23 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device |
| CN103928394B (en) * | 2013-01-10 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of metal interconnect structure |
| CN103928392B (en) * | 2013-01-10 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of local interconnection structure |
| US8836128B1 (en) * | 2013-03-15 | 2014-09-16 | Microchip Technology Incorporated | Forming fence conductors in an integrated circuit |
| CN104617032B (en) * | 2013-11-05 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | The method for forming interlayer interconnecting construction |
| US9379010B2 (en) * | 2014-01-24 | 2016-06-28 | Intel Corporation | Methods for forming interconnect layers having tight pitch interconnect structures |
| US9472414B2 (en) * | 2015-02-13 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned multiple spacer patterning process |
| US9842843B2 (en) | 2015-12-03 | 2017-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing static random access memory device |
| WO2018165815A1 (en) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | Chip fanning out method |
| US11837499B2 (en) | 2021-10-01 | 2023-12-05 | Nanya Technology Corporation | Method for preparing fine metal lines with high aspect ratio |
-
2001
- 2001-05-14 CN CNB011160705A patent/CN1146034C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1385889A (en) | 2002-12-18 |
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