CN1242481C - High coupling rate rapid flash memory and its manufacturing method - Google Patents
High coupling rate rapid flash memory and its manufacturing method Download PDFInfo
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- CN1242481C CN1242481C CN01145050.9A CN01145050A CN1242481C CN 1242481 C CN1242481 C CN 1242481C CN 01145050 A CN01145050 A CN 01145050A CN 1242481 C CN1242481 C CN 1242481C
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Abstract
The present invention provides a rapid flash memory with a high coupling rate and a manufacturing method for the rapid flash memory with a high coupling rate. In the present invention, a trench and a floating brake pole are also manufactured, and self alignment forms a silicon island to serve as the floating brake pole. The method of the present invention at least comprises the following procedures: forming a tunneling dielectric layer on a substrate; depositing a first conductive layer on the tunneling dielectric layer; etching the first conductive layer, the tunneling dielectric layer and the substrate so that the trench is simultaneously formed in the substrate and self alignment forms the floating brake pole; then, back filling materials in the trench; flatting the filling materials so as to form a trench insulation structure; forming an interlayer dielectric layer on the trench insulation structure of the floating brake pole; finally, depositing a second conductive layer on the interlayer dielectric layer.
Description
Technical field
The present invention relates to the manufacture method of a kind of flash memory, particularly a kind of high coupling rate rapid flash memory.
Background technology
The trend of manufacture of semiconductor constantly develops towards promoting wafer structure dress density, so circuit elements design is just constantly towards the idea evolution of saving the space.The size of being devoted to dwindle each element makes integration promote.For element is dwindled, size of component has been contracted to time micron or littler scope.Along with semi-conductive evolution, the use of multiple internal connecting lines also is one of trend of ic manufacturing technology development.The manufacturing of non-volatility memorizer is also along with trend is dwindled component size, non-volatility memorizer comprises the element of different types, PROM (programmable read only memory) for example, EPROM (EPROM), quickflashing EEPROM, the trend of different types element is all toward high persistence and high-speed demand side development.Various non-volatility memorizers are suggested successively, and for example Mitchellx proposes a kind of EPROMs and has autoregistration plane storage array (self-aligned planar array cell).Consult A.T.Mitchellx, " A NewSelf-Aligned PIanar Cell for Ultra High Density EPROMs ", IEDM, Tech.pp.548-553,1987 ".
Flash memory is a kind of non-volatile memory element, comprise one can store charge suspended grid and electric charge access and exit control unit.Portable computer and telecommunications industry have become the main drive of semiconductor integrated circuit designing technique.For example, flash memory can be applied in the ROM-BIOS (BIOS) in the computer, and the range of application of high density non-volatility memorizer then comprises the interface card of mass storage device, digital solid-state camera and PC in the portable terminal etc.Access time is the key that low-voltage reads running, and in order to cater to the application demand in Maneuver Computing System, the function of low electric power and fast access becomes the deisgn approach of non-volatility memorizer.Present low-voltage flash memory carries out the charge or discharge action to suspended grid usually under 3 to 5 volts operating voltage, in addition, be applied to the Fowler-Nordheim tunneling effect that electronic type programmable read only memory (ROM) all uses some degree, the energy barrier at wherein cold electron tunneling silicon and silicon dioxide interface and enter the oxidation conduction band, when a voltage imposes on grid, the silicon dioxide layer that the electric charge tunnelling is thin.Programming has many kinds with the method for erasing, and utilizes the current potential of control base material, drain, source electrode and grid usually, and the tunnelling electronics is moved into through thin oxide layer (tunnel oxide) by silicon, in the pattern of erasing, then electronic emission is come out.In order to reach good element function, above-mentioned tunnel oxide must possess good quality is arranged.Secondly, the information of flash memory stores must rely on electric charge is resided among the suspended grid for a long time, so must have good performance in order to the dielectric layer of isolation suspended grid.
Bergemont proposes the another kind of memory cell that is applied to portable computer and telecommunication apparatus in its paper, see also " Low VoltageNVG
TM: A New High Performance 3V/5V FlashTechnology for Portable Computing and TelecommunicationsApplication " (in IEEE Trans.Electron Devices Vol.43, p.1510,1996).This memory cell structure is incorporated in the anti-or lock formula virtual ground of low-voltage, and (NOR VirtualGround, NVG) flash memory has fast access time.In the flash array system, polysilicon layer extends on the field oxide between memory cell so that the grid coupling efficiency (gatecoupling ratio) of suitable foot to be provided.The NVG array adopts the mode of selecting element to reach the access time fast.
Summary of the invention
Purpose of the present invention is for proposing a kind of manufacture method of high coupling rate rapid flash memory.
The object of the present invention is achieved like this, a kind of method that forms non-volatility memorizer, and this method comprises the following step at least: form tunnel dielectric layer on a substrate; Deposit first conductive layer on this tunnel dielectric layer; This first conductive layer of etching, this tunnel dielectric layer and this substrate, make form simultaneously irrigation canals and ditches in this substrate and autoregistration form suspended grid; Backfill one is filled material among these irrigation canals and ditches; Planarization should be filled material, to form the trench insulation structure; This trench insulation structure of etching is to form groove between between suspended grid; Form the surface of second conductive layer in this suspended grid and these irrigation canals and ditches; This second conductive layer of etching is to form clearance wall; Form interlayer dielectric layer on this suspended grid, trench insulation structure, this clearance wall; And deposition the 3rd conductive layer is on this interlayer dielectric layer.
Purpose of the present invention also can be realized by following measure: wherein more comprised before forming this second conductive layer and form the 4th conductive layer.Wherein above-mentioned tunnel dielectric layer comprises oxide.Wherein above-mentioned interlayer dielectric layer comprises ONO.Wherein above-mentioned interlayer dielectric layer comprises NO.Wherein above-mentioned first conductive layer, second conductive layer, the 3rd conductive layer are selected from and comprise polysilicon or metal.
Purpose of the present invention can also be achieved in that a kind of method that forms non-volatility memorizer, and this method comprises the following step at least: form tunnel dielectric layer on a substrate; Deposit first conductive layer on this tunnel dielectric layer; This first conductive layer of etching, this tunnel dielectric layer and this substrate, make form simultaneously irrigation canals and ditches in this substrate and autoregistration form suspended grid; Backfill one is filled material among these irrigation canals and ditches; Planarization should be filled material, to form the trench insulation structure; This trench insulation structure of etching is to form groove between between suspended grid; Form interlayer dielectric layer on this suspended grid, trench insulation structure; And deposition second conductive layer is on this interlayer dielectric layer.
Purpose of the present invention can also be achieved in that and wherein more comprise formation the 3rd conductive layer and etching the 3rd conductive layer to form clearance wall before forming this interlayer dielectric layer.Wherein above-mentioned tunnel dielectric layer comprises oxide.Wherein above-mentioned interlayer dielectric layer comprises ONO.Wherein above-mentioned interlayer dielectric layer comprises NO.Wherein above-mentioned first conductive layer, second conductive layer are selected from and comprise polysilicon or metal.
The non-volatility memorizer that the present invention discloses comprises: substrate, and the bag irrigation canals and ditches are formed at wherein; First dielectric layer is formed on this substrate; First conductive layer is stacked on this first dielectric layer; The insulation material is formed in these irrigation canals and ditches, protrudes this substrate surface, and wherein this first conductive layer also protrudes this insulation material; Second conductive layer is formed at the surface of this first conductive layer; Second dielectric layer is formed on this second conductive layer; The 3rd conductive layer is formed on this second dielectric layer as the control grid.
The non-volatility memorizer that the present invention discloses wherein more comprises clearance wall and is formed on this second conductive layer.Wherein above-mentioned interlayer dielectric layer comprises ONO or NO.Wherein above-mentioned first conductive layer, second conductive layer are selected from and comprise polysilicon or metal.
The non-volatility memorizer that the present invention discloses comprises: substrate, and the bag irrigation canals and ditches are formed at wherein; First dielectric layer is formed on this substrate; First conductive layer is stacked on this first dielectric layer; The insulation material is formed in these irrigation canals and ditches, protrudes this substrate surface, and wherein this first conductive layer also protrudes this insulation material; Second dielectric layer is formed on this first conductive layer: and second conductive layer, be formed on this second dielectric layer as the control grid.
The non-volatility memorizer that the present invention discloses wherein more comprises clearance wall and is formed on first conductive layer.Wherein above-mentioned interlayer dielectric layer comprises ONO or NO.Wherein above-mentioned first conductive layer, second conductive layer are selected from and comprise polysilicon or metal.
Description of drawings
Fig. 1 is the semiconductor crystal wafer profile that forms irrigation canals and ditches according to the present invention on substrate;
Fig. 2 is the semiconductor crystal wafer profile of shallow trench insulation formed according to the present invention;
Fig. 3 is the semiconductor crystal wafer profile of grid formed according to the present invention;
Fig. 4 selects the semiconductor crystal wafer profile of step according to of the present invention another;
Fig. 5 is the schematic diagram that the present invention forms conductive layer.
The figure number explanation:
Irrigation canals and ditches 8 shallow trench insulation systems 12 interlayer dielectric layers 18
Second conductive layer 16
Embodiment
The invention provides a kind of manufacture method of Nonvolatile flash memory, in the present invention, form the making of irrigation canals and ditches and suspended grid simultaneously.In manufacturing process, need not change reative cell and promptly can make irrigation canals and ditches and suspended grid.Embodiments of the invention cooperate diagram to be described in detail as follows.
The semiconductor substrate at first is provided, and as shown in fig. 1, in most preferred embodiment, substrate 2 is that crystal plane is to＜100〉or＜111 monocrystalline silicon.Other semiconductor material such as arsenic potassium or germanium can also use.Then form on substrate 2 by the tunnel oxide 4 that silica constituted, this tunnel oxide 4 generally can grow up to thermal oxidation method in the oxygen environment under about 700 to 1100 degree of Celsius temperature.In addition, (Chemical VaporDeposition CVD) forms this tunnel oxide 4 also can to adopt additive method such as chemical vapour deposition technique.In the present embodiment, the thickness of tunnel oxide 4 is about the 15-250 dust.Then, doped polycrystalline silicon layer 6 is deposited on the tunnel oxide 4.The making of this polysilicon layer 6 can be adopted PH
3Be ion source, the phosphonium ion implantation formed with ion implantation or synchronous doping method.
One standard lithographic etch process is in order to above-mentioned polysilicon layer 6 of etching and tunnel oxide 4, and deep substrate 2 is to form a plurality of irrigation canals and ditches 8 in wherein.In this step, form insulating regions and suspended grid simultaneously, that is a self-aligning grid processing procedure is provided.For example, can adopt universe etching, with CF
4+ O
2The electricity slurry is as etchant, continue and one fill oxide backfill that material 10 for example forms by CVD among irrigation canals and ditches, in the preferred embodiment, process temperatures is about 400 to 600 degree Celsius, carry out a chemical mechanical milling method afterwards and remove the surface of the upper end of oxide, as shown in Figure 2 to suspended grid 6.The source electrode drain of element can use previous technology to be made, and is not shown at this.That is utilize grid structure to plant the cover curtain as cloth.
Consult Fig. 3, the etching that utilizes oxide and silicon to have high selectivity forms groove 12 with oxide 10 etchings, and the degree of depth of groove can be by etching control.Second conductive layer 14 continues and is formed at above-mentioned suspended grid 6 surfaces and irrigation canals and ditches 12 surfaces, conductive layer 6 and 14 both form suspended grid.The width of first conductive layer 6 is x, and the thickness of second conductive layer 14 is y, and then suspended grid upper surface width is x+2y.Therefore can promote coupling efficiency.Optionally etching second conductive layer 14 that continues forms clearance wall 14a, forms the clearance wall on the irrigation canals and ditches 12, shown in Fig. 3 B.
Another embodiment as shown in Figure 3A, clearance wall 16 is made in the groove with known techniques and is attached on second conductive layer 14.The thickness of supposing clearance wall 16 again is z, and then suspended grid upper surface width is x+2y+2z.
Interlayer dielectric layer 18 is formed at the upper end of suspended grid, generally can adopt ONO, NO as above-mentioned interlayer dielectric layer, shown in Fig. 4 to 4B.At last, a conductive layer 20 is formed on the above-mentioned interlayer dielectric layer 18, can adopt polysilicon, metal or alloy.
Consult Fig. 5, dielectric layer can directly be formed at etched first conductive layer 6 surfaces, continues to form rete 20.
In the present invention, tunnel oxide, suspended grid and irrigation canals and ditches are defined in same step simultaneously, in other words, suspended grid autoregistration simultaneously is formed at the both sides of irrigation canals and ditches, moreover, another advantage of the present invention need not changed gas for making irrigation canals and ditches and defining suspended grid, just belongs to material of the same race based on rete 6 and substrate 2, so need not change reative cell (chamber).
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the described claim scope.
Claims (12)
1. the manufacture method of a high coupling rate rapid flash memory, this method comprises the following step at least:
Form tunnel dielectric layer on a substrate;
Deposit first conductive layer on this tunnel dielectric layer;
This first conductive layer of etching, this tunnel dielectric layer and this substrate, make form simultaneously irrigation canals and ditches in this substrate and autoregistration form suspended grid;
Backfill one is filled material among these irrigation canals and ditches;
Planarization should be filled material, to form the trench insulation structure;
This trench insulation structure of etching is to form groove between between suspended grid;
Form the surface of second conductive layer in this suspended grid and these irrigation canals and ditches;
This second conductive layer of etching is to form clearance wall;
Form interlayer dielectric layer on this suspended grid, trench insulation structure, this clearance wall; And
Deposit the 3rd conductive layer on this interlayer dielectric layer.
2. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1 wherein more comprised formation the 4th conductive layer before forming this second conductive layer.
3. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned tunnel dielectric layer comprises oxide.
4. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned interlayer dielectric layer comprises ONO.
5. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned interlayer dielectric layer comprises NO.
6. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned first conductive layer, second conductive layer, the 3rd conductive layer are selected from and comprise polysilicon or metal.
7. the manufacture method of a high coupling rate rapid flash memory, this method comprises the following step at least:
Form tunnel dielectric layer on a substrate;
Deposit first conductive layer on this tunnel dielectric layer;
This first conductive layer of etching, this tunnel dielectric layer and this substrate, make form simultaneously irrigation canals and ditches in this substrate and autoregistration form suspended grid;
Backfill one is filled material among these irrigation canals and ditches;
Planarization should be filled material, to form the trench insulation structure;
This trench insulation structure of etching is to form groove between between suspended grid;
Form interlayer dielectric layer on this suspended grid, trench insulation structure; And
Deposit second conductive layer on this interlayer dielectric layer.
8. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 7 wherein more comprised formation the 3rd conductive layer and etching the 3rd conductive layer to form clearance wall before forming this interlayer dielectric layer.
9. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned tunnel dielectric layer comprises oxide.
10. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned interlayer dielectric layer comprises ONO.
11. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned interlayer dielectric layer comprises NO.
12. the manufacture method of a kind of high coupling rate rapid flash memory as claimed in claim 1, wherein above-mentioned first conductive layer, second conductive layer are selected from and comprise polysilicon or metal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01145050.9A CN1242481C (en) | 2001-12-31 | 2001-12-31 | High coupling rate rapid flash memory and its manufacturing method |
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| CN01145050.9A CN1242481C (en) | 2001-12-31 | 2001-12-31 | High coupling rate rapid flash memory and its manufacturing method |
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| CN1430283A CN1430283A (en) | 2003-07-16 |
| CN1242481C true CN1242481C (en) | 2006-02-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1324693C (en) * | 2003-07-24 | 2007-07-04 | 旺宏电子股份有限公司 | Manufacturing method of flash memory |
| KR100672763B1 (en) * | 2003-12-24 | 2007-01-22 | 주식회사 하이닉스반도체 | Method of forming gate for semiconductor device |
| CN106972022B (en) * | 2016-01-11 | 2019-10-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
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