CN106972022B - A kind of semiconductor devices and preparation method thereof, electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic device Download PDFInfo
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- CN106972022B CN106972022B CN201610014814.XA CN201610014814A CN106972022B CN 106972022 B CN106972022 B CN 106972022B CN 201610014814 A CN201610014814 A CN 201610014814A CN 106972022 B CN106972022 B CN 106972022B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 28
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
- 230000008569 process Effects 0.000 claims description 9
- 239000007787 solid Substances 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 230000009466 transformation Effects 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- -1 SiGe Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 238000006396 nitration reaction Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000011435 rock Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003856 thermoforming Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005915 ammonolysis reaction Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004821 distillation Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical group O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000002516 radical scavenger Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides production method, semiconductor devices and the electronic device of a kind of semiconductor devices, which includes: offer semiconductor substrate, is formed with tunnel dielectric layer, floating gate and gate dielectric on the semiconductor substrate；Polysilicon capping layer is formed on the gate dielectric；Groove is formed in the polysilicon capping layer and the gate dielectric；The surface for the floating gate that surface and the channel bottom to the polysilicon capping layer are exposed is handled, so that the oxide on the surface for the floating gate that the polysilicon capping layer and the channel bottom expose is changed into fluoride；Remove the fluoride on the surface of the floating gate of the polysilicon capping layer and the channel bottom；Form the control gate for covering the polysilicon capping layer and the groove.This method can prevent the high-pressure area of fast storage device from causing erase status to fail due to boundary layer to avoid boundary layer is formed between polysilicon capping layer and control.The semiconductor devices and electronic device stability with higher.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technique
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory is acted with can repeatedly carry out deposit, reading and erasing of information etc., and be stored in
The characteristic that information will not disappear after a loss of power, therefore, flash memory has become PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storage is due to large storage capacity and relatively high property
Can, it is widely used in the more demanding field of read/write.Recently, the capacity of NAND flash memory chip has reached 2GB, and
Size increases sharply.It has been developed based on the solid state hard disk of NAND quick-flash memory chip, and has been used as in portable computer
Store equipment.Therefore, in recent years, NAND fast storage is widely used as the storage equipment in embedded system, also serves as individual
Storage equipment in computer system.
In general, NAND quick-flash memory includes memory cell areas (cell), high-pressure area, area of low pressure, and for
High-pressure area is formed with polysilicon capping layer between gate dielectric and control gate, when using as subsequent etching gate dielectric
Exposure mask, but due to boundary layer easy to form between polysilicon capping layer and control gate, as shown in figure 1 shown in 100, such as titanium dioxide
Silicon, this is easy to cause erase status to fail for the high-pressure area of NAND fast storage.
Therefore, it is necessary to a kind of new production method be proposed, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention proposes a kind of manufacturing method of semiconductor devices, can be to avoid in polycrystalline
Boundary layer is formed between silicon cap rock and control, prevents the high-pressure area of fast storage device from causing to wipe shape due to boundary layer
State failure.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of production method of semiconductor devices, the party
Method includes the following steps: S1: providing semiconductor substrate, is formed with tunnel dielectric layer, floating gate and grid on the semiconductor substrate
Pole dielectric layer；S2: polysilicon capping layer is formed on the gate dielectric；S3: it is situated between in the polysilicon capping layer and the grid
Groove is formed in electric layer；S4: at the surface for the floating gate that surface and the channel bottom to the polysilicon capping layer are exposed
Reason, so that the oxide on the surface for the floating gate that the polysilicon capping layer and the channel bottom expose is changed into fluoride；S5: it goes
Except the fluoride on the surface of the polysilicon capping layer and the floating gate of the channel bottom；S6: it is formed and covers the polysilicon capping layer
And the control gate of the groove.
Further, in the step S4, the polysilicon capping layer and the channel bottom are exposed using ammonium fluoride
Floating gate surface handled so that the oxide on the surface of the polysilicon capping layer and the channel bottom floating gate is changed into fluorine
Compound.
Further in the step S5, the fluoride is removed by executing heat treatment, so that the fluoride
It is gaseous state by Solid State Transformation and is pumped.
Further, the step S4 and S5 is completed by executing SiCoNi cleaning process.
It further, further include prerinse step before the step S4, to remove the surface of the polysilicon capping layer
The residue on the surface of the floating gate exposed with the channel bottom.
The manufacturing method of semiconductor devices of the invention can to avoid forming boundary layer between polysilicon capping layer and control,
Prevent the high-pressure area of fast storage device causes erase status to fail due to boundary layer.
Another aspect of the present invention provides a kind of semiconductor devices made by the above method, which includes:
Semiconductor substrate is sequentially formed with tunnel dielectric layer, floating gate, gate dielectric, polysilicon capping layer on the semiconductor substrate
And control gate, and the groove in the gate dielectric, the control gate covering polysilicon capping layer and the ditch
Slot.
Boundary layer is not present in semiconductor devices proposed by the present invention between polysilicon capping layer and control, thus prevents quickly
The problem of high-pressure area of storage component part causes erase status to fail due to boundary layer.
Further aspect of the present invention provides a kind of electronic device comprising a kind of semiconductor devices and with the semiconductor device
The electronic building brick that part is connected.
Electronic device proposed by the present invention due to above-mentioned semiconductor device, thus has the advantages that similar.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows between polysilicon capping layer and control gate that there are the existing devices of boundary layer；
The production method that Fig. 2A~Fig. 2 G shows semiconductor devices according to an embodiment of the present invention is successively implemented respectively
The diagrammatic cross-section of the obtained semiconductor devices of step；
Fig. 3 shows the step flow chart of the production method of semiconductor devices according to an embodiment of the present invention；
Fig. 4 shows the structural schematic diagram of semiconductor devices according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with appended drawing reference.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relation term intention further include using with
The different orientation of device in operation.For example, then, being described as " below other elements " if the device in attached drawing is overturn
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to solve foregoing problems, that is, prevent in the high-pressure area of NAND device, polysilicon capping layer and control gate it
Between form boundary layer, and erase status is caused to fail, the present invention provides a kind of production method of semiconductor devices, and this method includes
Following step: S1: semiconductor substrate is provided, is formed with tunnel dielectric layer, floating gate and gate dielectric on the semiconductor substrate
Layer；S2: polysilicon capping layer is formed on the gate dielectric；S3: in the polysilicon capping layer and the gate dielectric
Form groove；S4: the surface for the floating gate that surface and the channel bottom to the polysilicon capping layer are exposed is handled, so that
The oxide on the surface for the floating gate that the polysilicon capping layer and the channel bottom expose is changed into fluoride；S5: described in removal
The fluoride on the surface of the floating gate of polysilicon capping layer and the channel bottom；S6: it is formed and covers the polysilicon capping layer and institute
The production method for stating the control gate semiconductor devices of the invention of groove, after forming polysilicon capping layer, to the polysilicon
The surface of cap rock and the surface of the channel bottom floating gate are handled, and the floating of the polysilicon capping layer and the channel bottom is made
The oxide on the surface of grid is changed into fluoride, and then removes the fluoride, in this way by the surface of polysilicon capping layer and institute
The oxide for stating the surface of channel bottom floating gate is removed, thus is being subsequently formed the polysilicon capping layer and the groove
After control gate, there is no the boundary layers of such as oxide layer between polysilicon capping layer and control gate, to avoid due to interface
Such as erase status caused by layer there are problems that fails.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiments.
Embodiment one
It is done below with reference to production method of Fig. 2A~Fig. 2 G and Fig. 3 to the semiconductor devices of an embodiment of the present invention
Detailed description.
Firstly, executing step 301: providing semiconductor substrate 201,201 be formed with tunnelling Jie on the semiconductor substrate
Electric layer 202, floating gate 203 and gate dielectric 204, it is as shown in Figure 2 A to be formed by structure.
Wherein, semiconductor substrate 201 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure is as an example, in the present embodiment, the constituent material of semiconductor substrate 201 selects monocrystalline, with a thickness of 1000~2000nm.
Tunnel dielectric layer 202 is used as insulating layer, and such as grid oxic horizon, tunnel dielectric layer 202 can use various
Suitable material, illustratively, in the present embodiment, the silica of tunnel dielectric layer 202, with a thickness ofTunnel
Wearing dielectric layer 202 can be formed by techniques such as PVD, CVD, ALD and thermoforming process commonly used in the art, exemplary, In
In the present embodiment, silica is formed as the tunnel dielectric layer 202 by thermal oxidation method.
The material of floating gate 203 uses such as polysilicon, is formed by PVD, CVD, ALD commonly used in the art.It is exemplary
Ground forms floating gate 203 by CVD method in the present embodiment, with a thickness of
Gate dielectric 204 can select various suitable dielectric materials, it is exemplary in the present embodiment, it is each in order to improve
Layer between interface performance, and have high dielectric constant, gate dielectric 204 use ONO structure, i.e., oxide layer/nitration case/
Oxide layer structure, wherein first layer oxide layer is the oxide layer being located on floating gate 203, can be formed by thermal oxidation method, oxygen
Nitration case on first layer oxide layer, such as silicon nitride can be formed by techniques such as PVD, CVD, ALD, and second
Secondary oxide layer can be formed by such as PVD, CVD, ALD and thermal oxidation technology, these techniques are technique commonly used in the art, In
Its concrete operations will not be described in detail in this.
Then, step 302 is executed, polysilicon capping layer 205 is formed on the gate dielectric 204, is formed by structure
As shown in Figure 2 B.
As shown in Figure 2 B, on gate dielectric 204, i.e., polysilicon capping layer 205, the polysilicon are formed on ONO layer 204
Cap rock 205 can be used as the barrier layer of subsequent ONO etching.Illustratively.In the present embodiment, it is formed by CVD technique described
Polysilicon capping layer 205, with a thickness of
Then, step 303 is executed, forms groove 206 in the polysilicon capping layer 205 and the gate dielectric 204,
The exposure of groove 206 floating gate 203, it is as shown in Figure 2 C to be formed by structure.
It is exemplary, in the present embodiment, by suitable photoetching and etching technics in the polysilicon capping layer 205 and institute
State formation groove 206 in gate dielectric 204, the exposure of groove 206 floating gate 203, so as in the high-pressure area of device
The function of various MOS transistors may be implemented.The etch process can be wet-etching technology or dry method etch technology, dry method
Etch process includes but is not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting.Institute
The source gas for stating dry etching may include CF4, CHF3 or other fluorocarbon gas.
It is exemplary, in this embodiment, the polysilicon capping layer 205 and the gate dielectric are etched using dry etch process
Layer 204, and as an example, in the present embodiment, described to be etched to dry etching, the technological parameter of the dry etching includes:
Etching gas includes that gases, the flows such as CF4, CHF3 are respectively 50sccm~500sccm, 10sccm~100sccm, and pressure is
2mTorr~50mTorr, wherein sccm represents cc/min, and mTorr represents milli millimetres of mercury.
Further, after due to forming polysilicon capping layer 205 in step 302, and in step 103, due to environment
There are oxygen, and the floating gate surface of 206 bottom of polysilicon capping layer or even groove is made to form oxide layer 207, such as silica,
, can be as shown in Figure 2 D in this way if directly controlling grid after step 103, between polysilicon capping layer 205 and control gate 208
There are dielectric layers 207, and the high-pressure area that will lead to device in this way goes wrong, such as erase status failure.Therefore, in this implementation
In example, in order to avoid there is such case, after executing the step 303, control gate is not formed directly, but first to oxidation
Layer 207 is handled, this will be described below.
It is understood that groove 206 need not be formed in all areas of device, such as NAND device, ditch
Slot 206 is only formed in the high-pressure area of device and area of low pressure, and is not formed in the memory cell region of device.When
So, in other devices, it is also possible to be made a change according to specific situation.
Then, step 304 is executed, the floating gate that the surface and 206 bottom of the groove to the polysilicon capping layer 205 are exposed
203 surface is handled, so that the oxygen on the surface for the floating gate 203 that the polysilicon capping layer 205 and the channel bottom expose
Compound is changed into fluoride, and it is as shown in Figure 2 E to be formed by structure.
It is exemplary, in the present embodiment, the oxide layer 207 is handled using ammonium fluoride (NH4F), to be 207 turns of oxide layer
Become fluoride layer 209.Specific reflection process are as follows: NH4F+SiO2 → (NH4) 2SiF6 (solid)+H2O.It is exemplary, in this reality
It applies in example, reflection temperature is 10 DEG C to 50 DEG C.
Then, step 305 is executed, the floating gate 203 of the polysilicon capping layer 205 and the exposing of 206 bottom of the groove is removed
Surface fluoride, it is as shown in Figure 2 F to be formed by structure.
Due to fluoride, for example (NH4) 2SiF6 is volatile solids, it can be made by Solid State Transformation gas by heating
State, thus by air extractor abstraction reaction chamber.Illustratively, in the present embodiment, it is made a return journey fluorine removal compound by annealing process
Layer 209, annealing temperature are 100 DEG C~300 DEG C, and annealing time is 1 minute to 30 minutes.
It is understood that step 304 and step 305 can be completed respectively respectively, SiCoNi scavenger also can be used
Skill is completed in the same chamber.SiCoNi technique mainly includes two steps: the long-range plasma etch of NF3/NH3 and in-situ annealing,
This two step is all completed in same chamber body.In etching process, wafer is placed on the bottom that temperature is strictly controlled at 35 DEG C
On seat, NF3 and NH3 are transformed into ammonium fluoride (NH4F) and bifluoride ammonia by the plasma-based of low-power.Fluoride is condensed in crystal column surface,
And preferentially reacted with oxide, it is formed hexafluoro silicon ammonia ((NH4) 2SiF6).This silicate can be in 70 DEG C or more of environment
Distillation.During in-situ annealing, wafer is moved to close to the position of heating element, and the hydrogen of flowing takes heat to wafer
On piece, wafer are heated to 100 DEG C or more in a short period of time, make hexafluoro silicon ammonolysis craft gaseous SiF4, NH3 and
HF, and be pumped away.
It will also be appreciated that further include pre-cleaning processes before step 104, to go to removing oxide layer and floating gate surface
Residue, to be better carried out subsequent technique.
Finally, executing step 306, the control gate 208 for covering the polysilicon capping layer 205 and the groove 203 is formed,
It is as shown in Figure 2 G to be formed by structure.
It is exemplary, in this embodiment, by the techniques such as PVD, CVD, ALD formed the polysilicon capping layer 205 and
The polysilicon layer of the groove 203, using as control gate.
It is understood that in the present embodiment, when after completing this step, polysilicon capping layer 205 and the step are formed
Polysilicon layer can merge, collectively as the electrode material layer of control gate in subsequent, in attached drawing be merely for convenience of that this is shown
Each step of invention, so the polysilicon formed in polysilicon capping layer and this step is using different representations.
So far, the processing step implemented according to the method for the embodiment of the present invention is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs later
The step of, it is included in the range of this implementation production method.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 4, semiconductor devices 400 includes: semiconductor substrate 401,
Tunnel dielectric layer 402, floating gate 403, gate dielectric 404, polysilicon capping layer are sequentially formed in the semiconductor substrate 401
405 and control gate 407, and the groove 406 in the gate dielectric 405, the control gate 407 cover the polycrystalline
Silicon cap rock 405 and the groove 406.
Wherein semiconductor substrate 401 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.It could be formed with device, such as NMOS in semiconductor substrate
And/or PMOS etc..Equally, can also be formed with conductive member in semiconductor substrate, conductive member can be transistor grid,
Source electrode or drain electrode are also possible to the metal interconnection structure, etc. being electrically connected with transistor.In addition, may be used also in the semiconductor substrate
To be formed with isolation structure, the isolation structure is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation junction
Structure is as example.In the present embodiment, the constituent material of semiconductor substrate 401 selects monocrystalline silicon.
Tunnel dielectric layer 402 is used as insulating layer, and such as grid oxic horizon, tunnel dielectric layer 202 can use various
Suitable material, illustratively, in the present embodiment, the silica of tunnel dielectric layer 202, with a thickness ofTunnel
Wearing dielectric layer 402 can be formed by techniques such as PVD, CVD, ALD and thermoforming process commonly used in the art, exemplary, In
In the present embodiment, silica is formed as the tunnel dielectric layer 202 by thermal oxidation method.
The material of floating gate 403 uses such as polysilicon, is formed by PVD, CVD, ALD commonly used in the art.It is exemplary
Ground forms floating gate 203 by CVD method in the present embodiment, with a thickness of
Gate dielectric 404 can select various suitable dielectric materials, it is exemplary in the present embodiment, it is each in order to improve
Layer between interface performance, and have high dielectric constant, gate dielectric 404 use ONO structure, i.e., oxide layer/nitration case/
Oxide layer structure, wherein first layer oxide layer is the oxide layer being located on floating gate 403, can be formed by thermal oxidation method, oxygen
Nitration case on first layer oxide layer, such as silicon nitride can be formed by techniques such as PVD, CVD, ALD, and second
Secondary oxide layer can be formed by such as PVD, CVD, ALD and thermal oxidation technology, these techniques are technique commonly used in the art, In
Its concrete operations will not be described in detail in this.
Polysilicon capping layer 405, groove 406 and control gate 407 are formed by method commonly used in the art, no longer superfluous herein
It states.
It is common in subsequent it is understood that in the present embodiment, polysilicon capping layer 405 and control gate 407 can merge
It as the electrode material layer of control gate, is merely for convenience of that each device layer is shown in attached drawing, so polysilicon capping layer 405 and control
Grid 407 use different representations.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic device, including above-mentioned semiconductor device and partly leads with described
The connected electronic building brick of body device.Wherein, which includes: semiconductor substrate, on the semiconductor substrate successively
It is formed with tunnel dielectric layer, floating gate, gate dielectric, polysilicon capping layer and control gate, and is located in the gate dielectric
Groove, the control gate covers the polysilicon capping layer and the groove.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
The electronic device of the embodiment of the present invention due to having used above-mentioned semiconductor devices, thus equally has above-mentioned excellent
Point.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (7)
1. a kind of production method of semiconductor devices, which is characterized in that include the following steps:
Step S1: semiconductor substrate is provided, is formed with tunnel dielectric layer, floating gate and gate dielectric on the semiconductor substrate
Layer；
Step S2: polysilicon capping layer is formed on the gate dielectric；
Step S3: groove is formed in the polysilicon capping layer and the gate dielectric；
Step S4: the surface for the floating gate that surface and the channel bottom to the polysilicon capping layer are exposed is handled, so that
The oxide on the surface for the floating gate that the polysilicon capping layer and the channel bottom expose is changed into fluoride；
Step S5: the fluoride on the surface of the floating gate of the polysilicon capping layer and the channel bottom is removed；
Step S6: the control gate for covering the polysilicon capping layer and the groove is formed.
2. the production method of semiconductor devices according to claim 1, which is characterized in that in the step S4, use
The floating gate surface that ammonium fluoride exposes the polysilicon capping layer and the channel bottom is handled, so that the polysilicon capping layer
It is changed into fluoride with the oxide on the surface of the channel bottom floating gate.
3. the production method of semiconductor devices according to claim 1, which is characterized in that in the step S5, pass through
Heat treatment is executed to remove the fluoride, so that the fluoride is gaseous state by Solid State Transformation and is pumped.
4. the production method of semiconductor devices according to claim 1, which is characterized in that the step S4 and S5 is by holding
Row SiCoNi cleaning process is completed.
5. the production method of semiconductor devices according to claim 1, which is characterized in that also wrapped before the step S4
Prerinse step is included, to remove the remnants on the surface on the surface of the polysilicon capping layer and the floating gate of channel bottom exposing
Object.
6. a kind of semiconductor devices of the production method production using the semiconductor devices as described in one of claim 1-5,
It is characterized in that, comprising:
Semiconductor substrate,
It is sequentially formed with tunnel dielectric layer, floating gate, gate dielectric, polysilicon capping layer and control on the semiconductor substrate
Grid,
And the groove in the gate dielectric, the control gate cover the polysilicon capping layer and the groove.
7. a kind of electronic device, which is characterized in that including semiconductor devices as claimed in claim 6 and with the semiconductor
The electronic building brick that device is connected.
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| Title |
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| 一种新型高速嵌入式动态随机存储器;臧松干，王鹏飞，林曦，刘昕彦，丁士进，张卫;《微电子学》;20120229;第42卷(第1期);全文 * |
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