CN113971982B - Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip - Google Patents
Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip Download PDFInfo
- Publication number
- CN113971982B CN113971982B CN202010716342.9A CN202010716342A CN113971982B CN 113971982 B CN113971982 B CN 113971982B CN 202010716342 A CN202010716342 A CN 202010716342A CN 113971982 B CN113971982 B CN 113971982B
- Authority
- CN
- China
- Prior art keywords
- chip
- flash
- jtag interface
- read
- binary sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010998 test method Methods 0.000 title claims abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 33
- 230000005540 biological transmission Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 11
- 230000003139 buffering effect Effects 0.000 claims description 3
- 238000010511 deprotection reaction Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 description 18
- 238000001514 detection method Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a test method for carrying out flash read-write of a memory chip by bypassing a system chip on a fixed chip, wherein a plurality of groups of specific binary sequence codes are sent to a data line TDI of a JTAG port through a parallel port of a computer, and the instruction length, the data length and the highest transmission speed of the JTAG port can be calculated by means of an oscilloscope through a code stream observed on the data line TDO of the JTAG port; then, converting an operation instruction corresponding to the specification model of the flash chip to be read-write tested into a corresponding binary sequence code according to the characteristic parameters of the JTAG interface, and finally loading the binary sequence code into a parallel port card of a computer; the parallel port card can automatically match the level of the JTAG interface and sequentially move the sequence codes into pins of the system-on-chip, meanwhile, an internal control logic circuit of the system-on-chip is automatically isolated, and finally, the binary sequence codes are accurately transmitted to a control bus of the flash chip, so that the full-automatic read-write test of the flash memory chip is realized.
Description
Technical Field
The invention relates to the field of read-write test, in particular to a read-write test method for bypassing a system-on-a-chip-customized chip to perform flash of a memory chip.
Background
With the development of semiconductor process technology, particularly the maturation of ultra-deep submicron process technology, it is possible to integrate different functional modules, memories, and peripheral circuits on one silicon chip). This complete system, in which the various functional modules are integrated on one chip, is a system-on-a-chip SOC. The system-on-chip has the characteristics of light weight, small volume, low power consumption, high running speed and the like, so that as the functions of the current civil aviation aircraft become more powerful, the required avionics system is more and more complex, but because the whole weight of the aircraft needs to be strictly controlled due to factors such as fuel economy and the like, the electronic part accessory circuit of the avionics system adopts a large number of system-on-chip SOC on a customized chip in design so as to reduce the volume and the number of circuit boards. In recent years, particularly the avionic components of thales and honeywell have the advantages of powerful functions, complex design, advanced manufacturing process, adoption of a plurality of personalized custom-made system-on-chip chips of factories, increased difficulty for a third-party MRO maintenance unit in China to perform three-level board card maintenance test on the components in a ground mode, difficulty in performing omnibearing resource test on the board card so as to rapidly locate faults, unsatisfactory maintenance period, cost and quality, and serious maintenance profits in most markets facing the high added values are monopolized by foreign original factories, and development and technical reserve of the domestic civil aviation maintenance industry are not facilitated.
When the board card of the electronic component of the civil aircraft is maintained, a system-on-chip is frequently used for controlling a certain resource on the board, such as a program storage chip FLASH, hardware detection is required to be carried out on the FLASH chip according to a maintenance flow, and programs and data stored in the FLASH chip are checked, and currently popular detection schemes are three, one detection scheme is that the FLASH chip is detached from a circuit board to be detected through an electric soldering iron and a hot air gun, then the hardware detection and the program data check are carried out by a common programmer according to the model of the FLASH chip, and finally the chip is welded back to the circuit board. The method belongs to a manual mode completely, has simple principle and low cost, but has the defects that on one hand, secondary artificial faults are easy to be introduced when a flash chip is welded to cause the difficulty of circuit board investigation to be increased, and on the other hand, programs and data in the flash cannot be replaced at any time according to a maintenance scheme in the fault diagnosis process so as to observe, track and isolate fault phenomena. The second detection scheme is that firstly, a virtual logic analyzer is utilized to capture, analyze and restore control logic when a system-on-chip reads and writes FLASH, and then, a large-scale automatic test equipment is utilized to program and simulate the captured control logic time sequence to perform read-write operation on the FLASH, so that detection and verification of hardware, programs and data are performed. However, the scheme has obvious defects, firstly, if the functions of the system-on-chip are strong and the control logic is complex, the capture difficulty and stability are greatly increased, and the accuracy of the time sequence of the capture control logic determines the success or failure of the whole detection scheme; secondly, the capturing scheme of the virtual logic analyzer must adjust the capturing mode according to the actual board card to be tested, and the control logic of the virtual logic analyzer needs to be captured again for different boards, so that a great amount of manpower and time are required to be input, and the virtual logic analyzer meeting the capturing condition is high in price and is not beneficial to large-scale popularization and utilization in a maintenance workshop. And thirdly, ISP programming is carried out on the FLASH chip through a JTAG interface of the system on chip. The disadvantage of this scheme is that the corresponding programmer is needed to implement ISP in system programming, but because the system chip on chip is a special custom chip of OEM manufacturer, there is no technical data such as model specification, data manual, etc., and therefore any programmer tool cannot be obtained, the scheme is basically not feasible in practical operation.
Therefore, it is necessary to provide a read-write test method for bypassing the system-on-a-chip-customized chip to perform flash of the memory chip, so as to solve the above technical problems.
Disclosure of Invention
The invention provides a read-write test method for bypassing a system chip on a fixed sheet to carry out flash of a storage chip, which solves the problems of unsatisfactory maintenance period, cost and quality caused by the difficulty in the test of the current board maintenance and the difficulty in carrying out the test of all-dimensional resources on the board so as to rapidly locate faults.
In order to solve the technical problems, the read-write test method for bypassing the system-on-a-chip of the customized chip to perform the flash of the memory chip provided by the invention comprises the following steps:
S1, firstly, a plurality of groups of specific binary sequence codes are sent to a data line TDI of a JTAG port through a parallel port of a computer, and by means of an oscilloscope, the instruction length, the data length and the highest transmission speed of the JTAG port can be calculated through a code stream observed on the data line TDO of the JTAG port;
S2, searching out an operation command of the target flash according to a data manual of a read-write test, including commands of erasing, deprotection, write buffering, programming, reading and the like, and completely converting the commands into binary sequence codes according to characteristic parameters of a JTAG interface and a certain format;
S3, converting data and addresses written into the flash, a write control time sequence and the like into binary sequence codes, and enabling the flash to recognize correct operation when the binary sequence codes are transmitted to a control bus of the flash chip through a JTAG port;
S4, the binary sequence codes obtained by converting the step S2 and the step S3 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
S5, the computer software reads back a feedback signal TDO data line of the JTAG port through the parallel port card;
S6, converting a target address and a control time sequence of the read flash chip into a binary sequence code;
S7, the binary sequence codes obtained by converting the step S6 and the step S2 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
S8, the computer software reads back a feedback signal TDO data line of the JTAG port through the parallel port card;
S9, comparing the data written in the flash with the read data according to a binary format by the computer software.
The S1 comprises the following steps:
S101, accessing a JTAG interface of the system-on-chip into a parallel port of a computer.
S102, binary sequence code 11111111 is sent to the TDI data line of the JTAG interface by using control software.
S103, the binary sequence code 10100001010 is sent to a TDI data line of the JTAG interface by using control software.
S104, observing a TDO data line of the JTAG interface by using a DSO of the digital oscilloscope, and calculating the instruction length of the JTAG interface.
S105, binary sequence code 00000000 is sent to the TDI data line of the JTAG interface by using control software.
S106, binary sequence codes 0000101000 and 0000010000 are circularly and alternately sent to a TDO data line of the JTAG interface for 100 times by using control software.
S107, observing a TDO data line of the JTAG interface by using a DSO of the digital oscilloscope, and calculating the data length of the JTAG interface.
S108, repeating the steps S102-S107, and simultaneously, referring the clock line TCK speed of the JTAG interface to 20M so as to calculate the highest transmission speed of the JTAG interface.
Preferably, in the step S5, it is determined whether the writing operation in the step S4 is successful, and if not, the writing operation is performed again from the step S3; if successful, the data is written into the target flash, and then step S6 is executed.
Preferably, in the step S8, it is determined whether the read operation in the step S7 is successful, and if not, the read operation is performed again from the step S6; if so, the data indicating the target address of the flash chip is saved in the local hard disk file of the computer, and then step S9 is executed.
Preferably, in the step S9, if the test result is the same, the flash read-write test is successful, and the operation is ended; if not, the flash read-write test fails, and the flash read-write test needs to be executed again from the step S3.
Compared with the related art, the read-write test method for bypassing the system-on-a-chip-customized chip to perform the flash of the memory chip has the following beneficial effects:
The invention provides a read-write test method for bypassing a system chip on a fixed chip to perform flash of a memory chip,
1. The invention has wide application range, does not need to know and master the control logic of the system-on-chip with complex working principle, has no relation with the model, specification and manufacturer of the system-on-chip, can be suitable for the maintenance test of circuit boards of a plurality of manufacturers, and solves the problem of non-ideal maintenance period, cost and quality;
2. The invention has low cost and high reliability, is beneficial to popularization in maintenance production lines, can be realized through four control lines (clock line TCK, data line TDI, data line TDO and mode line TMS) of a parallel port of a common computer, a common digital oscilloscope and a JTAG interface, and has higher reliability due to the adoption of more mature devices and standard protocols;
3. The invention has strong repeatability, the whole test method can repeatedly carry out read-write test on the flash in the actual maintenance test only by calculating the characteristics of the JTAG interface, thereby meeting the field maintenance requirement of a production workshop;
4. The invention has high expansibility, and can realize on-line read-write operation on a series of memory chips, such as flash, ram, eeprom chips, nvram chips and the like, and simultaneously is beneficial to expanding to simultaneously and parallelly operate a plurality of chips, thereby improving the test efficiency and shortening the maintenance period of a circuit board.
Drawings
FIG. 1 is a flowchart showing calculation of JTAG interface characteristic parameters of a read-write test method for bypassing a system-on-a-chip-customized chip for memory chip flash;
FIG. 2 is a general flow chart of the read-write test method of the memory chip flash by bypassing the system-on-a-chip-fixed chip shown in FIG. 1;
Fig. 3 is a schematic diagram of hardware wiring of the read-write test method for bypassing the system-on-a-chip-customized chip to perform flash of the memory chip shown in fig. 1.
Detailed Description
The invention will be further described with reference to the drawings and embodiments.
Referring to fig. 1, fig. 2 and fig. 3 in combination, fig. 1 is a flowchart showing calculation of characteristic parameters of a JTAG interface of a method for performing a read/write test of a memory chip flash by bypassing a system-on-a-chip-on-a-fixed chip, fig. 2 is a general flowchart of the method for performing a read/write test of a memory chip flash by bypassing a system-on-a-fixed chip of fig. 1, and fig. 3 is a schematic diagram of hardware wiring of the method for performing a read/write test of a memory chip flash by bypassing a system-on-a-fixed chip of fig. 1. A read-write test method for bypassing a system chip on a customized chip to carry out flash of a storage chip comprises the following steps:
S1, firstly, a plurality of groups of specific binary sequence codes are sent to a data line TDI of a JTAG port through a parallel port of a computer, and by means of an oscilloscope, the instruction length, the data length and the highest transmission speed of the JTAG port can be calculated through a code stream observed on the data line TDO of the JTAG port;
S2, searching out an operation command of the target flash according to a data manual of a read-write test, including commands of erasing, deprotection, write buffering, programming, reading and the like, and completely converting the commands into binary sequence codes according to characteristic parameters of a JTAG interface and a certain format;
S3, converting data and addresses written into the flash, a write control time sequence and the like into binary sequence codes, and enabling the flash to recognize correct operation when the binary sequence codes are transmitted to a control bus of the flash chip through a JTAG port;
S4, the binary sequence codes obtained by converting the step S2 and the step S3 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
S5, the computer software reads back a feedback signal TDO data line of the JTAG port through the parallel port card;
S6, converting a target address and a control time sequence of the read flash chip into a binary sequence code;
S7, the binary sequence codes obtained by converting the step S6 and the step S2 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
S8, the computer software reads back a feedback signal TDO data line of the JTAG port through the parallel port card;
S9, comparing the data written in the flash with the read data according to a binary format by the computer software.
The S1 comprises the following steps:
S101, accessing a JTAG interface of the system-on-chip into a parallel port of a computer.
S102, binary sequence code 11111111 is sent to the TDI data line of the JTAG interface by using control software.
S103, the binary sequence code 10100001010 is sent to a TDI data line of the JTAG interface by using control software.
S104, observing a TDO data line of the JTAG interface by using a DSO of the digital oscilloscope, and calculating the instruction length of the JTAG interface.
S105, binary sequence code 00000000 is sent to the TDI data line of the JTAG interface by using control software.
S106, binary sequence codes 0000101000 and 0000010000 are circularly and alternately sent to a TDO data line of the JTAG interface for 100 times by using control software.
S107, observing a TDO data line of the JTAG interface by using a DSO of the digital oscilloscope, and calculating the data length of the JTAG interface.
S108, repeating the steps S102-S107, and simultaneously, referring the clock line TCK speed of the JTAG interface to 20M so as to calculate the highest transmission speed of the JTAG interface.
In step S5, it is determined whether the write operation of step S4 is successful, and if not, the execution is resumed from step S3; if successful, the data is written into the target flash, and then step S6 is executed.
In step S8, it is determined whether the read operation of step S7 is successful, and if not, the execution is resumed from step S6; if so, the data indicating the target address of the flash chip is saved in the local hard disk file of the computer, and then step S9 is executed.
In step S9, if the flash read-write test is the same, the flash read-write test is successful, and the operation is ended; if not, the flash read-write test fails, and the flash read-write test needs to be executed again from the step S3.
The invention provides a read-write test method for bypassing a system chip on a fixed film to perform flash of a memory chip, which has the following working principle:
Firstly, a plurality of groups of specific binary sequence codes are sent to a data line TDI of a JTAG port through a parallel port of a computer, and by means of an oscilloscope, the instruction length, the data length and the highest transmission speed of the JTAG port can be calculated through a code stream observed on the data line TDO of the JTAG port; then, converting operation instructions (erasure, programming and reading) corresponding to the specification model of the flash chip to be read-write tested into corresponding binary sequence codes according to characteristic parameters (register length and transmission speed) of a JTAG interface, and finally loading the binary sequence codes into a parallel port card of a computer; the parallel port card can automatically match the level of the JTAG interface and sequentially move the sequence codes into pins of the system-on-chip, meanwhile, an internal control logic circuit of the system-on-chip is automatically isolated, and finally, the binary sequence codes are accurately transmitted to a control bus of the flash chip, so that the full-automatic read-write test of the flash memory chip is realized.
Compared with the related art, the read-write test method for bypassing the system-on-a-chip-customized chip to perform the flash of the memory chip has the following beneficial effects:
The invention has wide application range, does not need to know and master the control logic of the system-on-chip with complex working principle, has no relation with the model, specification and manufacturer of the system-on-chip, can be suitable for the maintenance test of circuit boards of a plurality of manufacturers, and solves the problems of non-ideal maintenance period, cost and quality.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (4)
1. A read-write test method for carrying out flash of a storage chip by bypassing a system-on-a-chip customization chip is characterized by comprising the following steps:
S1, firstly, a plurality of groups of binary sequence codes are sent to a data line TDI of a JTAG interface through a parallel port of a computer, and by means of an oscilloscope, the instruction length, the data length and the highest transmission speed of the JTAG interface can be calculated through a code stream observed on the data line TDO of the JTAG interface;
the S1 specifically comprises the following steps:
S101, accessing a JTAG interface of a system-on-chip into a parallel port of a computer;
S102, using control software to send binary sequence code 11111111 to TDI data line of JTAG interface;
S103, using control software to send binary sequence codes 10100001010 to a TDI data line of a JTAG interface;
S104, observing a TDO data line of the JTAG interface by using a DSO of the digital oscilloscope, and calculating the instruction length of the JTAG interface;
s105, the binary sequence code 00000000 is sent to a TDI data line of a JTAG interface by using control software;
S106, the binary sequence codes 0000101000 and 0000010000 are circularly and alternately transmitted to a TDO data line of the JTAG interface for 100 times by using control software;
S107, observing a TDO data line of the JTAG interface by using a DSO of a digital oscilloscope, and calculating the data length of the JTAG interface;
S108, repeating the steps S102-S107, and simultaneously, referring the clock line TCK speed of the JTAG interface to 20M so as to calculate the highest transmission speed of the JTAG interface;
s2, searching out an operation command of the target flash according to a data manual of the target flash for read-write test, including erasing, deprotection, write buffering, programming and read commands, and completely converting the operation command into a binary sequence code according to characteristic parameters of a JTAG interface and a certain format;
s3, converting the data and the address written into the flash into a binary sequence code, and enabling the flash to recognize correct operation when the binary sequence code is transmitted to a control bus of the flash chip through a JTAG interface;
S4, the binary sequence codes obtained by converting the step S2 and the step S3 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
s5, the computer software reads back a feedback signal TDO data line of the JTAG interface through the parallel port card;
S6, converting a target address and a control time sequence of the read flash chip into a binary sequence code;
S7, the binary sequence codes obtained by converting the step S6 and the step S2 are sequentially sent to a parallel port card by utilizing software operated by a computer, and are sent to a JTAG interface of a system-on-chip after the level is converted by the parallel port card, and are further sent to a target flash chip;
s8, the computer software reads back a feedback signal TDO data line of the JTAG interface through the parallel port card;
S9, comparing the data written in the flash with the read data according to a binary format by the computer software.
2. The method for performing read-write test of the memory chip flash by bypassing the system-on-a-chip of the customized tape according to claim 1, wherein in the step S5, it is determined whether the write operation of the step S4 is successful, and if not, the step S3 is performed again; if successful, the data is written into the target flash, and then step S6 is executed.
3. The method for performing read-write test of the memory chip flash by bypassing the system-on-a-chip of the customized package according to claim 1, wherein in the step S8, it is determined whether the read operation of the step S7 is successful, and if not, the step S6 is performed again; if so, the data indicating the target address of the flash chip is saved in the local hard disk file of the computer, and then step S9 is executed.
4. The method for performing flash read-write test of the memory chip by bypassing the system-on-a-chip of the customized chip according to claim 1, wherein in the step S9, if the same is the case, the flash read-write test is successful, and the operation is ended; if not, the flash read-write test fails, and the flash read-write test needs to be executed again from the step S3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010716342.9A CN113971982B (en) | 2020-07-23 | 2020-07-23 | Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010716342.9A CN113971982B (en) | 2020-07-23 | 2020-07-23 | Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113971982A CN113971982A (en) | 2022-01-25 |
| CN113971982B true CN113971982B (en) | 2024-10-01 |
Family
ID=79585307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010716342.9A Active CN113971982B (en) | 2020-07-23 | 2020-07-23 | Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113971982B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744052A (en) * | 2002-03-11 | 2006-03-08 | 华为技术有限公司 | Storage unit on-board measuring method |
| CN101315812A (en) * | 2008-03-20 | 2008-12-03 | 上海交通大学 | On-line Programming Method of FLASH Memory Based on Parallel Port |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6925583B1 (en) * | 2002-01-09 | 2005-08-02 | Xilinx, Inc. | Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device |
| CN100487668C (en) * | 2006-10-10 | 2009-05-13 | 北京中电华大电子设计有限责任公司 | Regulating technology of built-in processor |
| CN101329385B (en) * | 2008-08-01 | 2011-08-24 | 炬力集成电路设计有限公司 | Regulation test system and method of on-chip system as well as on-chip system |
| CN101713814B (en) * | 2009-12-18 | 2011-08-24 | 南京航空航天大学 | Flash chip detection method based on boundary scan |
| CN101996687A (en) * | 2010-10-27 | 2011-03-30 | 山东大学 | Built-in system test method of multiple static random access memory (SRAM) based on scanning test |
| CN102486939B (en) * | 2010-12-06 | 2014-08-13 | 普天信息技术研究院有限公司 | Method and apparatus for testing joint test action group (JTAG) of memories |
| CN106569162B (en) * | 2016-10-17 | 2019-04-02 | 深圳市鼎阳科技有限公司 | A kind of the analog bandwidth measurement method and device of logic analyser probe |
| CN108121672B (en) * | 2017-08-08 | 2024-05-24 | 鸿秦（北京）科技有限公司 | Storage array control method and device based on NandFlash storage multichannel |
| CN108648780B (en) * | 2017-12-19 | 2020-10-16 | 北京时代民芯科技有限公司 | Memory test system, method and storage medium |
-
2020
- 2020-07-23 CN CN202010716342.9A patent/CN113971982B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744052A (en) * | 2002-03-11 | 2006-03-08 | 华为技术有限公司 | Storage unit on-board measuring method |
| CN101315812A (en) * | 2008-03-20 | 2008-12-03 | 上海交通大学 | On-line Programming Method of FLASH Memory Based on Parallel Port |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113971982A (en) | 2022-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6681353B1 (en) | Methods and apparatus for obtaining a trace of a digital signal within a field programmable gate array device | |
| US7856582B2 (en) | Techniques for logic built-in self-test diagnostics of integrated circuit devices | |
| CN113190394A (en) | SOC chip-oriented multi-clock-domain concurrent test system and test method thereof | |
| JP2002215712A (en) | Method of verifying ic design | |
| CN1828553A (en) | System on Chip and Test/Debugging Method Applied thereto | |
| JP4334463B2 (en) | Semiconductor integrated circuit test apparatus and method | |
| CN114639439B (en) | Chip internal SRAM test method and device, storage medium and SSD device | |
| CN112685239A (en) | Automatic test system and method for multi-core DSP + FPGA framework processing circuit | |
| US20020163351A1 (en) | Method for producing test patterns for testing an integrated circuit | |
| CN117234831B (en) | Chip function test method and system based on multi-core CPU | |
| US6707313B1 (en) | Systems and methods for testing integrated circuits | |
| CN113160875A (en) | Chip test system and test method | |
| CN109283451B (en) | A system and method for detecting good quality of integrated circuits | |
| WO2007113940A1 (en) | Semiconductor test device | |
| CN103345944B (en) | Storage device and method for testing storage device through test machine | |
| CN202120623U (en) | Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 | |
| US11662383B2 (en) | High-speed functional protocol based test and debug | |
| CN113971982B (en) | Read-write test method for bypassing system-on-a-chip-customized chip to perform flash of memory chip | |
| CN114816868A (en) | Method for realizing serial interface chip test | |
| CN100372094C (en) | Wafer testing device with automatic recovery function and wafer testing method | |
| US6536020B2 (en) | Efficient generation of optimum test data | |
| CN117709251A (en) | ARINC429 interface automatic verification system and method based on SV | |
| CN109801664A (en) | FPGA configuration memory test method | |
| CN112597002A (en) | Python script based test vector generation method | |
| CN102262205B (en) | A kind of screen method of test point of test vector source file and shield assembly |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |