CN113764459A - Low-temperature magnetic superconducting hybrid storage unit and memory - Google Patents
Low-temperature magnetic superconducting hybrid storage unit and memory Download PDFInfo
- Publication number
- CN113764459A CN113764459A CN202111045202.4A CN202111045202A CN113764459A CN 113764459 A CN113764459 A CN 113764459A CN 202111045202 A CN202111045202 A CN 202111045202A CN 113764459 A CN113764459 A CN 113764459A
- Authority
- CN
- China
- Prior art keywords
- superconducting
- magnetic
- voltage
- tunnel junction
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005291 magnetic effect Effects 0.000 title claims abstract description 142
- 230000015654 memory Effects 0.000 title claims abstract description 86
- 238000003860 storage Methods 0.000 title claims abstract description 32
- 239000002070 nanowire Substances 0.000 claims abstract description 63
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 230000001105 regulatory effect Effects 0.000 claims abstract description 10
- 230000008859 change Effects 0.000 claims abstract description 9
- 230000006870 function Effects 0.000 claims abstract description 5
- 230000005415 magnetization Effects 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 13
- 230000005294 ferromagnetic effect Effects 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000395 magnesium oxide Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical group [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- ZDZZPLGHBXACDA-UHFFFAOYSA-N [B].[Fe].[Co] Chemical compound [B].[Fe].[Co] ZDZZPLGHBXACDA-UHFFFAOYSA-N 0.000 claims description 2
- FQMNUIZEFUVPNU-UHFFFAOYSA-N cobalt iron Chemical compound [Fe].[Co].[Co] FQMNUIZEFUVPNU-UHFFFAOYSA-N 0.000 claims description 2
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910003321 CoFe Inorganic materials 0.000 description 1
- 229910019236 CoFeB Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
Landscapes
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
The invention provides a low-temperature magnetic superconducting hybrid storage unit and a memory, wherein the storage unit comprises: the voltage regulating magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube are arranged in series or in parallel; the voltage-controlled magnetic anisotropy magnetic tunnel junction comprises a reference layer, a barrier layer and a free layer which are sequentially overlapped; the superconducting nanowire cryotube is a three-terminal device and comprises a channel end, a source end and a drain end, and gate current is applied to the channel end to control the change of the resistance of the channel end, so that the superconducting nanowire cryotube can realize a logic switch with a gating function. The storage unit is formed by combining the voltage-controlled magnetic anisotropy magnetic tunnel junction and the superconducting nanowire low-temperature tube, the advantages of the voltage-controlled magnetic anisotropy magnetic tunnel junction and the superconducting nanowire low-temperature tube are fully combined, the compatibility of the two technologies is considered, the read-write speed (with sub-nanosecond write-in speed) of the existing storage unit can be remarkably improved, the power consumption is effectively reduced, the unit integration density is increased, and the method is particularly suitable for the field of large-scale low-temperature storage.
Description
Technical Field
The present invention relates to the field of integrated circuit memories, and more particularly, to a low temperature magnetic superconducting hybrid memory cell and memory.
Background
Since the invention of integrated circuits, high performance computing has become an important driving force for technological and scientific progress, and with the development of technology and the continuous reduction of device size in the field of integrated circuits, silicon materials are gradually approaching the limit of processing, moore's law is slowed down, and the increase of leakage current and interconnection delay become the bottleneck of the traditional CMOS memory.
Superconducting computers have been a more powerful candidate than Moore computers, with the advantages of lower power consumption, faster speed, etc. However, the technology of the superconducting memory is not mature, the superconducting memory meeting the application requirements cannot be realized in a short period of time, and the technology of the high-capacity and ultra-high-speed low-temperature memory becomes one of the key bottlenecks restricting the development of the superconducting computer. The memory cell size based on the Single Flux Quantum (SFQ) technique is large, requiring tens of μm2The area of the memory limits the development and application of the memory. One approach to providing high density RAM for low temperature superconducting computers is to use a conventional CMOS based memory and SFQ-to-CMOS interface. However, the density, delay, and wiring requirements of the separate SFQ and CMOS dies limit the application of such hybrid SFQ/CMOS technologies.
Magnetic random access memory (STT-MRAM) is a typical spin-torque magnetic random access memory (STT-MRAM), and due to its unique properties, the STT-MRAM attracts more and more attention, such as non-volatility, fast read/write speed, low power consumption, simple cell structure, high array density, good compatibility with CMOS process, and expandability. The basic memory bit of an MRAM is a Magnetic Tunneling Junction (MTJ), which is composed of two ferromagnetic layers sandwiching a very thin non-ferromagnetic insulating material, wherein the Magnetic moment direction of one of the ferromagnetic layers is fixed, called the reference layer; another layer, called the free layer, whose magnetic moment is variable in direction, so that the magnetization direction of the free layer can be parallel or antiparallel to the magnetization direction of the reference layer, and its resistance can be changed by changing the magnetization direction of the different layers, these spin-based devices can be used as memory elements. When the magnetic moment directions of the free layer and the reference layer are consistent, the resistance of the MTJ device presents a low resistance state, which can represent a logic state of "0"; when the magnetic moment directions of the free layer and the reference layer are opposite, the resistance of the MTJ device assumes a high resistance state, which may represent a logic state "1". However, STT-MRAM requires a large write current to write data, and dynamic power consumption is high.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a low-temperature magnetic superconducting hybrid memory cell and a memory, which are used to solve the problems of low read/write speed, high dynamic power consumption, low integration density, etc. of the prior art magnetic random access memory.
To achieve the above and other related objects, the present invention provides a cryogenic magnetic superconducting hybrid memory cell, comprising:
the voltage regulating magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube are arranged in series or in parallel;
the voltage-controlled magnetic anisotropy magnetic tunnel junction comprises a reference layer, a barrier layer and a free layer which are sequentially overlapped, wherein the magnetization direction of the reference layer is fixed and unchanged, and the magnetization direction of the free layer can be turned between a P state parallel to the magnetization direction of the reference layer and an AP state antiparallel to the magnetization direction of the reference layer;
the superconducting nanowire cryotube is a three-terminal device and comprises a channel end, a source end and a drain end, and gate current is applied to the channel end to control the change of the resistance of the channel end, so that the superconducting nanowire cryotube can realize a logic switch with a gating function.
Optionally, the reference layer and the free layer are made of ferromagnetic metal.
Further, the ferromagnetic metal comprises at least one of the group consisting of a cobalt iron material, a cobalt iron boron material, and a nickel iron material.
Optionally, the material of the barrier layer is an oxide or graphene.
Further, the oxide is magnesium oxide or aluminum oxide.
Optionally, the superconducting nanowire cryostraw is made of NbN or NbTiN.
Optionally, the superconducting nanowire cryostraw comprises nTron, h-Tron, M-nTron or y-nTron.
Optionally, the voltage-controlled magnetic anisotropic magnetic tunnel junction is cylindrical, cubic or truncated cone-shaped.
The present invention also provides a cryogenic magnetic superconducting hybrid memory, the memory comprising:
a plurality of memory cells, word lines, bit lines and source lines as described above;
the memory cells are arranged to form a memory array, each row of the memory cells is connected with the bit line and the source line, and each column of the memory cells is connected with the word line.
Optionally, the voltage-controlled magnetic anisotropic magnetic tunnel junction in the storage unit is connected in series with the drain terminal of the superconducting nanowire cryostraw; the voltage-regulated magnetic anisotropic magnetic tunnel junctions in each row of the storage units are connected with the bit lines, and the source ends of the superconducting nanowire cryotubes are connected with the source lines; and the channel end of the superconducting nanowire cryostraw in each column of the storage units is connected with the word line.
Optionally, the voltage-controlled magnetic anisotropic magnetic tunnel junction in the storage unit is arranged in parallel with the superconducting nanowire cryostraw; one end of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the drain end of the superconducting nanowire low-temperature tube in each row of the storage units are connected with the bit line, and the other end of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the source end of the superconducting nanowire low-temperature tube are connected with the source line; and the channel end of the superconducting nanowire cryostraw in each column of the storage units is connected with the word line.
As described above, the low-temperature magnetic superconducting hybrid memory cell and the memory of the present invention combine the voltage-controlled magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube to form a memory cell, fully combine the advantages of the two, and consider the compatibility of the two processes, thereby significantly improving the read-write speed (with sub-nanosecond write speed) of the existing memory cell, effectively reducing power consumption, increasing the cell integration density, and being particularly suitable for the field of large-scale low-temperature memories.
Drawings
FIG. 1 is a schematic diagram of a structure of a voltage-controlled magnetic anisotropic magnetic tunnel junction in a low-temperature magnetic superconducting hybrid memory cell according to the present invention.
FIG. 2 shows the off-voltage V in the LTPS hybrid memory cell of the present inventionbAnd the schematic diagram of the influence on the energy barrier of the voltage regulation magnetic anisotropy magnetic tunnel junction magnetization state.
Fig. 3 is a schematic diagram showing the structure of the superconducting nanowire cryotube in the cryogenic magnetic superconducting hybrid memory cell of the present invention, wherein no current is injected into the channel end of the superconducting nanowire cryotube.
Fig. 4 is a schematic structural diagram illustrating a heat island formed after injecting current Igate into a channel end of the superconducting nanowire cryostraw in fig. 3.
Fig. 5 is a schematic structural diagram of a memory cell in a cryogenic magnetic superconducting hybrid memory according to a first embodiment of the invention.
Fig. 6 is a schematic structural diagram of a memory array in a cryogenic magnetic superconducting hybrid memory according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a memory cell in a cryogenic magnetic superconducting hybrid memory according to a second embodiment of the invention.
Fig. 8 is a schematic structural diagram of a memory array in a cryogenic magnetic superconducting hybrid memory according to a second embodiment of the invention.
Description of the element reference numerals
10 memory cell
11 voltage regulated magnetic anisotropy magnetic tunnel junction
111 reference layer
112 barrier layer
113 free layer
12 superconductive nanowire cryotube
121 source end
122 drain terminal
123 channel end
13 word line
14 bit line
15 source line
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 4, the present invention provides a cryogenic magnetic superconducting hybrid memory cell, the memory cell comprising:
a Voltage-Controlled Magnetic anisotropic Magnetic Tunnel Junction 11 (VCMA-MTJ for short) and a superconducting nanowire cryotron 12(nanocryotron) which are arranged in series or in parallel;
as shown in fig. 1 and 2, the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 includes a reference layer 111, a barrier layer 112, and a free layer 113 stacked in sequence, wherein the magnetization direction of the reference layer 111 is fixed, and the magnetization direction of the free layer 113 is flipped between a P state parallel to the magnetization direction of the reference layer 111 and an AP state antiparallel to the magnetization direction of the reference layer 111;
as shown in fig. 3 and 4, the superconducting nanowire cryostraw 12 is a three-terminal device, and includes a channel end 123, a source end 121, and a drain end 123, and a gate current Igate is applied to the channel end 123 for controlling the resistance change of the channel end 123, so that the superconducting nanowire cryostraw 12 implements a logic switch with a gate control function.
As shown in fig. 2, the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 has two stable magnetization states, a P state and an AP state, wherein in the P state, the magnetization direction of the free layer 113 is parallel to the magnetization direction of the reference layer 111, and the device has a low resistance characteristic; in the AP state, the magnetization direction of the free layer 113 is antiparallel to the magnetization direction of the reference layer 111, and the device exhibits high resistance. The information can be stored by this feature, and for example, the P state represents a logic state "0", and the AP state represents a logic state "1". As can be seen from fig. 2, when the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 is switched between two stable magnetization states (P state and AP state), a certain energy barrier needs to be overcome, the size of the energy barrier is affected by an external voltage Vb, when Vb increases, the energy barrier between the P state and the AP state decreases, which is beneficial to switching the state of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11, and from the perspective of the energy barrier, when the energy barrier is completely eliminated, a corresponding external voltage is called as a critical voltage Vc, and the switching state of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 is not only related to the size of the external voltage Vb, but also closely related to the loading time of the external voltage, i.e., the pulse width of the external voltage. The electric field/voltage (Vb) applied to the two ends of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 causes the accumulation of electron charges, and causes the change of interface atom orbitals and state density, thereby causing the change of interface magnetic anisotropy, and significantly reducing the current density required for magnetization reversal, thereby effectively reducing ohmic contact caused by current.
As shown in fig. 3 and 4, the superconducting nanowire cryostraw 12 is a superconducting nanowire three-terminal device, and an input gate current Igate is used to control the change of the resistance of the channel end 123, the gate end of the superconducting nanowire cryostraw 12 receives a current signal to the channel end 123, the source end 121 is grounded, the drain end 122 is connected to a bias current Ibias, and a current pulse Igate injected into the gate end is formed by a small-range heat island to regulate and control a circuit of a superconducting wire perpendicular to the gate end, so as to trigger the nanowire channel to change from a superconducting state to a normal resistance state, so that the nanowire channel can drive a large-impedance load, and has a strong fan-out capability. The logic switch with the gating function is used as a superconducting switch, has the advantages of small size, high speed, low power consumption and high output impedance, and can provide a quick selection switch for the low-temperature magnetic superconducting hybrid storage unit under the extremely low temperature condition (4.2K).
The low-temperature magnetic superconducting hybrid storage unit disclosed by the invention is formed by combining the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 and the superconducting nanowire low-temperature tube 12, the advantages of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube are fully combined, and meanwhile, the compatibility of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube in the process is considered, so that the read-write speed (with sub-nanosecond write-in speed) of the conventional storage unit can be obviously improved, the power consumption is effectively reduced, the unit integration density is increased, and the low-temperature magnetic superconducting hybrid storage unit is particularly suitable for the field of large-scale low-temperature storage.
As an example, the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 and the superconducting nanowire cryostraw 12 can be compatibly prepared, and the specific steps generally include: providing a semiconductor silicon substrate, and forming a silicon dioxide layer on the surface of the semiconductor silicon substrate; then, sequentially forming each layer of the magnetic tunnel junction on the bottom electrode from bottom to top by adopting a conventional deposition process (such as a chemical vapor deposition process, a physical vapor deposition process, ion beam epitaxy, atomic layer deposition, magnetron sputtering and the like); then forming the voltage-controlled magnetic anisotropy magnetic tunnel junction 11 through photoetching, etching and other processes; then preparing a superconducting film in a fixed area of the semiconductor silicon substrate, wherein the superconducting film is prepared by a molecular beam epitaxy method, an electron beam evaporation method, a pulse laser deposition method, a magnetron sputtering method and the like; etching by utilizing photoetching and reactive ion etching methods to form the superconducting nanowire cryostraw 12, and leading out a top layer electrode; and finally, performing series or parallel metal interconnection on the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 and the superconducting nanowire low-temperature tube 12 to finally form the storage unit.
As an example, the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 may be in a cylindrical shape (as shown in fig. 1), a cubic shape, or a truncated cone shape with an elliptical cross section, so as to reduce the cost and facilitate continuous size miniaturization, and is suitable for various memory structures such as a dual-interface structure and a multi-interface structure. However, the invention is not limited thereto, and in other examples, other shapes may be selected, specifically, according to actual needs, and are not limited herein.
As shown in fig. 1, the material of the reference layer 111 and the free layer 113 may be a ferromagnetic metal, for example, the ferromagnetic metal may be a single or mixed metal material formed by at least one of CoFe, CoFeB, or NiFe, wherein the ratio of the mixed metal materials may be the same or different. The material of the barrier layer 112 may be an oxide, which may be magnesium oxide, MgO, or aluminum oxide, Al, or graphene, etc2O3And one of the oxides is used for generating tunneling magnetoresistance effect. In practical applications, the ferromagnetic metal and the oxide may also be made of other suitable materials, and are not limited herein.
As shown in fig. 3, the material of the superconducting nanowire cryostraw 12 may be selected from NbN material or NbTiN material, for example.
As shown in fig. 3, the superconducting nanowire cryostraw 12 may be implemented with nTron, and various conventional variants, such as h-Tron, M-nTron, y-nTron, and so on, as examples.
As shown in fig. 5 to 8, the present invention also provides a cryogenic magnetic superconducting hybrid memory, comprising:
a plurality of memory cells 10, word lines 13, bit lines 14, and source lines 15 as described above;
the memory cells 10 are arranged to form a memory array, each row of the memory cells 10 is connected to the bit line 14 and the source line 15, and each column of the memory cells 10 is connected to the word line 13.
The cryomagnetic superconducting hybrid memory of the present invention will be described in detail with reference to specific embodiments.
Example one
As shown in fig. 5 and 6, the present embodiment provides a low temperature magnetic superconducting hybrid memory, which includes a plurality of memory cells 10, word lines 13, bit lines 14, and source lines 15.
A plurality of the storage units 10 are arranged to form a storage array, and the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 in the storage unit 10 is connected in series with the drain 122 of the superconducting nanowire cryotron 12; the voltage-controlled magnetic anisotropic magnetic tunnel junctions 11 in each row of the storage units 10 are connected with the bit lines 14, and the source ends 121 of the superconducting nanowire cryotubes 12 are connected with the source lines 15; the channel end 123 of the superconducting nanowire cryotubes 12 in each column of the memory cells 10 is connected to the word line 13.
After the bit line 14 and the source line 15 are powered on, the superconducting nanowire cryotron 12 is in a superconducting state under a low-temperature condition, and the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 is subjected to 0 and 1 state inversion by controlling inversion voltage and pulse time under the action of a voltage pulse Vb to realize data storage; when the word line 13 is powered on, due to the heat island effect, the channel end of the superconducting nanowire cryostraw 12 changes to a normal-temperature high-resistance state, the channel is disconnected, and the superconducting nanowire cryostraw 12 is not selected.
Example two
As shown in fig. 7 and 8, the present embodiment provides a low temperature magnetic superconducting hybrid memory, which includes a plurality of memory cells 10, word lines 13, bit lines 14, and source lines 15.
A plurality of storage units 10 are arranged to form a storage array, and the voltage-controlled magnetic anisotropic magnetic tunnel junctions 11 in the storage units 10 are arranged in parallel with the superconducting nanowire cryotubes 12; one end of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 and the drain 122 of the superconducting nanowire cryostraw 12 in each row of the memory cells 10 are connected to the bit line 14, and the other end of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 and the source 121 of the superconducting nanowire cryostraw 12 are connected to the source line 15; the channel end 123 of the superconducting nanowire cryotubes 12 in each column of the memory cells 10 is connected to the word line 13.
When the bit line 14 and the source line 15 are powered on, the power-on voltage Vb is less than Vc (Vc is the critical voltage of the voltage-controlled magnetic anisotropic magnetic tunnel junction), the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 cannot be turned over under the action of the voltage pulse, but the energy barrier for switching two stable magnetization states can be reduced, at the moment, the superconducting nanowire cryotube 12 is in a superconducting state, and current is discharged along the end of a channel; when the word line 13 is powered on, due to the heat island effect, the channel end of the superconducting nanowire low-temperature tube 12 is changed into a normal-temperature high-resistance state, the channel is disconnected, current passes through the voltage-regulated magnetic anisotropic magnetic tunnel junction 11, and based on the STT effect, the current overcomes the reduced energy barrier to enable the voltage-regulated magnetic anisotropic magnetic tunnel junction 11 to be turned over from a 0 state to a 1 state for data storage; after the memory cell is selected, the 1-to-0 state switching of the voltage-controlled magnetic anisotropic magnetic tunnel junction 11 can be realized by changing the voltage polarities on the bit line 14 and the source line 15.
In summary, the invention provides a low-temperature magnetic superconducting hybrid memory cell and a memory, wherein the voltage-controlled magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube are combined to form the memory cell, so that the advantages of the two are fully combined, and meanwhile, the compatibility of the two processes is considered, so that the read-write speed (with sub-nanosecond write speed) of the existing memory cell can be remarkably improved, the power consumption is effectively reduced, the integration density of the cell is increased, and the memory cell and the memory are particularly suitable for the field of large-scale low-temperature memories. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (11)
1. A cryogenic magnetic superconducting hybrid memory cell, the memory cell comprising:
the voltage regulating magnetic anisotropic magnetic tunnel junction and the superconducting nanowire low-temperature tube are arranged in series or in parallel;
the voltage-controlled magnetic anisotropy magnetic tunnel junction comprises a reference layer, a barrier layer and a free layer which are sequentially overlapped, wherein the magnetization direction of the reference layer is fixed and unchanged, and the magnetization direction of the free layer can be turned between a P state parallel to the magnetization direction of the reference layer and an AP state antiparallel to the magnetization direction of the reference layer;
the superconducting nanowire cryotube is a three-terminal device and comprises a channel end, a source end and a drain end, and gate current is applied to the channel end to control the change of the resistance of the channel end, so that the superconducting nanowire cryotube can realize a logic switch with a gating function.
2. The cryogenic magnetic superconducting hybrid memory cell of claim 1, wherein: the reference layer and the free layer are made of ferromagnetic metal.
3. The cryogenic magnetic superconducting hybrid memory cell of claim 2, wherein: the ferromagnetic metal comprises at least one of the group consisting of a cobalt iron material, a cobalt iron boron material, and a nickel iron material.
4. The cryogenic magnetic superconducting hybrid memory cell of claim 1, wherein: the barrier layer is made of oxide or graphene.
5. The cryomagnetic superconducting hybrid memory cell of claim 4, wherein: the oxide is magnesium oxide or aluminum oxide.
6. The cryogenic magnetic superconducting hybrid memory cell of claim 1, wherein: the superconducting nanowire low-temperature tube is made of NbN or NbTiN.
7. The cryogenic magnetic superconducting hybrid memory cell of claim 1, wherein: the superconducting nanowire cryogenic tube comprises nTron, h-Tron, M-nTron or y-nTron.
8. The cryogenic magnetic superconducting hybrid memory cell of claim 1, wherein: the voltage-controlled magnetic anisotropy magnetic tunnel junction is cylindrical, cubic or truncated cone-shaped.
9. A cryogenic magnetic superconducting hybrid memory, the memory comprising:
a plurality of memory cells, word lines, bit lines and source lines according to any one of claims 1 to 8;
the memory cells are arranged to form a memory array, each row of the memory cells is connected with the bit line and the source line, and each column of the memory cells is connected with the word line.
10. The cryogenic magnetic superconducting hybrid memory of claim 9, wherein: the voltage-regulated magnetic anisotropic magnetic tunnel junction in the storage unit is connected with the drain end of the superconducting nanowire low-temperature tube in series; the voltage-regulated magnetic anisotropic magnetic tunnel junctions in each row of the storage units are connected with the bit lines, and the source ends of the superconducting nanowire cryotubes are connected with the source lines; and the channel end of the superconducting nanowire cryostraw in each column of the storage units is connected with the word line.
11. The cryogenic magnetic superconducting hybrid memory of claim 9, wherein: the voltage-regulated magnetic anisotropic magnetic tunnel junction in the storage unit is connected with the superconducting nanowire low-temperature tube in parallel; one end of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the drain end of the superconducting nanowire low-temperature tube in each row of the storage units are connected with the bit line, and the other end of the voltage-controlled magnetic anisotropic magnetic tunnel junction and the source end of the superconducting nanowire low-temperature tube are connected with the source line; and the channel end of the superconducting nanowire cryostraw in each column of the storage units is connected with the word line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111045202.4A CN113764459A (en) | 2021-09-07 | 2021-09-07 | Low-temperature magnetic superconducting hybrid storage unit and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111045202.4A CN113764459A (en) | 2021-09-07 | 2021-09-07 | Low-temperature magnetic superconducting hybrid storage unit and memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113764459A true CN113764459A (en) | 2021-12-07 |
Family
ID=78793629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111045202.4A Pending CN113764459A (en) | 2021-09-07 | 2021-09-07 | Low-temperature magnetic superconducting hybrid storage unit and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113764459A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002184A1 (en) * | 2004-06-30 | 2006-01-05 | Headway Technologies, Inc. | Novel underlayer for high performance magnetic tunneling junction MRAM |
| US20080217710A1 (en) * | 2007-03-08 | 2008-09-11 | Magic Technologies, Inc. | Novel SyAF structure to fabricate Mbit MTJ MRAM |
| CN102664153A (en) * | 2012-05-08 | 2012-09-12 | 肖德元 | Superconductive field effect transistor as well as manufacturing method and application method thereof |
| CN103151457A (en) * | 2011-12-07 | 2013-06-12 | 三星电子株式会社 | Magnetic device and method of manufacturing the same |
| CN103323796A (en) * | 2013-06-21 | 2013-09-25 | 中国人民解放军国防科学技术大学 | MTJ magnetic field sensor using graphene as barrier layer |
| US20160035404A1 (en) * | 2014-07-29 | 2016-02-04 | Raytheon Bbn Technologies Corp. | Magnetic ram array architecture |
| US9761793B1 (en) * | 2016-05-18 | 2017-09-12 | Samsung Electronics Co., Ltd. | Magnetic memory device and method for manufacturing the same |
| US20190096461A1 (en) * | 2017-09-22 | 2019-03-28 | Toshiba Memory Corporation | Memory device |
| CN109638151A (en) * | 2018-12-04 | 2019-04-16 | 中国科学院上海微系统与信息技术研究所 | Storage unit, cryogenic memory and its reading/writing method |
| CN109860192A (en) * | 2019-02-28 | 2019-06-07 | 中国科学院上海微系统与信息技术研究所 | Memory array structure and preparation method, memory and wiring method and reading method |
| US20210167277A1 (en) * | 2019-12-02 | 2021-06-03 | HeFeChip Corporation Limited | Magnetic memory device and method for manufacturing the same |
-
2021
- 2021-09-07 CN CN202111045202.4A patent/CN113764459A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060002184A1 (en) * | 2004-06-30 | 2006-01-05 | Headway Technologies, Inc. | Novel underlayer for high performance magnetic tunneling junction MRAM |
| US20080217710A1 (en) * | 2007-03-08 | 2008-09-11 | Magic Technologies, Inc. | Novel SyAF structure to fabricate Mbit MTJ MRAM |
| CN103151457A (en) * | 2011-12-07 | 2013-06-12 | 三星电子株式会社 | Magnetic device and method of manufacturing the same |
| CN102664153A (en) * | 2012-05-08 | 2012-09-12 | 肖德元 | Superconductive field effect transistor as well as manufacturing method and application method thereof |
| CN103323796A (en) * | 2013-06-21 | 2013-09-25 | 中国人民解放军国防科学技术大学 | MTJ magnetic field sensor using graphene as barrier layer |
| US20160035404A1 (en) * | 2014-07-29 | 2016-02-04 | Raytheon Bbn Technologies Corp. | Magnetic ram array architecture |
| US9761793B1 (en) * | 2016-05-18 | 2017-09-12 | Samsung Electronics Co., Ltd. | Magnetic memory device and method for manufacturing the same |
| US20190096461A1 (en) * | 2017-09-22 | 2019-03-28 | Toshiba Memory Corporation | Memory device |
| CN109638151A (en) * | 2018-12-04 | 2019-04-16 | 中国科学院上海微系统与信息技术研究所 | Storage unit, cryogenic memory and its reading/writing method |
| CN109860192A (en) * | 2019-02-28 | 2019-06-07 | 中国科学院上海微系统与信息技术研究所 | Memory array structure and preparation method, memory and wiring method and reading method |
| US20210167277A1 (en) * | 2019-12-02 | 2021-06-03 | HeFeChip Corporation Limited | Magnetic memory device and method for manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| PEDRAM KHALILI AMIRI 等: ""Electric-Field-Controlled Magnetoelectric RAM:Progress, Challenged, and Scaling"", 《IEEE TRANSACTIONS ON MAGNETICS》, vol. 51, no. 11, 10 June 2015 (2015-06-10), pages 1 - 7, XP011587641, DOI: 10.1109/TMAG.2015.2443124 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11264089B1 (en) | Superconducting devices with ferromagnetic barrier junctions | |
| Guo et al. | Spintronics for energy-efficient computing: An overview and outlook | |
| US11790968B2 (en) | Spintronic device, SOT-MRAM storage cell, storage array and in-memory computing circuit | |
| US7932571B2 (en) | Magnetic element having reduced current density | |
| US9747968B2 (en) | Magnetic RAM array architecture | |
| US8976577B2 (en) | High density magnetic random access memory | |
| US20130070513A1 (en) | Method and apparatus for direct backup of memory circuits | |
| US8750036B2 (en) | Unipolar spin-transfer switching memory unit | |
| US9159409B2 (en) | Method and apparatus for providing complimentary state retention | |
| US9070456B2 (en) | High density magnetic random access memory | |
| CN109638151B (en) | Storage unit, low-temperature storage and reading and writing method thereof | |
| CN111986717A (en) | SOT-MRAM (spin on demand-random Access memory) without external magnetic field oriented spin reversal and array | |
| US8194436B2 (en) | Magnetic random access memory, write method therefor, and magnetoresistance effect element | |
| US20240005974A1 (en) | Self-reference storage structure and storage and calculation integrated circuit | |
| CN109860192B (en) | Memory array structure and preparation method thereof, memory and writing method and reading method | |
| CN116403624B (en) | Track transfer torque magnetic random storage device and implementation method thereof | |
| CN113764459A (en) | Low-temperature magnetic superconducting hybrid storage unit and memory | |
| CN109524035B (en) | Memory cell, embedded memory and read-write method thereof | |
| CN113451355B (en) | Spin orbit torque based magnetic memory device | |
| Zhang et al. | High-Density 1T1D1SOT-MRAM with Multi-Mode Ultrahigh-Speed Magnetization Switching | |
| Sverdlov et al. | CMOS technology compatible magnetic memories | |
| Takemura et al. | Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond | |
| Xuel et al. | High-Density STT-Assisted SOT-MRAM (SAS-MRAM) for Energy-Efficient AI Application | |
| Wang et al. | Spin-orbitronics memory device with matching and self-reference functionality | |
| CN112201747A (en) | Magnetic memory structure, read-write method and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |