CN113589609B

CN113589609B - GOA circuit, display panel and display device

Info

Publication number: CN113589609B
Application number: CN202110804633.8A
Authority: CN
Inventors: 刘净
Original assignee: TCL China Star Optoelectronics Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2023-04-04
Anticipated expiration: 2041-07-16
Also published as: CN113589609A

Abstract

The application provides a GOA circuit, display panel and display device, wherein, the GOA circuit is applied to display panel, includes: a plurality of connecting lines; a plurality of clock signal lines, at least one of the clock signal lines including a first portion and a second portion, the first portion having a width greater than a width of the second portion; and the GOA circuit units are connected with the second parts of the corresponding clock signal lines through the connecting lines. This application sets into first portion and second portion with clock signal line, and the width of second portion is less than the width of first portion, compares in prior art this embodiment and sets up the second portion that connecting wire and clock signal line and be connected, has reduced the area of contact of connecting wire and clock signal line, and then has improved the problem that there is electrostatic discharge to take place easily in clock signal line and connecting wire junction.

Description

GOA circuit, display panel and display device

[ technical field ] A method for producing a semiconductor device

The application relates to the technical field of liquid crystal display, in particular to a GOA circuit, a display device and a display device.

[ background of the invention ]

An Array substrate line driving (GOA, gate Driver On Array or Gate On Array) circuit is a technology for manufacturing a Gate line (Gate) line scanning driving signal circuit On an Array substrate by using the existing thin film transistor display device (TFT-LCD) Array (Array) manufacturing process so as to realize the driving mode of scanning the Gate line by line.

However, in the conventional GOA circuit, there is a problem that electrostatic discharge is likely to occur at the connection between the clock signal line and the connection line.

[ application contents ]

The application aims to provide a GOA circuit, a display device and a display device, and solves the problem that electrostatic discharge easily occurs at the joint of a clock signal line and a connecting line in the conventional GOA circuit.

The technical scheme of the application is as follows: a GOA circuit applied to a display panel comprises:

a plurality of connecting lines;

a plurality of clock signal lines, at least one of the clock signal lines including a first portion and a second portion, the first portion having a width greater than a width of the second portion;

and the GOA circuit unit is connected with the second part of the corresponding clock signal line through the connecting line.

Optionally, the second portion includes a plurality of sub-signal lines, a total width of the plurality of sub-signal lines is smaller than a width of the first portion, and the plurality of sub-signal lines located in the same clock signal line are all connected to one end of one of the connection lines.

Optionally, the widths of the plurality of sub-signal lines located in the same clock signal line are all equal.

Optionally, the plurality of sub-signal lines located in the same clock signal line are arranged at the same distance.

Optionally, the second portion includes a first sub-signal line and a second sub-signal line that are disposed at an interval, the first sub-signal line is located between the second sub-signal line and the GOA circuit, the side of the first sub-signal line facing the GOA circuit is flush with the side of the first portion facing the GOA circuit, and the side of the second sub-signal line away from the GOA circuit is flush with the side of the first portion away from the GOA circuit.

Optionally, the second portion includes at least one sub-signal line, and the number of the sub-signal lines is between 1 and 10.

Optionally, the plurality of clock signal lines are arranged at equal intervals.

Optionally, each of the clock signal lines includes a plurality of the first portions and a plurality of the second portions, and the first portions and the second portions are disposed at intervals.

The present embodiment further provides a display panel, where the display panel includes the GOA circuit described in any one of the above embodiments.

The embodiment also provides a display device, which comprises the display panel.

The beneficial effect of this application lies in: the GOA circuit is applied to the display panel and comprises a plurality of connecting lines, a plurality of clock signal lines and a GOA circuit unit, wherein at least one clock signal line comprises a first part and a second part, and the width of the first part is larger than that of the second part. The GOA circuit unit is connected with the second part of the corresponding clock signal line through a connecting line, and the connecting line and the second part are arranged on the same layer. This application sets up first portion and second portion with clock signal line, and the width of second portion is less than the width of first portion, compares and is connected through the connecting wire with the first portion of clock signal line among the prior art, and this embodiment sets up the second portion that the connecting wire is connected with clock signal line, has reduced the area of contact of connecting wire with clock signal line, and then has improved the problem that there is the easy electrostatic discharge that takes place in clock signal line and connecting wire junction.

[ description of the drawings ]

Fig. 1 is a schematic diagram of a first structure of a GOA circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a clock line in the GOA circuit shown in FIG. 1;

fig. 3 is a schematic diagram of a second structure of a GOA circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of a third structure of a GOA circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a fourth structure of a GOA circuit according to an embodiment of the present disclosure.

[ detailed description ] embodiments

The accompanying drawings, which are included to provide a further understanding of the application, are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application without limiting the application in any way. It is obvious that the drawings in the following description are only some embodiments, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. The present application will be further described with reference to the accompanying drawings and embodiments.

The GOA (Gate Driver on Array) technology is a row driving technology of an Array substrate, which is a driving method for implementing line-by-line scanning of a Gate by fabricating a Gate driving circuit on a TFT Array substrate by using an Array process of a liquid crystal display panel. The GOA technology can reduce the welding procedures of the external IC, can improve the productivity and reduce the product cost, and can be more suitable for manufacturing narrow-frame or frameless display products. When the GOA circuit is used for scanning line by line, some clock signals (CK) are needed for control, a plurality of clock signal lines are arranged in parallel, a plurality of connecting lines are connected with the clock signal lines in a vertical cross mode, and the other ends of the connecting lines are connected with the GOA circuit, so that the effect of controlling the GOA circuit is achieved.

However, in the actual process, due to the signal loading on the CK line, the CK is generally wider, and the wider the CK line is, the more likely the electrostatic Discharge (Electro-Static Discharge) occurs at the climbing position where the CK line is connected with the connection line, thereby causing panel damage and yield problems.

Based on the above problems, the present embodiment provides a GOA circuit, a display device and a display device to solve the above problems, which will be described in detail below with reference to the accompanying drawings.

Referring to fig. 1 to 3, fig. 1 is a first schematic structural diagram of a GOA circuit provided in an embodiment of the present disclosure, fig. 2 is a schematic structural diagram of a clock signal line in the GOA circuit shown in fig. 1, and fig. 3 is a second schematic structural diagram of the GOA circuit provided in the embodiment of the present disclosure. The present embodiment provides a GOA circuit 100, where the GOA circuit 100 includes a plurality of connection lines 30, a plurality of clock signal lines 20, and a GOA circuit unit 10, where the clock signal lines 20 are used for transmitting clock signals. The at least one clock signal line 20 includes a first portion 210 and a second portion 220, the width of the first portion 210 is greater than the width of the second portion 220, the GOA circuit unit 10 is connected to the second portion 220 of the corresponding clock signal line 20 through a connection line 30, and the connection line 30 and the second portion 220 are disposed in the same layer. In the present embodiment, by connecting the connection line 30 in the GOA circuit 100 with the second portion 220 with a smaller width in the clock signal line 20, compared with the connection point between the connection line 30 and the clock signal line 20 in the prior art, the contact area between the connection line 30 and the clock signal line 20 is reduced, and the problem of electrostatic discharge at the connection point between the clock signal line 20 and the connection line 30 is further improved.

The second portion 220 includes at least one sub-signal line, the number of which is between 1 and 10. In some embodiments, the second portion 220 includes only one sub-signal line, the width of the second portion 220 is smaller than the width of the first portion 210, in other embodiments, the number of the sub-signal lines included in the second portion 220 is between 2 and 10, each sub-signal line is spaced apart from another sub-signal line, and the total width of the plurality of sub-signal lines is smaller than the width of the first portion 210.

Illustratively, when the second portion 220 includes only one sub-signal line, the width of the sub-signal line is smaller than that of the first portion 210. It can be understood that the width of the first portion 210 can be as small as possible under the condition that the normal output signal of the clock signal line 20 is ensured, so as to reduce the connection area of the connection line 30 and the clock signal line 20.

It should be noted that the arrangement position of the sub-signal lines may be arbitrary, and for example, in some embodiments, the side of the sub-signal lines facing the GOA circuit 100 may be flush with the side of the first portion 210 facing the GOA circuit 100. In some embodiments, a side of the sub-signal line away from GOA circuit 100 is flush with a side of first portion 210 away from GOA circuit 100. In some embodiments, the sub-signal lines may not be flush with a side of the second portion 220 facing the GOA circuit 100, nor with a side of the second portion 220 away from the GOA circuit 100. The specific position of the sub-signal line may be set according to actual conditions, and is not limited specifically herein.

For example, when the second portion 220 includes the first sub-signal line 221 and the second sub-signal line 222, the first sub-signal line 221 and the second sub-signal line 222 are disposed at intervals, the width of the first sub-signal line 221 and the width of the second sub-signal line 222 may be equal or unequal, and the specific data of the width of the first sub-signal line 221 and the width of the second sub-signal line 222 are set according to practical application, and are not limited specifically herein.

When the first sub-signal line 221 is located between the second sub-signal line 222 and the GOA circuit 100, the side of the first sub-signal line 221 facing the GOA circuit 100 is flush with the side of the first portion 210 facing the GOA circuit 100, and the side of the second sub-signal line 222 away from the GOA circuit 100 is flush with the side of the first portion 210 away from the GOA circuit 100. In some embodiments, a side of first sub-signal line 221 facing GOA circuit 100 is flush with a side of first portion 210 facing GOA circuit 100, and a side of second sub-signal line 222 away from GOA circuit 100 is not flush with a side of first portion 210 away from GOA circuit 100. In some embodiments, the side of the first sub-signal line 221 facing the GOA circuit 100 is not flush with the side of the first portion 210 facing the GOA circuit 100, and the side of the second sub-signal line 222 facing away from the GOA circuit 100 is flush with the side of the first portion 210 facing away from the GOA circuit 100. In some embodiments, a side of first sub-signal line 221 facing GOA circuit 100 is not flush with a side of first portion 210 facing GOA circuit 100, and a side of second sub-signal line 222 away from GOA circuit 100 is not flush with a side of first portion 210 away from GOA circuit 100.

Illustratively, in conjunction with fig. 2, when the number of sub-signal lines is greater than or equal to 2, the widths of the plurality of sub-signal lines located in the second portion 220 of the same clock signal line 20 are all equal. It is understood that, in some embodiments, the widths of the plurality of sub-signal lines in the second portion 220 may not be equal, and the widths of the sub-signal lines may be reduced on the premise of ensuring that the clock signal line 20 outputs signals normally. Illustratively, the second portion 220 includes a first sub-signal line 221, a second sub-signal line 222, and a third sub-signal line 223, and the width of the third sub-signal line 223 may be reduced when the width of the first sub-signal line 221 and the width of the second sub-signal line 222 may ensure that the clock line outputs signals normally. In other embodiments, when the width of the first sub-signal line 221 and the width of the second sub-signal line 222 can ensure that the clock line can normally output signals, the second sub-signal line 222 may be configured as a plurality of sub-signal lines with smaller widths, the number of the plurality of sub-signal lines is not specifically limited herein, and it is only required to ensure that the sum of the widths of the plurality of sub-signal lines and the width of the first sub-signal line 221 can ensure that the clock line can normally output signals.

The plurality of sub-signal lines are disposed at the same distance, and illustratively, the second portion 220 includes a first sub-signal line 221, a second sub-signal line 222, and a third sub-signal line 223, and the distance between the first sub-signal line 221 and the second sub-signal line 222 is equal to the distance between the second sub-signal line 222 and the third sub-signal line 223. In some embodiments, a distance between the first sub-signal line 221 and the second sub-signal line 222 is greater than a distance between the second sub-signal line 222 and the third sub-signal line 223. In other embodiments, the distance between the first sub-signal line 221 and the second sub-signal line 222 is smaller than the distance between the second sub-signal line 222 and the third sub-signal line 223.

Referring to fig. 4 and 5, fig. 4 is a third schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure, and fig. 5 is a fourth schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure, where the GOA circuit 100 provided in this embodiment includes a plurality of clock signal lines 20, and the number of the clock signal lines 20 is 4, and the clock signal lines are respectively a first clock signal line 201, a second clock signal line 202, a third clock signal line 203, and a fourth clock signal line 204. It should be noted that, in other embodiments of the present invention, the number of the clock signal lines 20 may also be 2, 3 or more than 4, and the driving capability of the display panel can be adjusted for different GOAs, and the higher the driving capability is, the larger the number of the clock signals CK is. The specific number of the clock signal lines 20 is not limited in this application, and is set according to practical situations.

The plurality of clock signal lines 20 are sequentially arranged at intervals and parallel to each other in a direction away from the GOA at one side of the GOA circuit 100, the plurality of clock signal lines 20 are arranged at equal intervals, and in some embodiments, the distances between any two adjacent clock signal lines 20 are not equal.

The plurality of clock signal lines 20 have the same shape, each clock signal line 20 includes a plurality of first portions 210 and a plurality of second portions 220, and the first portions 210 and the second portions 220 are disposed at intervals and are sequentially connected. In some embodiments, the plurality of clock signal lines 20 are not all identical in shape, illustratively, the width of the first clock signal line 201 is greater than the width of the second clock signal line 202, and the width of the second clock signal line 202 is greater than the width of the third clock signal line 203. In other embodiments, when the width of the first portion 210 of the first clock signal line 201 and the width of the first portion 210 of the second clock signal are the same, the width of the second portion 220 of the first clock signal line 201 and the width of the second portion 220 of the second clock signal line 202 are different. In other embodiments, when the width of the first portion 210 of the first clock signal line 201 and the width of the first portion 210 of the second clock signal are the same, the sum of the widths of the second portions 220 of the first clock signal line 201 is the same as the sum of the widths of the second portions 220 of the second clock signal line 202, but the number, width, position, etc. of the sub-signal lines in the second portions 220 of the first clock signal line 201 and the number, width, position, etc. of the sub-signal lines in the second portions 220 of the second clock signal line 202 are different. It is understood that the plurality of clock signal lines 20 in the GOA circuit 100 may be the same or different, and the specific arrangement may be designed according to practical applications, and is not limited herein.

The connecting lines 30 are disposed at intervals, one end of each connecting line 30 is connected to the GOA unit, the other end is connected to the second portion 220 of the clock signal line 20, and the connecting lines 30 and the second portion 220 are disposed on the same layer. All the connecting lines 30 are arranged in the same layer and have the same thickness.

Illustratively, the connection lines include a first connection line 301, a second connection line 302, a third connection line 303, and a fourth connection line 304. One end of the first connection line 301 is connected to the GOA circuit unit 10, and the other end of the first connection line 301 is connected to the first clock signal line 201 adjacent to the GOA circuit unit 10. One end of the second connection line 302 is connected to the GOA circuit unit 10, and the other end of the second connection line 302 is connected to the second clock signal line 202 close to the GOA circuit unit 10. One end of the third connection line 303 is connected to the GOA circuit unit 10, and the other end of the third connection line 303 is connected to the third clock signal line 203 near the GOA circuit unit 10. One end of the fourth connection line 304 is connected to the GOA circuit unit 10, and the other end of the fourth connection line 304 is connected to the fourth clock signal line 204 close to the GOA circuit unit 10. The second portion 220 of the first clock signal line 201 connected to the first connection line 301, the second portion 220 of the second clock signal line 202 connected to the second connection line 302, the second portion 220 of the third clock signal line 203 connected to the third connection line 303, and the second portion 220 of the fourth clock signal line 204 connected to the fourth connection line 304 are not in the same layer, and are arranged in a staggered manner.

In some embodiments, since the clock signal line 20 far from the GOA circuit units 10 needs to cross over other clock signal lines 20 to transmit the corresponding clock signal to the corresponding GOA units, the clock signal line 20 and the connection line 30 may be arranged in different layers, and the clock signal line 20 is connected to the corresponding GOA units through the connection line 30 by using through holes, which is relatively simple and easy, and the thickness of the display panel can be reduced.

In some embodiments, the material used for all the connecting wires 30 is the same, for example, copper (Cu) or aluminum (Al).

In some embodiments, the equivalent resistance values of all the connecting lines 30 are the same. By designing the GOA circuit 100 with the resistances of the connecting wires 30 for transmitting signals, the situation that the input panel signals are different when the connecting wires 30 are different in resistance and lead to optical alignment is avoided, the difference of the input panel signals when optical alignment (HVA curing) is effectively improved, the line defect in the horizontal direction is avoided, and the product yield of the display panel is improved.

The GOA circuit 100 includes a plurality of GOA circuit units 10, and in some embodiments, a plurality of GOA circuit units 10 are cascaded, it being understood that the cascade relationship may be one stage after another, two stages after another, or multiple stages after another. The embodiment of the present application does not limit the cascade relationship between the GOA circuit units 10, and the cascade relationship between the GOA circuit units 10 may be set according to specific needs. For example, the alternate cascade between the GOA circuit units 10 is specifically: the level 1 GOA circuit unit 10 is electrically connected to the level 2 GOA circuit unit, the level 2 GOA circuit unit 10 is electrically connected to the level 3 GOA circuit unit 10, and so on, the level n-1 GOA circuit unit 10 is electrically connected to the level n GOA circuit unit 10. For another example, the two-stage cascade between the GOA circuit units 10 specifically includes: the level 1 GOA circuit unit 10 is electrically connected to the level 3 GOA circuit unit, the level 3 GOA circuit unit 10 is electrically connected to the level 5 GOA circuit unit 10, and so on, the level n-2 GOA circuit unit 10 is electrically connected to the level n GOA circuit unit 10, where n is a positive integer greater than 2.

The present application further provides a display panel, which includes any one of the above-mentioned GOA circuits 100. For details, see the above, and are not described herein again.

The present application further provides a display device, wherein the display device includes any one of the display panels, and specific details are described above, and are not repeated herein.

According to the invention, the clock signal line 20 is arranged into the first part 210 and the second part 220 with different widths, and the width of the second part 220 is smaller than that of the first part 210, so that the contact area between the connecting line 30 and the clock signal line 20 is reduced, and the problems of panel explosion and yield caused by electrostatic Discharge (Electro-Static Discharge) generated at the connecting part between the connecting line 30 and the clock signal line 20 in the prior art are solved. And while ensuring the normal output signal of the clock signal line 20, the second portion 220 is configured as a plurality of sub-signal lines with smaller width, which can effectively reduce the electrostatic discharge rate at the CK line, thereby improving the panel quality and yield. Moreover, the number, position, and width of the multiple sub-signal lines in the second portion 220 and the distance between the multiple sub-signal lines can be set according to practical application, so that multiple types of the GOA circuit 100 are increased, and the practicability of the GOA circuit 100 is further increased.

An ice making device and a refrigerator provided by the embodiments of the present application are described in detail above. The principles and embodiments of the present application have been described herein using specific guidelines, the above examples being provided only to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. The GOA circuit is applied to a display panel, and is characterized by comprising:

a plurality of connecting lines;

at least one of the clock signal lines comprises a first part and a second part, the width of the first part is larger than that of the second part, the second part comprises a plurality of sub signal lines, the total width of the plurality of sub signal lines is smaller than that of the first part, and the plurality of sub signal lines positioned on the same clock signal line are all connected to one end of one connecting line;

2. The GOA circuit according to claim 1, wherein the plurality of sub-signal lines on the same clock signal line have the same width.

3. The GOA circuit according to claim 1, wherein the plurality of sub-signal lines positioned in the same clock signal line are arranged at the same distance.

4. The GOA circuit of claim 1, wherein the second portion comprises a first sub-signal line and a second sub-signal line which are arranged at intervals, the first sub-signal line is located between the second sub-signal line and the GOA circuit, the side of the first sub-signal line facing the GOA circuit is flush with the side of the first portion facing the GOA circuit, and the side of the second sub-signal line facing away from the GOA circuit is flush with the side of the first portion facing away from the GOA circuit.

5. The GOA circuit of claim 1, wherein the second portion comprises at least one of the sub-signal lines, and wherein the number of the sub-signal lines is between 1 and 10.

6. The GOA circuit of claim 1, wherein the plurality of clock signal lines are arranged equidistant from one another.

7. The GOA circuit of claim 1, wherein each of the clock signal lines comprises a plurality of the first portions and a plurality of the second portions, the first portions and the second portions being spaced apart.

8. A display panel comprising the GOA circuit of any one of claims 1 to 7.

9. A display device characterized by comprising the display panel according to claim 8.