CN113517355B - Based on buried AlTiO 3 4H-SiC Schottky diode with terminal structure and preparation method thereof - Google Patents
Based on buried AlTiO 3 4H-SiC Schottky diode with terminal structure and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 22
- 230000002829 reductive effect Effects 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 104
- 238000005229 chemical vapour deposition Methods 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 14
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 230000002441 reversible effect Effects 0.000 abstract description 5
- 230000003068 static effect Effects 0.000 abstract description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 102
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 24
- 239000002184 metal Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 208000033830 Hot Flashes Diseases 0.000 description 1
- 206010060800 Hot flush Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention relates to a buried AlTiO-based material 3 A 4H-SiC schottky diode of a termination structure comprising: the N-type SiC epitaxial layer is internally provided with a plurality of buried terminal protection areas, the buried terminal protection areas are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode, the buried terminal protection areas are arranged in a step shape from top to bottom, and the distance between the buried terminal protection areas and two side surfaces of the N-type SiC epitaxial layer is sequentially reduced from top to bottom. The Schottky diode is provided with the plurality of buried terminal protection areas, and the buried terminal protection areas can gradually introduce the electric field concentration on the surface of the device into the device, so that the phenomenon of early breakdown of the device is avoided, the reliability of the device is improved, the reverse voltage endurance capability of the device under normal static characteristics is improved, the requirements on the surface passivation layer process in the preparation process of the device are reduced, and the overall preparation difficulty of the device is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a 4H-SiC Schottky diode based on a buried AlTiO3 terminal structure and a preparation method thereof.
Background
The SiC material has large forbidden bandwidth, high breakdown electric field, high saturation drift speed and high thermal conductivity, and the excellent properties of the material make the material an ideal material for manufacturing high-power, high-frequency, high-temperature-resistant and radiation-resistant devices. The silicon carbide Schottky diode has a series of advantages of high breakdown voltage, high current density, high working frequency and the like, so that the silicon carbide Schottky diode has a very wide development prospect. One of the main problems faced by current silicon carbide schottky diodes is to improve the reliability of the device application.
In order to achieve higher application reliability, from the device technology perspective, the surface metal edge region of the 4H-SiC schottky diode needs to be protected to reduce the electric field concentration phenomenon therein. In the conventional 4H-SiC power Schottky diode manufacturing process of a conventional structure, the part is formed by a specially designed P-type 4H-SiC terminal protection region, and is generally in a ring-shaped structure, and the transverse dimension and the spacing of the ring-shaped structure influence the electric field distribution. However, due to practical process errors, in reliability tests such as high-temperature reverse bias, hot flash reverse bias and the like, the phenomenon of concentration of a surface electric field is still obvious, so that leakage current of a device is increased, and the performance of the device is degraded.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a 4H-SiC Schottky diode based on a buried AlTiO3 terminal structure and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a buried AlTiO-based material 3 A 4H-SiC schottky diode of a termination structure comprising: an ohmic contact electrode, an N-type SiC substrate layer, an N-type SiC epitaxial layer and a Schottky contact electrode are sequentially stacked from bottom to top,
the N-type SiC epitaxial layer is internally provided with a plurality of buried terminal protection areas, the buried terminal protection areas are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode, the buried terminal protection areas are arranged in a step shape from top to bottom, and the distance between the buried terminal protection areas and two side surfaces of the N-type SiC epitaxial layer is sequentially reduced from top to bottom.
In one embodiment of the present invention, a distance between an upper surface of the buried termination protection region on the top layer and an upper surface of the N-type SiC epitaxial layer is 0.5 μm or less.
In one embodiment of the present invention, the spacing between the buried terminal protection areas increases from top to bottom.
In one embodiment of the invention, the spacing between the buried termination protection regions is increased from top to bottom in steps of 0.1 μm.
In one embodiment of the present invention, the buried termination protection region is made of AlTiO 3 Or AIN.
In one embodiment of the present invention, a plurality of P-type ion implantation regions are disposed in the N-type SiC epitaxial layer at intervals, the P-type ion implantation regions are located below the schottky contact electrode, and upper surfaces of the P-type ion implantation regions are in contact with the schottky contact electrode.
In one embodiment of the present invention, the buried AlTiO-based material 3 The 4H-SiC Schottky diode of the termination structure further comprises a passivation layer, wherein the passivation layer is arranged in a region, which is not covered by the Schottky contact electrode, on the N-type SiC epitaxial layer.
In one embodiment of the invention, the embedded AlTiO-based material 3 The 4H-SiC Schottky diode of the termination structure further comprises a protective layer, and the protective layer is arranged on the passivation layer.
The invention provides a buried AlTiO-based material 3 The preparation method of the 4H-SiC Schottky diode with the terminal structure comprises the following steps:
s1: forming a first 4H-SiC epitaxial layer on a 4H-SiC substrate;
s2: etching the first 4H-SiC epitaxial layer by using plasma dry etching to form a 4H-SiC groove region;
s3: depositing a buried terminal protection region in the 4H-SiC groove region by using a chemical vapor deposition technology;
s4: depositing a second 4H-SiC epitaxial layer on the surface of the device by using a chemical vapor deposition technology;
s5: repeating the steps S2-S4 to form a plurality of buried terminal protection areas;
s6: forming a P-type ion implantation region in the 4H-SiC epitaxial layer by utilizing ion implantation;
s7: forming a passivation layer on the surface of the 4H-SiC epitaxial layer through chemical vapor deposition;
s8: etching part of the passivation layer until the 4H-SiC epitaxial layer leaks out, and preparing a Schottky contact electrode on the leaked 4H-SiC epitaxial layer;
s9: preparing an ohmic contact electrode on the bottom surface of the 4H-SiC substrate;
s10: forming a protective layer on the passivation layer;
the buried terminal protection areas are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode, the buried terminal protection areas are arranged in a step shape from top to bottom, and the distances between the buried terminal protection areas and the two side surfaces of the 4H-SiC epitaxial layer are sequentially reduced from top to bottom.
In one embodiment of the present invention, the distance between the upper surface of the buried terminal protection region on the top layer and the upper surface of the 4H-SiC epitaxial layer is less than or equal to 0.5 μm, and the distances between the buried terminal protection regions tend to increase from top to bottom.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is based on buried AlTiO 3 The 4H-SiC Schottky diode with the terminal structure is provided with a plurality of step-shaped buried terminal protection areas, and the buried terminal protection areas can gradually introduce electric field concentration on the surface of the device into the device, so that on one hand, the phenomenon of early breakdown of the device is avoided, the reliability of the device is improved, and the reverse voltage withstand capability of the device under normal static characteristics is improved; on the other hand, as the electric field distribution is introduced into the device, the requirement on the surface passivation layer process in the device preparation process is reduced, thereby reducing the overall preparation difficulty of the device.
2. The invention is based on buried AlTiO 3 4H-SiC Schottky diode with terminal structure and AlTiO 3 Preparation of buried termination protection region due to AlTiO 3 The material belongs to a wide forbidden band material, has higher critical breakdown field strength, can optimize electric field distribution in a device, and is AlTiO 3 The matching degree of the material and the SiC material is good, and interface defects are fewer in the process of preparing the buried terminal protection region.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 shows an embodiment of the present invention based on buried AlTiO 3 4H-S of terminal structureSchematic structure of iC schottky diode;
FIG. 2 shows an embodiment of the present invention based on buried AlTiO 3 And a preparation method flow chart of the 4H-SiC Schottky diode with the terminal structure.
Icon: 1-ohmic contact electrode; a 2-N type SiC substrate layer; a 3-N type SiC epitaxial layer; a 4-Schottky contact electrode; 5-a buried terminal protection region; a 6-P type ion implantation region; 7-a passivation layer; 8-a protective layer.
Detailed Description
In order to further explain the technical means and effects adopted by the invention to achieve the preset aim, the invention provides a 4H-SiC Schottky diode based on a buried AlTiO3 terminal structure and a preparation method thereof, which are described in detail below with reference to the accompanying drawings and the specific embodiments.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a buried AlTiO-based system according to an embodiment of the present invention 3 The schematic structure of a 4H-SiC Schottky diode with a termination structure is shown in the figure, and the embodiment is used for burying AlTiO 3 A 4H-SiC schottky diode of a termination structure comprising: the ohmic contact electrode 1, the N-type SiC substrate layer 2, the N-type SiC epitaxial layer 3 and the Schottky contact electrode 4 are sequentially stacked from bottom to top.
In this embodiment, the ohmic contact electrode 1 includes an Ag metal layer and a Ni metal layer sequentially stacked from bottom to top, the N-type SiC substrate layer 2 and the N-type SiC epitaxial layer 3 are both N-type 4H-SiC materials, and the schottky contact electrode 4 includes a Ti metal layer and an Al metal layer sequentially stacked from bottom to top.
Further, a plurality of buried terminal protection areas 5 are arranged in the N-type SiC epitaxial layer 3, the buried terminal protection areas 5 are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode 4, the buried terminal protection areas 5 are arranged in a step shape from top to bottom, and the distance between the buried terminal protection areas and two side surfaces of the N-type SiC epitaxial layer 3 is sequentially reduced from top to bottom.
In this embodiment, a plurality of step-shaped buried terminal protection areas 5 are provided, and the buried terminal protection areas 5 can gradually introduce the electric field concentration on the surface of the device into the device, so that the phenomenon of advanced breakdown of the device is avoided, the reliability of the device is improved, and the reverse voltage withstand capability of the device under normal static characteristics is improved.
In this embodiment, the distance between the upper surface of the top buried termination protection region 5 and the upper surface of the N-type SiC epitaxial layer 3 is 0.5 μm or less, so as to achieve the desired effect of introducing the electric field concentration at the device surface from the surface into the device interior.
Furthermore, the intervals among the plurality of buried terminal protection areas 5 are in an increasing trend from top to bottom, so that the electric field distribution inside the device can be further balanced.
Optionally, the spacing between the buried termination protection regions 5 is increased in steps of 0.1 μm from top to bottom.
Optionally, the material of the buried terminal protection region 5 is AlTiO 3 Or AIN.
Preferably, alTiO is used 3 Preparation of buried termination protection region due to AlTiO 3 The material belongs to a wide forbidden band material, has higher critical breakdown field strength, can optimize electric field distribution in a device, and is AlTiO 3 The matching degree of the material and the SiC material is good, and interface defects are fewer in the process of preparing the buried terminal protection region.
It should be noted that, alternatively, the spacing between adjacent buried terminal protection regions 5 in the horizontal direction tends to increase from the center of the device to the two sides of the device, and in other embodiments, the spacing between adjacent buried terminal protection regions 5 in the horizontal direction is equal.
Further, a plurality of P-type ion implantation regions 6 are arranged in the N-type SiC epitaxial layer 3 at intervals, the P-type ion implantation regions 6 are located below the schottky contact electrode 4, and the upper surfaces of the P-type ion implantation regions 6 are in contact with the schottky contact electrode 4.
Further, the embodiment is based on buried AlTiO 3 The 4H-SiC Schottky diode of the terminal structure further comprises a passivation layer 7 and a protection layer 8, wherein the passivation layer 7 is arranged on the N-type SiC epitaxial layer 3 in a region which is not covered by the Schottky contact electrode 4. A protective layer 8 is provided on the passivation layer 7.
In the present embodiment, the passivation layer 7 is optionally SiO 2 The material, the protective layer 8 is polyimide protective layer.
Example two
The embodiment provides a buried AlTiO-based material 3 The preparation method of the 4H-SiC Schottky diode with the terminal structure is applicable to preparing the buried AlTiO-based diode in the first embodiment 3 Referring to fig. 2, fig. 2 shows a 4H-SiC schottky diode with a termination structure according to an embodiment of the present invention 3 The preparation method flow chart of the 4H-SiC Schottky diode with the terminal structure comprises the following steps:
s1: forming a first 4H-SiC epitaxial layer on a 4H-SiC substrate;
s2: etching the first 4H-SiC epitaxial layer by using plasma dry etching to form a 4H-SiC groove region;
s3: depositing a buried terminal protection region in the 4H-SiC groove region by using a chemical vapor deposition technology;
s4: depositing a second 4H-SiC epitaxial layer on the surface of the device by using a chemical vapor deposition technology;
s5: repeating S2-S4 to form a plurality of buried terminal protection areas;
s6: forming a P-type ion implantation region in the 4H-SiC epitaxial layer by utilizing ion implantation;
s7: forming a passivation layer on the surface of the 4H-SiC epitaxial layer through chemical vapor deposition;
s8: etching part of the passivation layer until the 4H-SiC epitaxial layer leaks out, and preparing a Schottky contact electrode on the leaked 4H-SiC epitaxial layer;
s9: preparing an ohmic contact electrode on the bottom surface of the 4H-SiC substrate;
s10: preparing and forming a protective layer on the passivation layer;
in this embodiment, the buried terminal protection regions are of a closed loop structure and sequentially wound around the periphery of the schottky contact electrode, and the buried terminal protection regions are arranged in a step shape from top to bottom, and the distances between the buried terminal protection regions and the two side surfaces of the 4H-SiC epitaxial layer are sequentially reduced from top to bottom. The distance between the upper surface of the top layer buried terminal protection area and the upper surface of the 4H-SiC epitaxial layer is smaller than or equal to 0.5 mu m, and the distances among the buried terminal protection areas are increased from top to bottom.
In the embodiment, the electric field concentration on the surface of the device is gradually introduced into the device by preparing the buried terminal protection region in a stepped shape, and the electric field distribution is introduced into the device, so that the requirement on the surface passivation layer process in the preparation process of the device is reduced, and the overall preparation difficulty of the device is reduced.
Further, taking four buried terminal protection regions as an example, the embodiment is based on buried AlTiO 3 The preparation method of the 4H-SiC Schottky diode with the terminal structure is specifically described. The method specifically comprises the following steps:
step 1: selecting an N-type 4H-SiC substrate, and preparing a first N-type 4H-SiC epitaxial layer on the N-type 4H-SiC substrate;
step 2: etching the front peripheral area of the first N-type 4H-SiC epitaxial layer by using plasma dry etching to form a first 4H-SiC groove area with a closed loop structure;
step 3: deposition of AlTiO in the first 4H-SiC trench region by chemical vapor deposition 3 Form a first AlTiO 3 Burying the terminal protection area, and then mechanically polishing the surface of the device;
step 4: depositing a second N-type 4H-SiC epitaxial layer on the surface of the mechanically polished device by using a chemical vapor deposition technology;
step 5: etching the peripheral area of the front surface of the second N-type 4H-SiC epitaxial layer by using plasma dry etching to form a second 4H-SiC groove area with a closed loop structure;
wherein the second 4H-SiC trench region has a smaller size than the first 4H-SiC trench region.
Step 6: deposition of AlTiO in the second 4H-SiC trench region by chemical vapor deposition 3 Forming a second AlTiO 3 Burying the terminal protection area, and then mechanically polishing the surface of the device;
step 7: depositing a third N-type 4H-SiC epitaxial layer on the surface of the mechanically polished device by using a chemical vapor deposition technology;
step 8: etching the peripheral area of the front surface of the third N-type 4H-SiC epitaxial layer by using plasma dry etching to form a third 4H-SiC groove area with a closed loop structure;
wherein the size of the third 4H-SiC trench region is smaller than the size of the second 4H-SiC trench region;
step 9: deposition of AlTiO in the third 4H-SiC trench region by chemical vapor deposition 3 Form a third AlTiO 3 Burying the terminal protection area, and then mechanically polishing the surface of the device;
wherein, the third AlTiO 3 Buried termination protection region and second AlTiO 3 The distance between the buried terminal protection regions is smaller than that of the second AlTiO 3 Buried terminal protection region and first AlTiO 3 The distance between the buried terminal protection areas.
Step 10: depositing a fourth N-type 4H-SiC epitaxial layer on the surface of the mechanically polished device by using a chemical vapor deposition technology;
step 11: etching the peripheral area of the front surface of the fourth N-type 4H-SiC epitaxial layer by using plasma dry etching to form a fourth 4H-SiC groove area with a closed loop structure;
wherein the fourth 4H-SiC trench region has a smaller size than the third 4H-SiC trench region.
Step 12: deposition of AlTiO in the fourth 4H-SiC trench region using chemical vapor deposition techniques 3 Forming a fourth AlTiO 3 Burying the terminal protection area, and then mechanically polishing the surface of the device;
wherein, the fourth AlTiO 3 Buried terminal protection region and third AlTiO 3 The distance between the buried terminal protection regions is smaller than that of the third AlTiO 3 Buried terminal protection region and the firstDiaaltio 3 The distance between the buried terminal protection areas.
Step 13: depositing a fifth N-type 4H-SiC epitaxial layer on the surface of the mechanically polished device by using a chemical vapor deposition technology;
wherein the thickness of the fifth N-type 4H-SiC epitaxial layer is 0.5 mu m.
Step 14: forming a plurality of P-type 4H-SiC injection regions at intervals by injecting Al ions in the front middle region of the device;
step 15: siO formation on device surface by chemical vapor deposition 2 Passivation layer, etched part of SiO 2 The passivation layer is used for leaking out the 4H-SiC epitaxial layer in the middle area of the device;
step 16: forming a Ni ohmic contact metal layer on the back of the device by utilizing magnetron sputtering, and then carrying out rapid thermal annealing on the whole device, wherein the annealing temperature is 1000 ℃ and the annealing time is 3min;
step 17: forming a Ti Schottky contact metal layer on the 4H-SiC epitaxial layer in the middle area of the device by utilizing magnetron sputtering, and then carrying out rapid thermal annealing on the whole device, wherein the annealing temperature is 450 ℃, and the annealing time is 3min;
step 18: forming an Ag contact layer on the surface of the Ni ohmic contact metal layer by utilizing electron beam evaporation, and forming an Al contact layer on the surface of the Ti Schottky contact metal layer;
step 19: in SiO 2 Forming a polyimide protective layer on the surface of the passivation layer by spin coating to finish the process based on the buried AlTiO 3 Preparation of a 4H-SiC Schottky diode with a terminal structure.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description and to simplify the description, and is not indicative or implying that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (9)
1. Based on buried AlTiO 3 A termination structure 4H-SiC schottky diode comprising: an ohmic contact electrode (1), an N-type SiC substrate layer (2), an N-type SiC epitaxial layer (3) and a Schottky contact electrode (4) are sequentially stacked from bottom to top,
a plurality of buried terminal protection areas (5) are arranged in the N-type SiC epitaxial layer (3), the buried terminal protection areas (5) are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode (4), the buried terminal protection areas (5) are arranged in a step shape from top to bottom, and the intervals between the buried terminal protection areas and two side surfaces of the N-type SiC epitaxial layer (3) are sequentially reduced from top to bottom;
the buried terminal protection region (5) is made of AlTiO 3 。
2. The buried AlTiO-based according to claim 1 3 The 4H-SiC Schottky diode with the terminal structure is characterized in that the distance between the upper surface of the buried terminal protection region (5) on the top layer and the upper surface of the N-type SiC epitaxial layer (3) is smaller than or equal to 0.5 mu m.
3. The buried AlTiO-based according to claim 1 3 The 4H-SiC Schottky diode with the terminal structure is characterized in that the spacing between a plurality of buried terminal protection areas (5) is increased from top to bottom.
4. A buried AlTiO-based according to claim 3 3 The 4H-SiC Schottky diode of the terminal structure is characterized in that the spacing between a plurality of buried terminal protection areas (5) is gradually increased from top to bottom in a step size of 0.1 mu m.
5. The buried AlTiO-based according to claim 1 3 The 4H-SiC Schottky diode with the terminal structure is characterized in that a plurality of P-type ion implantation areas (6) are arranged in the N-type SiC epitaxial layer (3) at intervals, the P-type ion implantation areas (6) are located below the Schottky contact electrode (4), and the upper surfaces of the P-type ion implantation areas (6) are in contact with the Schottky contact electrode (4).
6. The buried AlTiO-based according to claim 1 3 The 4H-SiC Schottky diode of the terminal structure is characterized by further comprising a passivation layer (7), wherein the passivation layer (7) is arranged in a region, which is not covered by the Schottky contact electrode (4), on the N-type SiC epitaxial layer (3).
7. The buried AlTiO-based material according to claim 6 3 The 4H-SiC Schottky diode of the terminal structure is characterized by further comprising a protective layer (8), wherein the protective layer (8) is arranged on the passivation layer (7).
8. Based on buried AlTiO 3 The preparation method of the 4H-SiC Schottky diode with the terminal structure is characterized by comprising the following steps of:
s1: forming a first 4H-SiC epitaxial layer on a 4H-SiC substrate;
s2: etching the first 4H-SiC epitaxial layer by using plasma dry etching to form a 4H-SiC groove region;
s3: depositing a buried terminal protection region in the 4H-SiC groove region by using a chemical vapor deposition technology;
s4: depositing a second 4H-SiC epitaxial layer on the surface of the device by using a chemical vapor deposition technology;
s5: repeating the steps S2-S4 to form a plurality of buried terminal protection areas;
s6: forming a P-type ion implantation region in the 4H-SiC epitaxial layer by utilizing ion implantation;
s7: forming a passivation layer on the surface of the 4H-SiC epitaxial layer through chemical vapor deposition;
s8: etching part of the passivation layer until the 4H-SiC epitaxial layer leaks out, and preparing a Schottky contact electrode on the leaked 4H-SiC epitaxial layer;
s9: preparing an ohmic contact electrode on the bottom surface of the 4H-SiC substrate;
s10: forming a protective layer on the passivation layer;
wherein the buried terminal protection areas are of a closed loop structure and sequentially wound on the periphery of the Schottky contact electrode, a plurality of the buried terminal protection areas are arranged in a ladder shape from top to bottom, the distance between the buried terminal protection areas and two side surfaces of the 4H-SiC epitaxial layer is sequentially reduced from top to bottom, and the buried terminal protection areas are made of AlTiO 3 。
9. The method of claim 8, wherein the spacing between the top surface of the buried termination protection region and the top surface of the 4H-SiC epitaxial layer is less than or equal to 0.5 μm, and the spacing between the buried termination protection regions increases from top to bottom.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303956A (en) * | 2002-04-11 | 2003-10-24 | Fuji Electric Co Ltd | Silicon carbide semiconductor device and manufacturing method thereof |
| CN106298967A (en) * | 2015-06-02 | 2017-01-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | Silicon carbide diode and preparation method thereof |
| CN108281491A (en) * | 2017-12-28 | 2018-07-13 | 厦门市三安集成电路有限公司 | A kind of silicon carbide power device and preparation method thereof with step structure |
| CN111653609A (en) * | 2020-06-05 | 2020-09-11 | 苏州凤凰芯电子科技有限公司 | JBS two-stage tube device structure with stepped structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8232558B2 (en) * | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
| US8796809B2 (en) * | 2008-09-08 | 2014-08-05 | Cree, Inc. | Varactor diode with doped voltage blocking layer |
| JP5455973B2 (en) * | 2011-05-27 | 2014-03-26 | 三菱電機株式会社 | Method for manufacturing silicon carbide semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303956A (en) * | 2002-04-11 | 2003-10-24 | Fuji Electric Co Ltd | Silicon carbide semiconductor device and manufacturing method thereof |
| CN106298967A (en) * | 2015-06-02 | 2017-01-04 | 中国科学院苏州纳米技术与纳米仿生研究所 | Silicon carbide diode and preparation method thereof |
| CN108281491A (en) * | 2017-12-28 | 2018-07-13 | 厦门市三安集成电路有限公司 | A kind of silicon carbide power device and preparation method thereof with step structure |
| CN111653609A (en) * | 2020-06-05 | 2020-09-11 | 苏州凤凰芯电子科技有限公司 | JBS two-stage tube device structure with stepped structure and manufacturing method thereof |
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Denomination of invention: 4H SiC Schottky diode based on buried AlTiO3terminal structure and preparation method Granted publication date: 20230721 Pledgee: Fuyang Zhejiang rural commercial bank Limited by Share Ltd. the Fuchun River branch Pledgor: Zhejiang Xinke Semiconductor Co.,Ltd. Registration number: Y2024980000125 |