CN113471207A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113471207A CN113471207A CN202010234316.2A CN202010234316A CN113471207A CN 113471207 A CN113471207 A CN 113471207A CN 202010234316 A CN202010234316 A CN 202010234316A CN 113471207 A CN113471207 A CN 113471207A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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Abstract
The embodiment of the invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor base, wherein the semiconductor base comprises a semiconductor substrate, a plurality of initial floating gate structures formed on the semiconductor substrate, and an isolation structure formed between adjacent initial floating gate structures and extending into the semiconductor substrate; etching back to remove part of the isolation material in the isolation structure to form a target groove exposing part of the side wall of the initial floating gate structure; removing residues on the side wall of the initial floating gate structure in the target groove; and thinning the side wall of the initial floating gate structure exposed by the target groove to form a target floating gate structure, wherein the method improves the performance of the device.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
As the demand for semiconductor memory devices has increased, semiconductor memory devices have received more attention. Flash memory (Flash), also known as Flash memory, has become the mainstream of non-volatile memory. Flash memories are classified into Nor Flash (Nor Flash) and NAND Flash (NAND Flash) according to their structures. The flash memory has the main characteristics of long-term storage information retention without power-on, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, thereby being widely applied to various fields such as microcomputer, automatic control and the like.
However, the electrical performance of the prior art flash memory is still to be improved.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same to improve device performance.
The invention provides a method for forming a semiconductor structure, which comprises the following steps:
providing a semiconductor base, wherein the semiconductor base comprises a semiconductor substrate, a plurality of initial floating gate structures formed on the semiconductor substrate, and an isolation structure formed between adjacent initial floating gate structures and extending into the semiconductor substrate;
back-etching to remove part of the isolation material in the isolation structure to form a target groove, wherein the target groove exposes part of the side wall of the initial floating gate structure;
removing residues on the side wall of the initial floating gate structure in the target groove;
and thinning the side wall of the initial floating gate structure exposed by the target groove to form a target floating gate structure.
An embodiment of the present invention further provides a semiconductor structure, including:
a semiconductor substrate;
a plurality of initial floating gate structures located on the semiconductor substrate;
a target recess between adjacent initial floating gate structures and an isolation material filled at the bottom of the target recess, wherein sidewalls of the initial floating gate structures on both sides of the target recess are completely exposed, the isolation material extending into the semiconductor substrate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the embodiment of the invention provides a semiconductor structure and a forming method thereof, wherein the method comprises the following steps: providing a semiconductor base, wherein the semiconductor base comprises a semiconductor substrate, a plurality of initial floating gate structures formed on the semiconductor substrate, and an isolation structure formed between adjacent initial floating gate structures and extending into the semiconductor substrate; etching back to remove part of the isolation material in the isolation structure to form a target groove exposing part of the side wall of the initial floating gate structure; removing residues on the side wall of the initial floating gate structure in the target groove; and thinning the side wall of the initial floating gate structure exposed by the target groove to form a target floating gate structure.
In the embodiment of the invention, before the step of thinning the side wall of the initial floating gate structure exposed by the target groove and forming the target floating gate structure, the residue on the side wall of the initial floating gate structure in the target groove is removed, so that the problem that the residue on the side wall of the initial floating gate structure obstructs the realization of related processes in the step of thinning the side wall of the initial floating gate structure can be avoided, the side wall of the initial floating gate structure exposed by the target groove can be thinned, the target floating gate structure with good appearance is formed, and the performance of a device is improved.
In addition, the embodiment of the invention eliminates the residues on the side wall of the initial floating gate structure in the target groove, and further avoids the problem of poor uniformity of the target floating gate structure caused by uneven distribution of the residues on the side wall of the initial floating gate structure.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 5-8 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 9 to 15 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the electrical performance of flash memory devices still needs to be improved. There are still reasons for improvement in electrical performance that have been analyzed in conjunction with a method of forming a semiconductor structure.
Specifically, in the prior art, an initial floating gate structure is usually refined (FG sliming process) to increase the distance between floating gate structures and to smooth the top of the floating gate structure, thereby avoiding the interference between bit lines and improving the reliability of the device. Referring to fig. 1 to fig. 3 in combination, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown. The forming method of the semiconductor structure comprises the following steps:
referring to fig. 1, a base (not labeled) is provided, the base comprising a semiconductor substrate 1, a plurality of initial floating gate structures 2 formed on the semiconductor substrate, isolation structures 3 formed between adjacent initial floating gate structures and extending into the semiconductor substrate;
referring to fig. 2, a portion of the isolation material in the isolation structure 3 is etched back to form a target recess 4, and the target recess 4 exposes a portion of the sidewall of the initial floating gate structure 2;
referring to fig. 3, the sidewalls of the initial floating gate structure exposed by the target recess are thinned to form the target floating gate structure 5.
By thinning the side wall of the initial floating gate structure, the distance between the formed target floating gate structures is further increased, so that the interference problem of adjacent bit lines of the device can be improved, and the reliability of the device is improved.
However, in the ideal target floating gate structure (i.e. the target floating gate structure 5 shown in fig. 3), the exposed sidewall portion of the target recess should present a smooth vertical state, however, referring to the structure diagram of the target floating gate structure actually formed by the above method shown in fig. 4, it can be seen that, in the target floating gate structure formed by the above method, the exposed sidewall portion of the target recess does not present an ideal state, but a bottle-shaped state with a small top size and a large bottom size, obviously, the topography of the target floating gate structure formed by the above method is not good.
The inventor researches and discovers that the reason for causing the poor appearance of the target floating gate structure is that in the step of thinning the side wall of the initial floating gate structure exposed by the target groove to form the target floating gate structure, residues which are not completely removed by the process before the step are attached to the side wall of the initial floating gate structure, and the residues obstruct the realization of the related process in the process of thinning the side wall of the initial floating gate structure exposed by the target groove, so that the step can not thin the side wall of the initial floating gate structure attached with the residues, and further the poor appearance of the target floating gate structure is caused.
Moreover, the residue is unevenly distributed on the side wall of the initial floating gate structure, so that the target floating gate structure formed by the process further has the problem of poor uniformity.
Based on this, the embodiment of the invention provides a method for forming a semiconductor structure and a semiconductor structure, wherein the method comprises the following steps: providing a semiconductor base, wherein the semiconductor base comprises a semiconductor substrate, a plurality of initial floating gate structures formed on the semiconductor substrate, and an isolation structure formed between adjacent initial floating gate structures and extending into the semiconductor substrate; etching back to remove part of the isolation material in the isolation structure to form a target groove exposing part of the side wall of the initial floating gate structure; removing residues on the side wall of the initial floating gate structure in the target groove; and thinning the side wall of the initial floating gate structure exposed by the target groove to form a target floating gate structure.
In the embodiment of the invention, before the step of thinning the side wall of the initial floating gate structure exposed by the target groove and forming the target floating gate structure, the residue on the side wall of the initial floating gate structure in the target groove is removed, so that the problem that the residue on the side wall of the initial floating gate structure obstructs the realization of related processes in the step of thinning the side wall of the initial floating gate structure can be avoided, the side wall of the initial floating gate structure exposed by the target groove can be thinned, the target floating gate structure with good appearance is formed, and the performance of a device is improved.
In addition, the embodiment of the invention eliminates the residues on the side wall of the initial floating gate structure in the target groove, and further avoids the problem of poor uniformity of the target floating gate structure caused by uneven distribution of the residues on the side wall of the initial floating gate structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a semiconductor substrate (not shown) is provided.
The semiconductor base includes a semiconductor substrate 100, a plurality of initial floating gate structures 120 formed on the semiconductor substrate, and isolation structures 140 formed between adjacent initial floating gate structures and extending into the semiconductor substrate.
The semiconductor substrate 100 provides a process platform for subsequent formation of flash memory. Specifically, the semiconductor substrate 100 is used to form a NAND Flash (NAND Flash) device.
In this embodiment, the semiconductor substrate 100 is used to form a core memory circuit. In other embodiments, the semiconductor substrate may also be used to form peripheral circuits, or to form core memory circuits and peripheral circuits.
Alternatively, the semiconductor substrate 100 in this embodiment may be a silicon substrate. In other embodiments, the material of the semiconductor substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the semiconductor substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration.
The initial floating gate structure 120 is used to form the target floating gate structure. The target floating gate structure is used for storing carriers in the formed flash memory, so that the flash memory has a data storage function. In this embodiment, the material of the initial floating gate structure 120 is polysilicon.
A gate oxide layer 110 is further formed between the initial floating gate structure 120 and the semiconductor substrate 100. The gate oxide layer 110 is used as an isolation layer between a target floating gate structure formed later and the semiconductor substrate 100, so that carriers stored in the target floating gate structure are prevented from entering the semiconductor substrate 100 in a data storage process, loss of the carriers is reduced, and data stored in the flash memory is prevented from being lost. In this embodiment, the material of the gate oxide layer 110 may be silicon oxide.
In an optional example, a hard mask layer 130 is further formed on the initial floating gate structure 120, and the hard mask layer 130 is used as an etching mask in the process of forming the isolation structure, so as to form an isolation trench for accommodating the isolation structure, and protect the top of the initial floating gate structure 120.
The hard mask layer 130 is made of a material different from that of the semiconductor substrate 100, and is used as an etching mask for forming an isolation trench by etching; moreover, the hard mask layer 130 is made of a material different from that of the isolation material of the isolation structure, so that etching loss to the isolation material is reduced when the hard mask layer 130 is removed.
Optionally, the hard mask layer 130 may be made of silicon nitride or silicon oxynitride. In this embodiment, the hard mask layer 130 is made of silicon nitride.
The isolation structure 140 is used to provide a process foundation for forming a shallow trench isolation structure. In the present embodiment, the isolation structure is formed between adjacent initial floating gate structures 120 and extends into the semiconductor substrate, so that the subsequently formed shallow trench isolation structure isolates the adjacent initial floating gate structures.
In this embodiment, the material of the isolation structure 140 may be silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
Referring to fig. 6, a portion of the isolation material in the isolation structure is etched back to form a target recess 150.
In the embodiment of the present invention, the target recess 150 exposes a portion of the sidewall of the initial floating gate structure 120, so as to provide a process space for performing the subsequent sidewall thinning of the initial floating gate structure 120.
In this step, the isolation material remaining at the bottom of the target recess 150 after formation of the target recess is used as a shallow trench isolation structure 160, and the shallow trench isolation structure 160 is used to isolate adjacent devices or device structures. It should be noted that, in the conventional process, the top surface of the shallow trench isolation structure formed at the bottom of the target recess is generally flush with the surface of the semiconductor substrate, or flush with the gate oxide layer on the semiconductor substrate. However, in the embodiments of the present invention, the residue on the sidewalls of the initial floating gate structure in the target recess is subsequently removed, and the removal step inevitably removes a portion of the isolation material on the top of the shallow trench isolation structure (i.e., the bottom of the target recess) at the same time. In order to offset the loss of the isolation material on the top of the shallow trench isolation structure caused by the cleaning step, in the present step, the target groove 150 is further formed, in which the bottom surface is higher than the surface of the semiconductor substrate 100, so that a certain margin is left on the top of the shallow trench isolation structure 160, thereby avoiding the problem of the isolation failure of the shallow trench isolation structure 160 after the cleaning step.
In this step, the distance D1 that the bottom surface of the target recess 150 (i.e., the top surface of the shallow trench isolation structure) is higher than the surface of the semiconductor substrate 100 should not be too large or too small. When the distance is too large, even if the clearing step is performed, the height D2 of the exposed sidewall of the initial floating gate structure in the target recess 150 is too small, so that the height D2 of the exposed and thinned sidewall of the initial floating gate structure is too small, which may not effectively improve the interference problem of the adjacent bit lines of the device, and the too small height may not effectively avoid the problem of the isolation failure of the shallow trench isolation structure 160 after the clearing step. Specifically, in the embodiment of the present invention, the distance D1 that the bottom surface of the target groove 160 (i.e., the top surface of the shallow trench isolation structure) is higher than the surface of the semiconductor substrate may be 1 to 400 angstroms, and optionally, the distance D1 that the bottom surface of the target groove 150 is higher than the surface of the semiconductor substrate 100 may be 100 angstroms, 200 angstroms or 300 angstroms, so that the sidewall of the initial floating gate structure with a suitable height is exposed while the problem of isolation failure that may occur after the shallow trench isolation structure 160 is removed is effectively avoided.
In this embodiment, referring to fig. 5 in combination, the isolation structure 140 may be etched back by using a dry etching process or a wet etching process, for example, using DHF (dilute hydrofluoric acid) to etch away the isolation material, or using a plasma etching process to etch back the isolation material.
It should be noted that, in this embodiment, a hard mask layer 130 is further formed on the initial floating gate structure, and the etch-back process may be performed by using the hard mask layer 130 as a mask.
Referring to fig. 7, the target recess 150 is cleared of residues located on the sidewalls of the initial floating gate structure 120.
The inventor researches and discovers that in combination with the residues on the sidewall of the initial floating gate structure 120 shown in fig. 6, due to the existence of the residues, the problem that the related processes are not easy to implement in the step of thinning the sidewall of the initial floating gate structure is caused, and by removing the residues on the sidewall of the initial floating gate structure, the residues on the sidewall of the initial floating gate structure can be prevented from hindering the implementation of the related processes in the step of thinning the sidewall of the initial floating gate structure, so that the sidewall of the initial floating gate structure exposed by the target recess can be thinned, and a target floating gate structure with good appearance is formed.
The residue on the sidewall of the initial floating gate structure 120 in the target recess 160 may be a separation material remaining on the sidewall of the initial floating gate structure, or may be a new polymer (i.e., an etching-back residue) generated in a back etching process, and based on a specific back etching process, the composition of the residue in this step may be determined, so as to perform a corresponding removal process.
In the embodiment of the invention, the residue is an isolation material, and correspondingly, a dry etching process can be adopted to remove the residue so as to better control the etching amount of the residual isolation material.
It should be noted that, in the embodiment of the present invention, when the residue is an isolation material, it is necessary to avoid using a wet etching process to remove the residue. The reason is that the wet etching has a higher etching rate on the isolation material at the bottom of the target groove when the isolation material is etched, so that excessive damage is easily caused on the shallow groove isolation structure at the bottom of the target groove, and the isolation effect of the shallow groove isolation structure is influenced.
In the dry etching process, in order to avoid etching damage to the initial floating gate structure, the selective etching ratio of the isolation material to the initial floating gate structure is greater than or equal to 10.
Specifically, the dry etching process may be a COR (Chemical oxide ETCH Chemical oxide etching) process, the adopted etching gas may be HF, and the corresponding etching parameters include: the etching temperature is 20-80 ℃, and the air pressure is 500-1000 mT. For example, the etching temperature may be 40 ℃ or 60 ℃, and the gas pressure may be 700mT or 900 mT.
In another alternative example, the residue is an isolation material, and a SiCoNi pre-clean process may be further used to remove the isolation material located on the sidewalls of the initial floating gate structure in the target recess. The SiCoNi precleaning process is originally a low-strength chemical etching method for removing an oxide film from the surfaces of cobalt silicon and nickel silicon, and the inventor researches that the method can be used for removing residues of an isolation material, so that the damage to a shallow trench isolation structure at the bottom of a target groove is reduced while the isolation material on the side wall of an initial floating gate structure is removed.
Specifically, the SiCoNi precleaning process adopts NF as the reaction gas3And NH3The reaction temperature is 32-38 ℃. For example, the reaction temperature may be 34 ℃ or 36 ℃.
In another embodiment of the present invention, the residue is an etching residue generated in the etching-back step, and accordingly, a wet etching process may be used to remove the residue, so as to remove the residue better.
In the wet etching process, the adopted etching solution is a mixed acid solution, and the mixed acid solution can be a mixed solution of a plurality of acid solutions of hydrochloric acid, nitric acid, sulfuric acid and hydrofluoric acid according to different components of the etching residues.
It should be noted that, in the embodiment of the present invention, with reference to fig. 6 and fig. 7, after the step of forming the target recess 150, the hard mask layer 130 may be further removed. Wherein, a wet etching process may be used to remove the hard mask layer 30. Based on the hard mask layer 30 being made of silicon nitride or silicon oxynitride, the etching solution used in the wet etching process is a phosphoric acid solution.
Referring to fig. 8, the sidewalls of the initial floating gate structure exposed by the target recess 160 are thinned to form a target floating gate structure 170.
By thinning the sidewall of the initial floating gate structure exposed by the target groove 160, the target floating gate structure 170 formed in the embodiment of the present invention can effectively improve the interference problem of adjacent bit lines of the device, and improve the reliability of the device.
In the embodiment of the invention, the thickness of the thinned sidewall of the initial floating gate structure is not too large or too small. The reason is that if the thinned thickness is too large, the target floating gate structure is too small, so that enough carriers cannot be stored, the performance of the device is reduced, and if the thinned thickness is too small, the interference problem of adjacent bit lines of the device cannot be effectively improved.
Illustratively, the thickness of the thinned sidewalls of the initial floating gate structure may be 10% or 20% of the thickness of the initial floating gate structure.
In this step, an etching process may be used to thin the sidewalls of the initial floating gate structure exposed by the target recess 160. In order to avoid damage to the isolation material caused by the etching process, in the etching process of the embodiment of the invention, the selective etching ratio of the initial floating gate structure to the isolation material is greater than or equal to 10.
In the embodiment of the present invention, before the step of thinning the sidewall of the initial floating gate structure exposed by the target recess 160 and forming the target floating gate structure, the residue on the sidewall of the initial floating gate structure in the target recess 160 is removed, so that the residue on the sidewall of the initial floating gate structure in the step of thinning the sidewall of the initial floating gate structure can be prevented from hindering the implementation of the related process, and the sidewall of the initial floating gate structure exposed by the target recess can be thinned, so that the target floating gate structure obtained by using the method for forming a semiconductor structure provided by the embodiment of the present invention can be effectively thinned, and the sidewall presents a smooth vertical state, that is, the target floating gate structure 170 with a good appearance is formed, and the performance of the device is improved.
In order to offset the loss of the shallow trench isolation structure caused by the cleaning step on the isolation material at the top of the shallow trench isolation structure, the embodiment of the invention further forms the target groove with the bottom surface higher than the surface of the semiconductor substrate in the step of forming the target groove, so that a certain margin is reserved at the top of the shallow trench isolation structure, and the loss of the isolation material at the top of the shallow trench isolation structure caused by the subsequent cleaning step is offset, thereby avoiding the problem of the isolation failure of the shallow trench isolation structure after the cleaning step.
In another embodiment of the present invention, a method for forming a semiconductor substrate is further provided, and with reference to fig. 9 to 15, a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention is shown, where the method includes:
referring to fig. 9, a semiconductor substrate 200 is provided;
alternatively, the substrate 200 in this embodiment may be a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
Referring to fig. 10, a gate oxide material layer 211, an initial floating gate material layer 221 and a hard mask material layer 231 are sequentially formed on the semiconductor substrate 200;
the gate oxide material layer is used for forming a gate oxide layer, the initial floating gate material layer is used for forming an initial floating gate structure, and the hard mask material layer is used for forming a hard mask layer.
The gate oxide material layer may be silicon oxide, the initial floating gate material layer may be polysilicon, the hard mask material layer may be silicon nitride or silicon oxynitride, and in this embodiment, the hard mask material layer is silicon nitride.
The forming process of the gate oxide material layer and the hard mask material layer can be a deposition process, and the forming process of the initial floating gate material layer can be an epitaxial growth process.
Referring to fig. 11, a pattern layer 250 is formed on the hard mask material layer, wherein the pattern layer 250 exposes a partial region of the hard mask material layer 231;
the pattern layer may be a patterned photoresist layer, and an exposed region of the pattern layer is a region for forming an isolation trench.
Referring to fig. 12, the hard mask material layer and the floating gate material layer are sequentially etched using the pattern layer 250 as a mask.
In this step, the remaining floating gate material layer after etching is used as the initial floating gate structure 220, and the remaining hard mask material layer is used as the hard mask layer 230.
The etching in this step may be a wet etching process to effectively remove the hard mask material layer and the floating gate material layer exposed by the pattern layer.
It should be noted that after this step, the graphics layer 250 is further removed. In other embodiments of the present invention, the graphic layer may be removed after any subsequent step.
Referring to fig. 13, the hard mask layer 230 is used as a mask to etch the gate oxide layer and the semiconductor substrate 200, and an isolation trench 201 is formed in the semiconductor substrate 200.
In this step, the etched residual gate oxide layer is used as the gate oxide layer 210.
The isolation trench is used for providing a process space for the subsequent formation of an isolation structure.
Specifically, the etching in this step may be a wet etching process to effectively remove the gate oxide layer and the semiconductor substrate 200 exposed by the hard mask layer 230.
Referring to fig. 14, an isolation material 241 is filled in the isolation trench, and the isolation material 241 covers the isolation trench and the top of the hard mask layer 230.
Wherein, a deposition process may be adopted to fill the isolation trench with an isolation material. The isolation material covers the isolation trench and the top of the hard mask layer 230, so that the isolation trench is effectively filled with the isolation material, and the surface of a subsequently formed isolation structure is prevented from being recessed.
Referring to fig. 15, a planarization process is used to remove the isolation material above the top of the hard mask layer 230.
Wherein the isolation material in the isolation trench is used as the isolation structure 240.
Referring to fig. 7, an embodiment of the present invention further provides a semiconductor structure, where the semiconductor structure includes:
a semiconductor substrate 100; a plurality of initial floating gate structures 120 located on the semiconductor substrate; a target recess 150 located between adjacent ones of the initial floating gate structures 120 and an isolation material 160 filled at the bottom of the target recess, wherein sidewalls of the initial floating gate structures 120 on both sides of the target recess 150 are completely exposed, and the isolation material 160 extends into the semiconductor substrate.
Specifically, the semiconductor substrate 100 in this embodiment may be a silicon substrate. In other embodiments, the material of the semiconductor substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the semiconductor substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate may be a material suitable for process requirements or easy integration.
The initial floating gate structure 120 serves to store carriers in the formed flash memory, thereby enabling the flash memory to function as a data storage device. In this embodiment, the material of the initial floating gate structure 120 is polysilicon.
It should be noted that a gate oxide layer 110 is further disposed between the initial floating gate structure 120 and the semiconductor substrate 100. The gate oxide layer 110 is used to prevent carriers stored in the floating gate structure from entering the semiconductor substrate 100 during data storage, thereby reducing the loss of carriers and preventing the loss of data stored in the flash memory. In this embodiment, the material of the gate oxide layer 110 may be silicon oxide.
The isolation material 160 forms a shallow trench isolation structure for isolating adjacent initial floating gate structures.
In this embodiment, the material of the isolation material 160 may be silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.
In the embodiment of the invention, the side walls of the initial floating gate structure at two sides of the target groove are completely exposed, so that the problem that the realization of related processes is hindered in the step of thinning the side wall of the initial floating gate structure when residues exist on the side wall of the initial floating gate structure can be avoided, the side wall of the initial floating gate structure exposed by the target groove can be thinned, a target floating gate structure with good appearance is formed, and the performance of a device is improved.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (20)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor base, wherein the semiconductor base comprises a semiconductor substrate, a plurality of initial floating gate structures formed on the semiconductor substrate, and an isolation structure formed between adjacent initial floating gate structures and extending into the semiconductor substrate;
back-etching to remove part of the isolation material in the isolation structure to form a target groove, wherein the target groove exposes part of the side wall of the initial floating gate structure;
removing residues on the side wall of the initial floating gate structure in the target groove;
and thinning the side wall of the initial floating gate structure exposed by the target groove to form a target floating gate structure.
2. The method of claim 1, wherein the step of etching back to remove a portion of the isolation material in the isolation structure to form a target recess has a bottom surface higher than a surface of the semiconductor substrate.
3. The method of claim 2, wherein a bottom surface of the target recess is located between 1 and 400 angstroms above a surface of the semiconductor substrate.
4. The method of forming a semiconductor structure of claim 1, wherein the residue is an isolation material.
5. The method for forming a semiconductor structure according to claim 4, wherein a dry etching process is used to remove residues on sidewalls of the initial floating gate structure in the target recess.
6. The method of forming a semiconductor structure of claim 5, wherein a selective etch ratio of the isolation material to the initial floating gate structure in the step of removing the residue on the sidewalls of the initial floating gate structure in the target recess by the dry etch process is greater than or equal to 10.
7. The method for forming a semiconductor structure according to claim 6, wherein in the step of removing the residue on the sidewall of the initial floating gate structure in the target recess by the dry etching process, the etching gas is HF, the etching temperature is 20 to 80 ℃, and the pressure is 500 to 1000 mT.
8. The method of claim 4, wherein a SiCoNi preclean process is used to remove residue on sidewalls of the initial floating gate structure in the target recess.
9. The method of claim 8, wherein the SiCoNi preclean process uses NF as the reactant gas3And NH3The reaction temperature is 32-38 ℃.
10. The method of claim 1, wherein the residue is a polymer generated in the etching back step.
11. The method for forming a semiconductor structure of claim 10, wherein a wet etch process is used to remove residue on sidewalls of said initial floating gate structure in said target recess.
12. The method for forming a semiconductor structure according to claim 11, wherein the etching solution used in the wet etching process is a mixed acid solution, and the mixed acid solution is a mixed solution of any of hydrochloric acid, nitric acid, sulfuric acid, and hydrofluoric acid.
13. The method of forming a semiconductor structure of claim 1, wherein said step of thinning the sidewalls of said initial floating gate structure exposed by said target recess to form a target floating gate structure, the thickness of the sidewalls of said initial floating gate structure is thinned to between 2% and 30% of the thickness of said initial floating gate structure.
14. The method of forming a semiconductor structure of claim 13, wherein sidewalls of the initial floating gate structure exposed by the target recess are thinned using an etching process, wherein a selective etch ratio of the initial floating gate structure and the isolation material in the etching process is greater than or equal to 10.
15. The method of forming a semiconductor structure of claim 1, wherein in said step of providing a semiconductor base, a gate oxide layer is further formed between said initial floating gate structure and said semiconductor substrate.
16. The method of forming a semiconductor structure of claim 15, wherein in the step of providing a semiconductor substrate, a hard mask layer is further formed on the initial floating gate structure;
after the step of removing a portion of the isolation material in the isolation structure to form the target recess, the method further includes:
and removing the hard mask layer.
17. The method of forming a semiconductor structure of claim 16, wherein the forming of the initial floating gate structure and the hard mask layer comprises:
providing a semiconductor substrate;
sequentially forming a gate oxide material layer, an initial floating gate material layer and a hard mask material layer on the semiconductor substrate;
forming a pattern layer on the hard mask material layer, wherein the pattern layer exposes partial area of the hard mask material layer;
and sequentially etching the hard mask material layer and the floating gate material layer exposed by the graph layer by taking the graph layer as a mask, taking the rest of the etched floating gate material layer as the initial floating gate structure, and taking the rest of the hard mask material layer as the hard mask layer.
18. The method of forming a semiconductor structure of claim 17, wherein the forming of the isolation structure comprises:
etching the gate oxide material layer and the semiconductor substrate by taking the hard mask layer as a mask, forming an isolation groove in the semiconductor substrate, and taking the etched residual gate oxide material layer as the gate oxide layer;
filling an isolation material in the isolation trench, wherein the isolation material covers the isolation trench and the top of the hard mask layer;
and removing the isolation material higher than the top of the hard mask layer by adopting a planarization process, and taking the isolation material in the isolation groove as the isolation structure.
19. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of initial floating gate structures located on the semiconductor substrate;
a target recess between adjacent initial floating gate structures and an isolation material filled at the bottom of the target recess, wherein sidewalls of the initial floating gate structures on both sides of the target recess are completely exposed, the isolation material extending into the semiconductor substrate.
20. The semiconductor structure of claim 19, wherein a gate oxide layer is further disposed between said initial floating gate structure and said semiconductor substrate.
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