CN113078169B - Display substrate, manufacturing method thereof and display device - Google Patents
Display substrate, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN113078169B CN113078169B CN202110322239.0A CN202110322239A CN113078169B CN 113078169 B CN113078169 B CN 113078169B CN 202110322239 A CN202110322239 A CN 202110322239A CN 113078169 B CN113078169 B CN 113078169B
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- via hole
- barrier layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 193
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 64
- 230000008569 process Effects 0.000 claims abstract description 52
- 238000005452 bending Methods 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 300
- 238000005530 etching Methods 0.000 claims description 42
- 238000000059 patterning Methods 0.000 claims description 32
- 239000011229 interlayer Substances 0.000 claims description 28
- 239000007789 gas Substances 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000011521 glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the application provides a display substrate, a manufacturing method thereof and a display device. The display substrate includes: a substrate; a barrier layer on one side of the substrate; orthographic projection is positioned on the substrate to form a first via hole in the bending region, and the first via hole penetrates through the barrier layer and part of the substrate to expose the substrate; the orthographic projection on the substrate is located at a second via of the bonding region, the second via penetrating through a portion of the barrier layer to expose the barrier layer. In the manufacturing process of the display substrate provided by the embodiment of the application, when the laser stripping process is carried out, the exposed barrier layer at the binding area position can block the gas oozed out of the substrate, so that the bonding bubbles are improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display substrate, a manufacturing method thereof and a display device.
Background
The full-screen display screen is widely applied due to the fact that the full-screen display screen has a higher screen occupation ratio and a narrower frame.
However, the inventor of the present application found that the present display panel with a full screen has bonding bubbles at the module stage, thereby affecting the display quality of the display panel.
Disclosure of Invention
The application provides a display substrate, a manufacturing method thereof and a display device aiming at the defects of the prior art, and aims to solve the technical problem that the display panel in the prior art has attaching bubbles in the module stage.
The embodiment of the application provides a display substrate, which comprises a bending area and a binding area, and further comprises:
a substrate;
a barrier layer located on one side of the substrate;
The orthographic projection of the first via hole on the substrate is positioned in the bending region, and the first via hole penetrates through the barrier layer and part of the substrate so as to expose the substrate;
and the orthographic projection of the second via hole on the substrate is positioned in the binding region, and the second via hole penetrates through part of the barrier layer so as to expose the barrier layer.
Optionally, the substrate is a flexible substrate, and in the binding region, the substrate comprises a barrier layer, a buffer layer, an active layer, a gate insulating layer and an interlayer insulating layer which are sequentially stacked on the substrate;
The second via hole penetrates through the interlayer insulating layer, the gate insulating layer, the active layer, the buffer layer and part of the barrier layer in sequence.
Optionally, the substrate is a flexible substrate, and the bending region comprises a blocking layer, a buffer layer, a gate insulating layer and an interlayer insulating layer which are sequentially stacked on the substrate;
the first via hole sequentially penetrates through the interlayer insulating layer, the gate insulating layer, the blocking layer, the buffer layer and part of the substrate.
The embodiment of the application provides a display device, which comprises a display substrate schematically shown in the previous embodiment.
The embodiment of the application provides a manufacturing method of a display substrate, which comprises the following steps:
Providing a substrate;
sequentially manufacturing a blocking layer and an active layer on one side of the substrate through a patterning process, wherein the active layer comprises a first active layer and a second active layer, the orthographic projection of the first active layer on the substrate is positioned in a display area, and the orthographic projection of the second active layer on the substrate is positioned in a binding area;
Forming a first via hole and a second via hole through a patterning process, wherein orthographic projection of the first via hole on the substrate is positioned in a bending region and penetrates through the barrier layer and part of the substrate to expose the substrate; the orthographic projection of the second via hole on the substrate is positioned in the binding region and penetrates through part of the barrier layer to expose the barrier layer.
Optionally, the forming the first via hole and the second via hole through a patterning process includes:
Forming a third via hole positioned in the display area, a fourth via hole positioned in the bending area and a fifth via hole positioned in the binding area through a first patterning process, wherein the third via hole exposes the first active layer, and the fifth via hole exposes the second active layer;
Forming a sixth via hole located in the bending region and a seventh via hole located in the binding region through a second patterning process, wherein the sixth via hole penetrates through the barrier layer and part of the substrate, and the seventh via hole penetrates through part of the barrier layer; wherein:
the fourth via and the sixth via constitute the first via, and the fifth via and the seventh via constitute the second via.
Optionally, the forming, through a second patterning process, a sixth via in the bending region and a seventh via in the bonding region includes:
Forming an eighth via hole in the bending region and forming a protective layer covering the exposed second active layer through first etching;
forming a ninth via hole positioned in the bending region and a seventh via hole positioned in the binding region through second etching, wherein the ninth via hole at least penetrates part of the substrate; wherein:
The eighth via and the ninth via constitute the sixth via.
Optionally, after the first etching and before the second etching, the method includes:
And removing the protective layer.
Optionally, the first etching includes: dry etching is carried out by adopting gas comprising carbon tetrafluoride, trifluoromethane and argon;
And/or, the second etching comprises: dry etching is performed using a gas including carbon tetrafluoride and oxygen.
Optionally, after the barrier layer and the active layer are sequentially fabricated on one side of the substrate through a patterning process, and before the first via hole and the second via hole are formed through the patterning process, the method includes:
Sequentially manufacturing a gate insulating layer and an interlayer insulating layer on one side of the active layer, which is far away from the substrate;
the first via hole also penetrates through the gate insulating layer and the interlayer insulating layer;
The second via hole also penetrates through the gate insulating layer and the interlayer insulating layer.
The technical scheme provided by the embodiment of the application at least has the following beneficial effects:
The display substrate provided by the embodiment of the application comprises: the substrate, the barrier layer, the first via hole and the second via hole; the orthographic projection of the first via hole on the substrate is positioned in the bending region and penetrates through the barrier layer and part of the substrate to expose the substrate, so that the display substrate in the embodiment of the application can be well bent in the module stage; compared with the prior art, when the display substrate in the embodiment of the application is subjected to the laser stripping process subsequently, the exposed barrier layer at the position of the binding region can block the gas oozed out of the substrate, so that the attaching bubbles are improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another display substrate according to an embodiment of the present application;
FIG. 3 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present application;
Fig. 4 to fig. 7 are schematic views of a display substrate structure at different manufacturing stages in the manufacturing process of the display substrate according to the embodiment of the application.
Reference numerals illustrate:
11-a display area; 12-bending region; 13-binding area; 14-a substrate; 15-a barrier layer; 16-a first via; 17-a second via; 18-a rigid substrate; 19-a buffer layer; 21-a gate insulation layer; 22-an interlayer insulating layer; a 23-gate;
141-a first substrate; 142-a second substrate; 151-a first barrier layer; 152-a second barrier layer; 201-a first active layer; 202-a second active layer; 211-a first gate insulation layer; 212-a second gate insulation layer; 231-a first gate; 232-a second gate;
31-a third via; 32-fourth vias; 33-fifth vias; 34-eighth via; 35-protective layer.
Detailed Description
The present application is described in detail below, examples of embodiments of the application are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Further, "connected" as used herein may include wireless connections. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
When the display substrate is manufactured in the prior art, firstly, a flexible layer is manufactured on a glass substrate, the flexible layer can be Polyimide Film (PI), and then Film layers such as a blocking layer, an active layer, a first gate insulating layer, a first gate, a second gate insulating layer, a second gate, an interlayer insulating layer, a source drain layer, a passivation layer and the like are sequentially manufactured on the flexible layer. The display substrate manufactured and formed in the prior art comprises a display area (AA area), a bending area (Bending area) and a binding area (Pad area), and after the bending area bends towards one side deviating from the light-emitting surface in a module stage, the binding area is attached to a flexible circuit board (Flexible Printed Circuit, FPC).
However, the inventor of the present application found that the flexible layer is exposed at the positions of the bending region and the binding region of the display substrate manufactured by the prior art (i.e., during the manufacturing process of the display substrate, the film layer at the positions of the bending region and the binding region is etched to the flexible layer by using an etching process); thus, when the rigid glass substrate and the flexible layer are separated by the subsequent laser peeling process, the flexible layer can possibly leak out of gas due to high-energy sweeping of laser, and then a small amount of gas released by the flexible layer in the binding area can eject bubbles out of the FPC when the FPC is attached to the module stage, so that the problem of attaching the bubbles occurs.
In order to solve the above-mentioned drawbacks of the prior art, the present application provides a display substrate and a manufacturing method thereof, and a detailed description is given below of the technical scheme of the present application and how the technical scheme of the present application solves the above-mentioned technical problems with specific embodiments.
As shown in fig. 1, the embodiment of the present application provides a display substrate, which includes a display area 11, a bending area 12 and a binding area 13, where the setting positions of the display area 11, the bending area 12 and the binding area 13 are set according to the actual requirements of products, and the specific setting is similar to that of the prior art, and will not be repeated here.
Specifically, as shown in fig. 1, the display substrate provided in the embodiment of the present application further includes: a substrate 14, a barrier layer 15, a first via 16 and a second via 17; the barrier layer 15 is positioned on one side of the substrate 14; the orthographic projection of the first via 16 on the substrate 14 is located in the bending region 12, and the first via 16 penetrates through the barrier layer 15 and part of the substrate 14 to expose the substrate 14; an orthographic projection of the second via 17 on the substrate 14 is located at the bonding region 13, and the second via 17 penetrates a portion of the barrier layer 15 to expose the barrier layer 15.
It should be noted that, the substrate 14 in the embodiment of the present application is a flexible substrate, for example, the substrate 14 may be a Polyimide Film (PI), the substrate 14 in the embodiment of the present application is first fabricated on the rigid substrate 18, for example, on a glass substrate, then a Film layer such as the barrier layer 15 is fabricated on the substrate 14, finally, a laser lift-off process is performed to separate the rigid substrate 18 from the substrate 14, the laser lift-off process may cause the substrate 14 to bleed out gas, and the display substrate shown in fig. 1 is a display substrate before the laser lift-off process is performed.
The display substrate provided by the embodiment of the application comprises: a substrate 14, a barrier layer 15, a first via 16 and a second via 17; the orthographic projection of the first via hole 16 on the substrate 14 is located in the bending region 12 and penetrates through the barrier layer 15 and part of the substrate 14 to expose the substrate 14, so that the display substrate in the embodiment of the application can well realize bending in the module stage; the orthographic projection of the second via hole 17 on the substrate 14 is located in the binding region 13 and penetrates through a part of the barrier layer 15 to expose the barrier layer 15, and compared with the prior art, when the display substrate in the embodiment of the application is subjected to the laser lift-off process subsequently, the exposed barrier layer 15 at the position of the binding region 13 can block the gas oozing from the substrate 14, so that the bonding bubbles are improved.
Specifically, as shown in fig. 1, in the embodiment of the present application, the thickness h of the barrier layer 15 is 2000 angstroms at the position corresponding to the second via hole 17 along the direction perpendicular to the substrate 14To 5000 angstromsThe barrier layer 15 in this thickness range can provide a good barrier to the gas exuded from the substrate 14, and thus the adhesion of bubbles is improved.
In one embodiment, as shown in fig. 2, in the bonding region 13, the display substrate in the embodiment of the present application includes a barrier layer 15, a buffer layer 19, an active layer (second active layer 202), a gate insulating layer 21, and an interlayer insulating layer 22 sequentially stacked on a base 14; the second via hole 17 penetrates the interlayer insulating layer 22, the gate insulating layer 21, the active layer, the buffer layer 19, and a part of the barrier layer 15 in this order (as penetrating a part of the second barrier layer 152 in the figure); of course, the bonding region 13 may also include other layers, such as a passivation layer (not shown) on the side of the interlayer insulating layer 22 away from the substrate 14, where the second via 17 sequentially penetrates the passivation layer, the interlayer insulating layer 22, the gate insulating layer 21, the active layer, the buffer layer 19, and a portion of the barrier layer 15.
In particular, as shown in fig. 2, the substrate 14 in the embodiment of the present application includes a first substrate 141 and a second substrate 142, the materials of the first substrate 141 and the second substrate 142 are the same, the barrier layer 15 includes a first barrier layer 151 and a second barrier layer 152, the materials of the first barrier layer 151 and the second barrier layer 152 are the same, the gate insulating layer 21 includes a first gate insulating layer 211 and a second gate insulating layer 212, and the materials of the first gate insulating layer 211 and the second gate insulating layer 212 are the same; the arrangement mode of the two layers of substrates (the first substrate 141 and the second substrate 142) and the arrangement mode of the two layers of barrier layers (the first barrier layer 151 and the second barrier layer 152) can well improve the characteristics of water resistance, reliability and the like of the screen; of course, in practical design, the display substrate in the embodiment of the present application may be designed with only one substrate (for example, only the second substrate 142 is provided) and only one barrier layer (for example, only the second barrier layer 152 is provided), and the display substrate may be provided with no buffer layer 19, and the thickness of the second barrier layer 152 may be set to be thicker.
In one embodiment, as shown in fig. 2, in the bending region 12, the display substrate in the embodiment of the present application includes a barrier layer 15, a buffer layer 19, a gate insulating layer 21, and an interlayer insulating layer 22 sequentially stacked on a base 14; the first via 16 penetrates the interlayer insulating layer 22, the gate insulating layer 21, the buffer layer 19, the barrier layer 15 (penetrating the second barrier layer 152 in the figure), and a portion of the substrate 14 (penetrating a portion of the second substrate 142 in the figure) in this order. Of course, the bending region 12 may also include other layers, such as a passivation layer (not shown) located on a side of the interlayer insulating layer 22 away from the substrate 14, where the first via 16 sequentially penetrates the passivation layer, the interlayer insulating layer 22, the gate insulating layer 21, the buffer layer 19, the barrier layer 15, and a portion of the substrate 14.
In a specific embodiment, as shown in fig. 2, in the display area 11, the display substrate in the embodiment of the present application includes a barrier layer 15 (a first barrier layer 151 and a second barrier layer 152), a buffer layer 19, an active layer (a first active layer 201), a gate insulating layer 21 (a first gate insulating layer 211 and a second gate insulating layer 212), a gate electrode 23 (a first gate electrode 231 and a second gate electrode 232) and an interlayer insulating layer 22, which are sequentially stacked on a substrate 14, and the specific arrangement of these layers is similar to that of the prior art, and will not be repeated here.
Based on the same inventive concept, the embodiments of the present application also provide a display device including the display substrate illustrated in the foregoing embodiments. Since the display device includes the display substrate provided in the foregoing embodiment of the present application, the display device provided in the embodiment of the present application has the same advantages as the display substrate, and will not be described herein.
Specifically, the display device in the embodiment of the application can be a display device such as a mobile phone, a notebook computer and the like.
Based on the same inventive concept, the embodiment of the application also provides a manufacturing method of the display substrate, as shown in fig. 3, the method includes:
s101, providing a substrate;
S102, sequentially manufacturing a barrier layer and an active layer on one side of a substrate through a composition process, wherein the active layer comprises a first active layer and a second active layer, the orthographic projection of the first active layer on the substrate is positioned in a display area, and the orthographic projection of the second active layer on the substrate is positioned in a binding area;
S103, forming a first via hole and a second via hole through a patterning process, wherein orthographic projection of the first via hole on the substrate is positioned in the bending region and penetrates through the barrier layer and part of the substrate to expose the substrate; the orthographic projection of the second via hole on the substrate is positioned in the binding region and penetrates through part of the barrier layer to expose the barrier layer.
Specifically, the substrate in S101 may include a single flexible layer or two flexible layers, and when two flexible layers are included, as shown in fig. 4, the substrate provided in S101 includes a first substrate 141, a first barrier layer 151, and a second substrate 142 sequentially formed on a rigid substrate 18, where the first substrate 141 and the second substrate 142 are flexible substrates, for example, the first substrate 141 and the second substrate 142 may each be a Polyimide Film (PI).
Specifically, as shown in fig. 4, in S102, a barrier layer and an active layer are sequentially fabricated on a substrate side through a patterning process, which specifically includes: the second barrier layer 152, the buffer layer 19, the first active layer 201 and the second active layer 202 are sequentially fabricated on the side of the second base 142 far away from the rigid substrate 18 through a patterning process, however, in the actual fabrication process, the buffer layer 19 may not be fabricated in this step, the first active layer 201 and the second active layer 202 may be directly fabricated on the second barrier layer 152, and the display substrate fabricated with the buffer layer 19 may further improve the characteristics of waterproof performance, reliability and the like of the screen.
In particular, the patterning process in the embodiment of the present application includes the processes of coating, exposing, developing, etching the photoresist, and removing part or all of the photoresist. In the process of manufacturing the active layer, the embodiment of the application is manufactured by adopting a new active layer mask plate different from the prior art, and the new active layer mask plate is adopted to form the first active layer 201 positioned in the display area 11 and the second active layer 202 positioned in the binding area 13, and the first active layer 201 and the second active layer 202 are manufactured and formed in the same composition process.
Specifically, as shown in fig. 5, after the barrier layer and the active layer are sequentially fabricated on one side of the substrate through the patterning process in S102, and before the first via hole and the second via hole are formed through the patterning process in S103, the method includes: the gate insulating layer 21 and the interlayer insulating layer 22 are sequentially formed on the sides of the active layers (the first active layer 201 and the second active layer 202) away from the substrate (the first substrate 141 or the second substrate 142). In implementation, the first gate insulating layer 211, the first gate 231, the second gate insulating layer 212, the second gate 232, and the interlayer insulating layer 22 are sequentially formed on the first active layer 201 and the second active layer 202, and the specific manufacturing methods of these film layers are similar to those of the prior art, and are not repeated here. Of course, in actual manufacturing, a passivation layer (not shown) may be formed on the interlayer insulating layer 22, and the specific manufacturing method of the passivation layer is similar to that of the prior art.
Specifically, as shown in fig. 2 and 6, forming the first via hole 16 and the second via hole 17 through the patterning process in S103 includes: forming a third via hole 31 located in the display region 11, a fourth via hole 32 located in the bending region 12 and a fifth via hole 33 located in the bonding region 13 through a first patterning process, wherein the third via hole 31 exposes the first active layer 201, the fourth via hole 32 exposes the buffer layer 19 (if no buffer layer is provided, the fourth via hole 32 exposes the second barrier layer 152 at this time), and the fifth via hole 33 exposes the second active layer 202; forming a sixth via (not shown) located in the bending region 12 and a seventh via (not shown) located in the bonding region 13 through the buffer layer 19, the barrier layer (the second barrier layer 152 in fig. 2) and a part of the substrate (the second substrate 142 in fig. 2) by a second patterning process, the seventh via penetrating the second active layer 202, the buffer layer 19 and a part of the barrier layer (the second barrier layer 152 in fig. 2); wherein: the fourth via 32 and the sixth via constitute the first via 16, and the fifth via 33 and the seventh via constitute the second via 17.
In specific implementation, the first patterning process and the second patterning process in the embodiment of the application are performed by using different masks, and each patterning process comprises the steps of coating, exposing, developing and etching photoresist and removing part or all of the photoresist.
As shown in fig. 6, in the first patterning process in the embodiment of the present application, a first mask is used for exposing, developing and removing photoresist at positions where the third via hole 31, the fourth via hole 32 and the fifth via hole 33 need to be formed, and then etching is performed, and etching is performed at the position of the display area 11 until the first active layer 201 is etched, so as to form the third via hole 31, so as to expose the first active layer 201; etching the bending region 12 to the buffer layer 19 to form a fourth via 32 to expose the buffer layer 19; the second active layer 202 is etched at the location of the bonding region 13, and a fifth via 33 is formed to expose the second active layer 202.
Further, as shown in fig. 2 and 7, the forming of the sixth via hole located in the bending region 12 and the seventh via hole located in the bonding region by the second patterning process according to the embodiment of the present application includes: forming an eighth via hole 34 located in the bending region 12 and forming a protection layer 35 covering the exposed second active layer 202 by first etching, wherein the eighth via hole 34 penetrates part of the buffer layer 19 (if no buffer layer is provided, the eighth via hole 34 penetrates part of the second barrier layer 152); forming a ninth via (not shown) located in the bending region 12 and a seventh via (not shown) located in the binding region by a second etching, where the ninth via penetrates at least a portion of the substrate (as shown in fig. 2 and 7, the ninth via penetrates a portion of the buffer layer 19, the second barrier layer 152, and a portion of the second substrate 142 in the embodiment of the present application); wherein: the eighth via hole and the ninth via hole constitute a sixth via hole.
Specifically, as shown in fig. 2, the second patterning process in the embodiment of the present application uses a second mask plate to expose, develop and remove the photoresist at the positions where the first via hole 16 and the second via hole 17 need to be formed, and then perform the first etching and the second etching.
In a specific embodiment, as shown in fig. 7, in the first etching, a gas including carbon tetrafluoride (CF 4), trifluoromethane (CHF 3) and argon (Ar) is used to perform dry etching, in which a dense protective layer 35 is formed on the second active layer 202, the protective layer 35 is formed by reacting an etching gas with the second active layer 202, the protective layer 35 is specifically a substance of carbon (C), the protective layer 35 is formed at the position of the bonding region 13, the etching rate of the bonding region 13 is almost zero in the first etching, and the bending region 12 can be normally etched to form the eighth via 34, the etching rate is aboutThe buffer layer 19 forms a step difference at the location of the inflection region 12 and at the location of the binding region 13 at this time.
In a specific embodiment, as shown in fig. 2, at the time of the second etching, dry etching is performed using a gas including carbon tetrafluoride (CF 4) and oxygen (O2). In a specific implementation, before the second etching, the embodiment of the present application further includes removing the protection layer 35 formed at the position of the binding region 13 in the first etching process, and since the protection layer 35 is removed, in the second etching process, the binding region 13 and the bending region 12 can be etched normally, and since the buffer layer 19 forms a step difference between the position of the bending region 12 and the position of the binding region 13 in the first etching process, after the second etching, when part of the second substrate 142 is etched at the position of the bending region 12, due to the existence of the step difference, the position of the binding region 13 is not etched to the second substrate 142, but only part of the second barrier layer 152 is etched, and the retained second barrier layer 152 can well block the gas oozed out from the second substrate 142, so that the bonding bubble is improved.
Specifically, in the first etching in the embodiment of the present application, the specific etching depth at the position of the bending region 12 is determined according to the specific thicknesses of the second active layer 202, the buffer layer 19 and the second barrier layer 152, so as to ensure that the first via 16 formed after the second etching can penetrate part of the second substrate 142, and the second via 17 formed can only penetrate part of the second barrier layer 152, specifically, the thickness of the remaining second barrier layer 152 along the direction perpendicular to the second substrate 142 is about
In summary, by applying the embodiment of the application, at least the following beneficial effects can be achieved:
the display substrate provided by the first embodiment of the application comprises: a substrate 14, a barrier layer 15, a first via 16 and a second via 17; the orthographic projection of the first via hole 16 on the substrate 14 is located in the bending region 12 and penetrates through the barrier layer 15 and part of the substrate 14 to expose the substrate 14, so that the display substrate in the embodiment of the application can well realize bending in the module stage; the orthographic projection of the second via hole 17 on the substrate 14 is located in the binding region 13 and penetrates through a part of the barrier layer 15 to expose the barrier layer 15, and compared with the prior art, when the display substrate in the embodiment of the application is subjected to the laser lift-off process subsequently, the exposed barrier layer 15 at the position of the binding region 13 can block the gas oozing from the substrate 14, so that the bonding bubbles are improved.
The second patterning process in the second embodiment of the present application includes a first etching process and a second etching process, where in the first etching process, a dense protection layer 35 is generated on the second active layer 202, so that the etching rate of the bonding region 13 is almost zero, and the bending region 12 can perform normal etching, so that a step difference is formed between the position of the bending region 12 and the position of the bonding region 13 in the buffer layer 19, the position of the bending region 12 is etched to the second substrate 142 after the second etching, the position of the bonding region 13 is etched to the second barrier layer 152, and the second barrier layer 152 reserved at the position of the bonding region 13 can perform good barrier to the gas oozed out from the second substrate 142, so that the bonding bubble is improved.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.
Claims (10)
1. A display substrate comprising a bending region and a binding region, wherein the display substrate further comprises:
a substrate;
a barrier layer located on one side of the substrate;
The orthographic projection of the first via hole on the substrate is positioned in the bending region, and the first via hole penetrates through the barrier layer and part of the substrate so as to expose the substrate;
and the orthographic projection of the second via hole on the substrate is positioned in the binding region, and the second via hole penetrates through part of the barrier layer so as to expose the barrier layer.
2. The display substrate according to claim 1, wherein the base is a flexible base, and the bonding region includes a barrier layer, a buffer layer, an active layer, a gate insulating layer, and an interlayer insulating layer sequentially stacked on the base;
The second via hole penetrates through the interlayer insulating layer, the gate insulating layer, the active layer, the buffer layer and part of the barrier layer in sequence.
3. The display substrate according to claim 1, wherein the base is a flexible base, and the bending region includes a barrier layer, a buffer layer, a gate insulating layer, and an interlayer insulating layer sequentially stacked on the base;
the first via hole sequentially penetrates through the interlayer insulating layer, the gate insulating layer, the blocking layer, the buffer layer and part of the substrate.
4. A display device comprising the display substrate according to any one of claims 1 to 3.
5.A method for manufacturing a display substrate, comprising:
Providing a substrate;
sequentially manufacturing a blocking layer and an active layer on one side of the substrate through a patterning process, wherein the active layer comprises a first active layer and a second active layer, the orthographic projection of the first active layer on the substrate is positioned in a display area, and the orthographic projection of the second active layer on the substrate is positioned in a binding area;
Forming a first via hole and a second via hole through a patterning process, wherein orthographic projection of the first via hole on the substrate is positioned in a bending region and penetrates through the barrier layer and part of the substrate to expose the substrate; the orthographic projection of the second via hole on the substrate is positioned in the binding region and penetrates through part of the barrier layer to expose the barrier layer.
6. The method of claim 5, wherein forming the first via and the second via by a patterning process comprises:
Forming a third via hole positioned in the display area, a fourth via hole positioned in the bending area and a fifth via hole positioned in the binding area through a first patterning process, wherein the third via hole exposes the first active layer, and the fifth via hole exposes the second active layer;
Forming a sixth via hole located in the bending region and a seventh via hole located in the binding region through a second patterning process, wherein the sixth via hole penetrates through the barrier layer and part of the substrate, and the seventh via hole penetrates through part of the barrier layer; wherein:
the fourth via and the sixth via constitute the first via, and the fifth via and the seventh via constitute the second via.
7. The method of claim 6, wherein forming a sixth via in the inflection region and a seventh via in the bonding region by the second patterning process comprises:
Forming an eighth via hole in the bending region and forming a protective layer covering the exposed second active layer through first etching;
forming a ninth via hole positioned in the bending region and a seventh via hole positioned in the binding region through second etching, wherein the ninth via hole at least penetrates part of the substrate; wherein:
The eighth via and the ninth via constitute the sixth via.
8. The method of claim 7, wherein after the first etching and before the second etching, comprising:
And removing the protective layer.
9. The method of claim 7, wherein the first etching comprises: dry etching is carried out by adopting gas comprising carbon tetrafluoride, trifluoromethane and argon;
And/or, the second etching comprises: dry etching is performed using a gas including carbon tetrafluoride and oxygen.
10. The method according to any one of claims 5 to 9, wherein after sequentially forming the barrier layer and the active layer on the substrate side by a patterning process, and before forming the first via hole and the second via hole by a patterning process, the method comprises:
Sequentially manufacturing a gate insulating layer and an interlayer insulating layer on one side of the active layer, which is far away from the substrate;
the first via hole also penetrates through the gate insulating layer and the interlayer insulating layer;
The second via hole also penetrates through the gate insulating layer and the interlayer insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110322239.0A CN113078169B (en) | 2021-03-25 | 2021-03-25 | Display substrate, manufacturing method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110322239.0A CN113078169B (en) | 2021-03-25 | 2021-03-25 | Display substrate, manufacturing method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113078169A CN113078169A (en) | 2021-07-06 |
| CN113078169B true CN113078169B (en) | 2024-09-03 |
Family
ID=76610353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110322239.0A Active CN113078169B (en) | 2021-03-25 | 2021-03-25 | Display substrate, manufacturing method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113078169B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735785A (en) * | 2018-05-21 | 2018-11-02 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and its manufacturing method |
| CN110611039A (en) * | 2019-08-20 | 2019-12-24 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of flexible OLED display device and flexible OLED display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102280959B1 (en) * | 2013-12-16 | 2021-07-26 | 삼성디스플레이 주식회사 | Display device and method for manufacturing the same |
| CN206003771U (en) * | 2016-07-28 | 2017-03-08 | 上海天马微电子有限公司 | Flexible display device |
-
2021
- 2021-03-25 CN CN202110322239.0A patent/CN113078169B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108735785A (en) * | 2018-05-21 | 2018-11-02 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and its manufacturing method |
| CN110611039A (en) * | 2019-08-20 | 2019-12-24 | 武汉华星光电半导体显示技术有限公司 | Manufacturing method of flexible OLED display device and flexible OLED display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113078169A (en) | 2021-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7476812B2 (en) | Printed circuit board and manufacturing method thereof | |
| CN108227281B (en) | Stretchable display device and preparation method thereof | |
| TWI326196B (en) | Capacitor-embedded pcb having blind via hole and method of manufacturing the same | |
| KR20060037698A (en) | Method for manufacturing rigid-flexible printed circuit board | |
| JP7113757B2 (en) | DISPLAY SUBSTRATE, DISPLAY SUBSTRATE MANUFACTURING METHOD, AND DISPLAY DEVICE | |
| US12041829B2 (en) | Chip-on-film structure, display apparatus and method for manufacturing same | |
| TW200829104A (en) | Circuit board and method for manufaturing thereof | |
| CN108288437B (en) | Connector, manufacturing method thereof and display screen | |
| US20200305286A1 (en) | Method for Contacting and Rewiring an Electronic Component Embedded into a Printed Circuit Board | |
| TWI571912B (en) | Method for making narrow electric wires on the peripheral region of touch screen, the touch screen containing the said wires, and display screen apparatus | |
| CN108417730B (en) | Flexible substrate, preparation method thereof and display device | |
| CN113078169B (en) | Display substrate, manufacturing method thereof and display device | |
| CN107369777B (en) | OLED substrate, preparation method thereof and display device | |
| CN109213372B (en) | Touch panel, preparation method thereof and touch device | |
| CN109148271B (en) | Preparation method of display substrate, display substrate and display screen | |
| CN111295056A (en) | Manufacturing method of flexible plate of step circuit | |
| CN116528496A (en) | Manufacturing method of high-thickness copper circuit board solder mask | |
| WO2022062170A1 (en) | Method for forming solder mask layer on circuit board, circuit board manufacturing method, and circuit board | |
| JP3155743B2 (en) | Wiring board, method of manufacturing the same, and multilayer wiring board | |
| US6274291B1 (en) | Method of reducing defects in I/C card and resulting card | |
| JP3010869B2 (en) | Manufacturing method of printed wiring board | |
| JP3010822B2 (en) | Manufacturing method of printed wiring board | |
| JPH0766551A (en) | Manufacture of thin film multilayer interconnection board | |
| JPH06310838A (en) | Manufacture of printed-wiring board | |
| CN117476555A (en) | Display panel, manufacturing method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |