CN112968691B

CN112968691B - Pulse time delay precision self-adaptive synchronization method

Info

Publication number: CN112968691B
Application number: CN202110183712.1A
Authority: CN
Inventors: 曾富华; 张帆; 莫明威; 蒋友邦
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2021-02-10
Filing date: 2021-02-10
Publication date: 2023-04-11
Anticipated expiration: 2041-02-10
Also published as: CN112968691A

Abstract

The invention provides a pulse delay precision self-adaptive synchronization method, and aims to provide a self-adaptive synchronization delay method with high synchronization precision, good reliability and low error rate. The invention is realized by the following scheme: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and the sampling signals P1 pass through a register to be sampled to obtain pulse signals P2; meanwhile, a clock CLK of an external digital circuit system is used for driving a timing pulse generator to generate a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, a time delay comparator calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, a delay judgment strategy model is used for carrying out combined calculation according to a plurality of search periods to obtain the time delay control quantity N0 of the digital difference value N, so that a time delay correction quantity M is obtained, and an internal pulse signal which is stably synchronous with the external pulse signal is obtained.

Description

Pulse time delay precision self-adaptive synchronization method

Technical Field

The invention relates to a synchronous FPGA pulse time delay method in the technical field of array digital signal processing.

Background

The array signal processing is an important branch of the signal processing field, with the development of the technology, the array signal processing is developed towards the direction of full digitalization, and the advanced Digital Beam Forming (DBF) technology is adopted to realize the shaping of a transmitting beam so as to reduce the probability of the interception of the transmitting signal. And digital sampling is directly adopted in the channel array elements or digital sampling is carried out after analog synthesis among local array elements, next step of synthesis processing is carried out, and the diversity of array application functions can be realized by utilizing the stability and flexibility of a digital system. In large-scale array signal processing, digital processing circuits are distributed in various modules at different positions, synchronous sampling is required among the modules, namely the digital processing circuits are distributed in different modules and are processed by using the same time reference. The digital system generally adopts a mode of distributing periodic synchronous pulses to each digital processing module, so that synchronous processing among the modules firstly needs to accurately identify the processing clock period corresponding to the synchronous pulses according to the processing clock, but due to engineering reasons, the time delay of the pulse signals distributed to each digital processing module is slightly different, and when the processing clock of the digital module is higher, the rising edge of the pulse signals is approximate to the edge of the digital clock, so that the metastable state is caused. Metastability can cause inconsistent identification of the rising edge of the pulse signal between digital blocks, which can result in synchronization failure between blocks, i.e., different digital blocks sample the transition of the pulse signal at different rising edges of CLK.

In a distributed digital synchronous processing system, the delay performance of synchronous pulse transmission for synchronization among digital circuits is an important index in the system, and the performance of the system is directly influenced by the performance of delay difference, delay jitter and the like. The phased array system requires phase coherent to be realized in each array element, thereby effectively forming the antenna directivity. Modern array processing signal bandwidth is wider and wider, clocks of digital processing circuits are higher and higher, and requirements on synchronous distribution precision of synchronous pulse signals are higher and higher.

Synchronization of all modules of each subarray of the distributed phased array is achieved through a common clock signal. For the distributed phased array, it is very complicated to implement signal coherent and synchronization between the receiving and transmitting units at far distance, which requires a high-precision synchronous clock source. The distributed control system clock is realized by using counters, and whether 2 standards exist in synchronization of the 2 clocks is judged, wherein the standards include whether the numerical values of the counters are equal, and whether the increasing speeds of the numerical values of the counters are equal. According to IEEE1588, to synchronize the slave clock to the master clock, the offset between the slave clock and the master clock is first determined, this offset is calculated from the offset between the transmission timestamp and the reception timestamp of the packet, and its accuracy is affected by 2 factors, namely the uncertainty of the delay time of the data transmission and the accuracy of the timestamp itself. Because the clock delay has only two choices, the precise matching of the phase can not be realized, and the requirement of some ultra-high speed circuits is difficult to adapt. The self-adaptive synchronizer can predict the phase relation between the sampling clock and the input data, self-adaptively select the steady-state sampling result and reduce the probability of the metastable state. Although the data delay synchronizer can realize accurate delay of data, the latch of ultra-high speed data or DDR data is realized. However, due to the use of a large number of delay units, the complexity of FPGA design is increased, and implementation is difficult. The FPGA can acquire data such as frequency, duty ratio, amplitude, rise time and the like of a pulse signal at a high speed, and a D trigger is generally adopted in the FPGA to realize sampling of input data. In order to avoid a metastable state, the D flip-flop requires that input data meet certain setup and hold times relative to a clock edge, that is, the input data and an internal clock of the FPGA meet a certain phase relationship. The rising edge of a pulse signal can be resolved only by taking the clock CLK period as stepping, so that the resolution of the clock CLK decimal cycle time delay is realized. Due to uncertainty of relative phases of input data and a sampling clock, the establishing and holding time of a D trigger in the FPGA can not be met, and a metastable state occurs. However, in the high-speed data acquisition system based on the FPGA, in which the internal clock and the external clock use the same clock source, due to the routing delay, the device delay, and the FPGA input pin delay, the relative phase relationship between the FPGA input data and the FPGA internal clock is uncertain, and the influence of the precision of the timestamp itself on the synchronization precision is obviously increased.

Disclosure of Invention

The invention aims to provide a self-adaptive synchronization method with high synchronization precision, good reliability, low error rate and high-precision pulse delay precision aiming at the synchronization requirements of distributed digital modules of the existing large conformal phased array system, so as to solve the problems of long delay and poor data consistency of the existing synchronization method and effectively improve the stability of the distributed system.

The above object of the present invention can be achieved by the following means. A pulse time delay precision self-adaptive synchronization method has the following technical characteristics: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and the sampling signals P1 pass through a register to be sampled to obtain pulse signals P2; meanwhile, the FPGA drives a timing pulse generator by utilizing an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained digital clock difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable time delayer to obtain a corresponding digital difference value N; the delay adjustment module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjustment delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through the pulse delay adjustment module, the other path is sent into the time comparator, time-sharing strategy delay judgment is carried out on the delay adjustment module by comparing and outputting a P2 delay difference value N and a P3 delay difference value N, a fine delay difference between a sampling signal P1 and a pulse signal P3 is calculated, a delay control quantity N0 of a digital difference value N is obtained by searching according to a plurality of search periods and is jointly calculated to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, the pulse delay adjustment circuit is controlled to adjust the pulse signal P3, and an internal pulse signal stably synchronized with an external pulse signal is obtained in a self-adaptive mode.

Compared with the prior art, the invention has the beneficial effects that:

the synchronization precision is high. The invention aims at the problem of metastable state sampling which can occur when an external periodic pulse signal is directly sampled by an external input clock CLK. An external periodic pulse signal P0 is input into the FPGA through a field programmable gate array FPGA pin, a sampling signal P1 is output through an adjustable time delay unit and is sent into a register, an internal pulse signal P2 is obtained according to a clock CLK input from the outside of a digital circuit system and is sent into a time comparator, a timing pulse generator is driven by the clock CLK input from the outside of the digital circuit system inside the FPGA, a pulse signal P3 with the same frequency as the external periodic pulse signal is generated and is divided into two paths, stable and reliable synchronization is realized by using a periodic pulse reference signal, the resolution of the clock CLK fractional period time delay is realized, the resolution precision of the FPGA circuit on the rising edge of the pulse signal is obviously improved, and the defect that the rising edge of the pulse signal can only be resolved by using the clock CLK period as stepping is overcome.

The reliability is good. The method comprises the steps of sending a time comparator to compare and output N digital difference values N to a time delay judgment strategy module for time delay judgment, calculating the digital difference value N of the rising edges of a pulse signal P2 and a pulse signal P3, feeding back the obtained time delay value DT to an adjustable time delay unit, sequentially changing the time delay value DT to obtain the corresponding digital difference value N, comparing the interval of the digital difference value N with the value change by the time comparator to obtain the time delay control range of the external periodic pulse signal stably sampled by a clock CLK and the value N0 of the digital difference value N corresponding to the range, and remarkably improving the phenomenon of digital module asynchronization caused by the metastable state which possibly occurs when the rising edge of the external periodic pulse signal is close to the rising edge of the clock CLK. The problem of providing stable pulse output when carrying out rising edge continuous search to external pulse is effectively solved. In the process of obtaining N0 through analyzing the interval of numerical change and stability of the N value, multiple detection combined judgment is adopted, continuous detection of the external periodic pulse signal can be realized under the condition of not influencing continuous generation of the internal pulse signal P4, and when the state of the external periodic pulse signal is detected to be changed, the state of the internal pulse signal P4 can be adjusted in time. When the external periodic pulse signal disappears, the internal pulse signal P4 can be continuously generated in each digital module, so that the synchronous state among the digital modules is kept. To resolve the possibility of false pulse acquisition due to glitches.

The error rate is low. The time delay judgment strategy module of the invention corrects according to the N0 value of the digital difference value N to obtain the time delay correction quantity M, and the pulse signal P3 is adjusted by the pulse time delay adjustment module to obtain the internal pulse signal which is stably synchronous with the external pulse signal, so the error rate is low, the fault tolerance of the distributed digital system to the pulse signal can be obviously improved, and the normal synchronization between the digital modules can still be normally maintained when the pulse signal has burrs or the pulse signal fails (fails after first effectiveness). The metastable state sampling problem which can occur when the external periodic pulse signal is directly sampled by the external input clock CLK is effectively solved.

The invention is suitable for the synchronization among the distributed digital circuit modules of the large-scale digital phased array system, and is also suitable for the field of other digital signal processing.

Drawings

FIG. 1 is a circuit schematic processing flow diagram of the adaptive synchronous FPGA pulse delay of the present invention.

Fig. 2 is a schematic diagram of the phase relationship of the delay count to the fine delay adjust input pulses P0 and CLK.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the present invention will be further described with reference to the accompanying drawings and embodiments. The technical scheme in the embodiment of the invention is clearly and completely described.

Detailed Description

See fig. 1. According to the invention, firstly, a clock CLK sampling signal P1 is obtained by periodically inputting a pulse P0 outside a digital circuit system through a built-in adjustable delayer of an FPGA, and a pulse signal P2 is obtained by sampling the sampling signal P1 through a register; meanwhile, the FPGA drives a timing pulse generator by utilizing an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained digital clock difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable time delayer to obtain a corresponding digital difference value N; the delay judgment strategy module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjusting delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through a pulse delay adjustment module, the other path is sent into a time comparator, time delay difference values N of P2 and P3 are compared and output to a delay judgment strategy module to carry out time-sharing strategy delay judgment, fine delay difference between a sampling signal P1 and a pulse signal P3 is calculated, delay control quantity N0 of a digital difference value N is obtained according to searching of a plurality of search periods and is jointly calculated to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, a pulse delay adjustment circuit is controlled to adjust the pulse signal P3, and an internal pulse signal which is stably synchronous with an external pulse signal is obtained.

The method comprises the steps that an external periodic input pulse P0 of a digital circuit system is input into an FPGA through a Field Programmable Gate Array (FPGA) pin, the P0 outputs a sampling signal P1 through an adjustable time delay device and is sent into a register, the register samples the signal, an internal pulse signal P2 is obtained according to an external input clock CLK of the digital circuit system and is sent into a time comparator, the internal part of the FPGA utilizes the external CLK of the digital circuit system to drive a timing pulse generator, a pulse signal P3 with the same frequency as the external periodic pulse signal is generated, a time delay judgment strategy module performs combined calculation according to N0 values searched in a plurality of search periods to obtain a time delay correction quantity M, the combined calculation process is that when a new N0 value is obtained, the N0 value at this time is compared with the N0 values searched for a plurality of times, the N0 value at this time is considered to be valid if the N0 value is the same, a constant is added or subtracted according to the N0 to obtain the M value, and if the N0 is different, the N0 is considered to be wrong data, and the M value is not calculated.

In an optional embodiment, the adaptive synchronous FPGA pulse delay may be divided into three parts, a first part processes an input, the adaptive synchronous FPGA pulse delay is divided into three parts, the first part processes the input, a second part generates a pulse P3 by locally counting a digital circuit system clock CLK, and a third part of the delay judgment strategy completes an interval search and delay screening judgment function.

In a first part for processing input, an external input pulse P0 of a digital circuit system passes through an adjustable delayer to obtain a sampling signal P1, and the sampling signal P1 is sampled by a clock CLK of the digital circuit system to obtain a pulse signal P2;

in the second part, the digital circuit system sends a clock CLK local counting generated pulse P3 to a time delay comparator, and calculates the CLK clock number of the pulse signal P2 and the pulse signal P3 to obtain the CLK rising edge time delay difference n;

in the third part, a time delay judgment strategy module time delay comparator block records a digital difference value N of a time delay difference N, controls a time delay value DT to adjust the delay amount of the adjustable delayer, searches for a period range larger than 1 CLK, adjusts a time delay unit to be smaller than a CLK clock period, completes interval search and time delay screening judgment by using a time delay judgment strategy, calculates a fine time delay difference between a sampling signal P1 and a pulse signal P3, and controls a pulse time delay adjustment circuit to adjust the pulse signal P3 to obtain an output pulse signal P4 signal of self-adaptive synchronous FPGA pulse time delay.

And the time delay judgment strategy module sets the time delay control quantity DT to the adjustable time delayer, and obtains a corresponding digital difference value N when the time delay value DT is set once.

And the time delay judgment strategy module controls the time delay control quantity DT to search within a certain range by stepping a period which is not more than the CLK, and the search period is more than the period of the CLK according to the capacity of the adjustable delayer. And obtaining a time delay control range of the external periodic pulse signal of the digital circuit system stably sampled by the clock CLK and a numerical value N0 of a digital difference value N corresponding to the range through searching in a search period.

The delay judgment strategy module takes less than 1/5 CLK period to more than 1 CLK period as a beneficial search range, controls the delay value DT to adjust the delay amount of the adjustable delayer, records the value N every time adjustment is carried out for 1 time, adjusts the delay unit to be less than the CLK clock period, accumulates the delay value DT on the unit of the adjustable delay unit one by one, and obtains the digital difference value N of the delay count of the delay value DT and the fine delay adjustment data shown in figure 2 after the search range is carried out for one time.

The delay judgment strategy module can search limited round numbers or continuous search as required, after the search range of the delay judgment strategy module is completed, the interval of numerical value change and stability of the N value is analyzed, the stable N value is selected to determine a delay correction M, the delay value DT is controlled again to perform a new round of search, the delay correction M is determined jointly according to the digital difference N of the multiple rounds of search, the external periodic pulse signal of the delay control range which can be stably sampled by the clock CLK and the N value N0 corresponding to the range are obtained, the pulse signal P3 is corrected by the N0 value, and the internal pulse signal which is stably synchronous with the external pulse signal is obtained.

As shown in fig. 2, the delay judgment policy module calculates a digital difference N between rising edges of the pulse signal P2 and the pulse signal P3 by changing the delay value DT of the controllable delay circuit once, and sequentially changes DT to obtain a corresponding N, calculates a digital difference N between rising edges of the pulse signal P2 and the pulse signal P3 by changing the delay value DT once, obtains a digital clock difference N between pulses P2 and P3 by sequentially changing the delay value DT, and records a corresponding delay value DT as a metastable delay value DT0 when the value N jumps from the digital difference N to N + 1. When the adjustable delayer is set to be the initial delay value DT0, and the register sampling signal P1 value has a metastable state with sampling uncertainty, the phase relation between the input pulse P0 and the CLK is different, and the initial delay value DT0 value is different.

The abnormal digital difference value N caused by the reasons of the burrs of the input clock signal and the like is removed, so that the influence of accidental burrs is avoided. When the external input pulse signal of the digital circuit system disappears, the external input pulse-free signal can be determined according to the jump characteristic that the digital difference value N cannot be searched to N + 1; when the external pulse signal disappears, the delay correction amount M can be maintained, so that the pulse signal P4 has a continuous output and is synchronized with the pulse before the external pulse signal disappears.

The embodiments described above are some, but not all embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Claims

1. A pulse time delay precision self-adaptive synchronization method has the following technical characteristics: the method comprises the steps that external periodic input pulses P0 of a digital circuit system pass through an FPGA built-in adjustable delayer to obtain clock CLK sampling signals P1, and the sampling signals P1 pass through a register to be sampled to obtain pulse signals P2; meanwhile, the FPGA drives a timing pulse generator by using an external digital circuit system clock CLK, generates a pulse signal P3 which is generated by local counting and has the same frequency with an external periodic pulse signal, sends the pulse signal P3 to a time comparator for comparison, calculates the time delay difference N of the rising edges of the pulse signal P2 and the pulse signal P3, sends the obtained time delay difference N to a time delay judgment strategy module for time delay correction, sets a time delay value DT by the time delay judgment strategy module, and feeds the set time delay value DT back to the adjustable delayer to obtain a corresponding digital difference value N; the delay judgment strategy module controls a delay value DT to adjust the delay amount of the adjustable delayer, an adjusting delay unit is smaller than the CLK clock period and is divided into two paths, one path passes through the pulse delay adjustment module, the other path is sent into the time comparator, the P2 and P3 digital difference value N is compared and output to the delay judgment strategy module to carry out time-sharing strategy delay judgment, the fine delay difference between the sampling signal P1 and the pulse signal P3 is calculated, delay control quantity N0 of the digital difference value N is obtained according to searching of a plurality of search periods and is jointly calculated to obtain a delay correction quantity M, interval searching and delay screening judgment are completed, the pulse delay adjustment circuit is controlled to adjust the pulse signal P3, and an internal pulse signal which is stably synchronous with an external pulse signal is obtained in a self-adaptive mode.

2. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the self-adaptive synchronous FPGA pulse time delay is divided into three parts, wherein the first part processes input, the second part generates a pulse P3 by locally counting a digital circuit system clock CLK, and the third part completes the functions of interval search and time delay screening judgment according to a time delay judgment strategy; in a first part for processing input, an external input pulse P0 of a digital circuit system passes through an adjustable delayer to obtain a sampling signal P1, and the sampling signal P1 is sampled by a clock CLK of the digital circuit system to obtain a pulse signal P2; in the second part, the digital circuit system sends a clock CLK local counting generated pulse P3 to a time comparator, and calculates the CLK clock number of the pulse signal P2 and the pulse signal P3 to obtain the CLK clock rising edge time delay difference n; in the third part, a time comparator of a time delay judgment strategy module records a digital difference value N of a time delay difference N, controls a time delay value DT to adjust the delay amount of the adjustable delayer, searches for a range larger than 1 CLK period, adjusts a time delay unit to be smaller than the CLK clock period, and completes the functions of interval searching and time delay screening judgment by using a time delay judgment strategy.

3. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module performs combined calculation to obtain a time delay correction quantity M according to the searched N0 values of a plurality of search periods, the process of the combined calculation is that every time a new N0 value is obtained, the N0 value of the time is compared with the N0 values searched for a plurality of times, if the N0 values are the same, the N0 value of the time is considered to be effective, a constant is added or subtracted according to the N0 to obtain an M value, if the N0 values are different, the N0 is considered to be possibly error data, and the M value is not calculated.

4. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module sets a time delay control quantity DT to the adjustable delayer, a corresponding digital difference value N is obtained by setting a time delay value DT once, searching is carried out in a period with the step not larger than CLK by controlling the time delay control quantity DT, the searching period is larger than the period of CLK according to the capacity of the adjustable delayer, and a time delay control range of external periodic pulse signals of the digital circuit system stably sampled by the clock CLK and a numerical value N0 of the digital difference value N corresponding to the range are obtained through searching of one searching period.

5. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: and the time delay judgment strategy module takes less than 1/5 CLK period to more than 1 CLK period as a beneficial search range, controls the time delay value DT to adjust the delay amount of the adjustable delayer, records the value N every time adjustment is carried out for 1 time, adjusts the time delay unit to be less than the CLK clock period, accumulates the time delay value DT on the time delay unit one by one, and obtains the digital difference value N of the time delay count of the time delay value DT and fine time delay adjustment data after the search range is carried out for one time.

6. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module can search limited round numbers or continuous search as required, after the search range of the time delay judgment strategy module is completed, the time delay judgment strategy module analyzes the interval of numerical value change and stability of the N value, selects the stable N value to determine a time delay correction quantity M, controls the time delay value DT again to perform a new round of search, jointly determines the time delay correction quantity M according to the digital difference value N of multiple rounds of search, obtains an external periodic pulse signal of the time delay control range which can be stably sampled by a clock CLK and an N value N0 corresponding to the range, and corrects a pulse signal P3 by using the N0 value to obtain an internal pulse signal which is stably synchronous with the external pulse signal.

7. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: the time delay judgment strategy module calculates the digital difference value N of the rising edges of the pulse signal P2 and the pulse signal P3 by changing the time delay value DT of the controllable time delay circuit every time, obtains the corresponding N by sequentially changing the DT, calculates the digital difference value N of the rising edges of the pulse signal P2 and the pulse signal P3 by changing the time delay value DT every time, obtains the time delay difference N between the pulse P2 and the pulse P3 by sequentially changing the time delay value DT, and records the time delay value DT corresponding to the moment when the N value jumps to the N +1 from the digital difference value N as the metastable state time delay value DT0.

8. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the adjustable delayer is set to be the initial delay value DT0, and the register sampling signal P1 value has a metastable state with sampling uncertainty, the phase relation between the input pulse P0 and the CLK is different, and the initial delay value DT0 value is different.

9. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the external input pulse signal of the digital circuit system disappears and the jump characteristic of the digital difference value N to N +1 cannot be searched, determining that the external input pulse-free signal exists, and keeping the time delay correction quantity M, so that the pulse signal P4 has continuous output and is synchronous with the pulse before the external pulse signal disappears.

10. The pulse delay accuracy adaptive synchronization method of claim 1, wherein: when the external input pulse signal of the digital circuit system disappears, determining the external input pulse-free signal according to the jump characteristic from the digital difference value N to N +1 which cannot be searched; when the external pulse signal disappears, the delay correction quantity M is kept, so that the pulse signal P4 has continuous output and is synchronous with the pulse before the external pulse signal disappears.