CN112951986A

CN112951986A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112951986A
Application number: CN201911264110.8A
Authority: CN
Inventors: 刘奇青; 陈侑廷; 白昌宗; 蓝顺醴; 李彦德; 倪志荣
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2021-06-11

Abstract

The invention provides a manufacturing method of a semiconductor element and the semiconductor element, wherein the manufacturing method of the semiconductor element comprises the following steps. A plurality of first vias are formed in the first dielectric layer in the memory cell region and the peripheral region. Performing surface treatment on the first vias to form a plurality of sacrificial layers. And removing the sacrificial layers to form a plurality of grooves. Forming a plurality of protective layers in the plurality of grooves. A memory element is formed on the first dielectric layer of the memory cell region. A second dielectric layer is formed over the memory element and over the first dielectric layer. Forming a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory elements in the memory cell region and the first vias in the peripheral region, respectively.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to integrated circuits and methods of fabricating the same, and more particularly, to a semiconductor device and a method of fabricating the same.

Background

With the advance of technology, various electronic products are developed towards the trend of high speed, high performance, light weight, small size and so on. How to effectively utilize the chip area and increase the yield rate is a very important issue at present.

The development of resistive memories, such as Resistive Random Access Memories (RRAMs), has been very rapid in recent years and is currently the most attractive future memory structure. Resistive memory is very suitable for the next generation of non-volatile memory devices due to its low power consumption, high speed operation, high density and potential advantages compatible with Complementary Metal Oxide Semiconductor (CMOS) process technology.

However, during the etching process for forming the memory device, the via (via) in the peripheral region is over-etched, so that the gap in the via is exposed, and slurry of the subsequent chemical mechanical polishing process remains in the gap, causing a problem of excessive contact resistance, or even causing the subsequently formed via not to contact with the gap.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which can avoid the problems of too high contact resistance or abnormal contact between vias.

An embodiment of the invention provides a method for manufacturing a semiconductor device, which includes the following steps. A plurality of first vias are formed in the first dielectric layer in the memory cell region and the peripheral region. Performing surface treatment on the first vias to form a plurality of sacrificial layers. And removing the sacrificial layers to form a plurality of grooves. Forming a plurality of protective layers in the plurality of grooves. A memory element is formed on the first dielectric layer of the memory cell region. A second dielectric layer is formed over the memory element and over the first dielectric layer. Forming a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory elements in the memory cell region and the first vias in the peripheral region, respectively.

In accordance with an embodiment of the present invention, wherein forming the memory element comprises: forming a first electrode layer, a variable resistance layer, a second electrode layer and a top cover layer on the first dielectric layer and the protective layer; and patterning the cap layer, the second electrode layer, the variable resistance layer and the first electrode layer to form the memory element in contact with the protective layer.

In accordance with an embodiment of the present invention, wherein forming the memory element comprises:

taking the protective layer as a first electrode layer; forming a variable resistance layer, a second electrode layer and a top cover layer on the protective layer; and patterning the second electrode layer, the variable resistance layer and the first electrode layer to form the memory element in contact with the first via.

According to an embodiment of the present invention, the method of manufacturing a semiconductor device further includes removing the protection layer in the peripheral region before forming the second via, wherein the second via in the peripheral region is in physical contact with the first via.

In accordance with an embodiment of the present invention, the second via and the first via in the peripheral region are electrically connected through the protection layer.

The embodiment of the invention provides a semiconductor element, which comprises a plurality of first dielectric windows, a plurality of second dielectric windows and a plurality of first dielectric layers, wherein the first dielectric windows are respectively arranged in a first dielectric layer in a memory cell area and a first dielectric layer in a peripheral area; a plurality of passivation layers embedded in the first via holes; a memory element on the protective layer and the first dielectric layer of the memory cell region; a second dielectric layer on the memory element and on the first dielectric layer; and a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region. The second via in the memory cell region is electrically connected to the memory element, and the second via in the peripheral region is electrically connected to the first via through the protection layer.

According to an embodiment of the present invention, a material of the passivation layer includes a conductive material different from the first vias.

According to an embodiment of the present invention, wherein the protective layer serves as a first electrode of the memory element.

According to an embodiment of the present invention, wherein the protective layer is in contact with the first electrode of the memory element.

According to the embodiment of the present invention, the thickness of the protective layer is smaller than that of the second electrode of the memory element.

In view of the above, the semiconductor device and the manufacturing method thereof according to the embodiments of the invention can increase the process margin by forming the protection layer, avoid the problems of too high contact resistance between the vias or abnormal contact, and reduce the distance between the memory devices.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIGS. 1A to 1I are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A-2B are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the invention.

Detailed Description

Referring to fig. 1A,

vias

108 and 109 connected to the conductive layer 100 are formed in the dielectric layer 102 in the memory cell region 10A and the peripheral region 10B, respectively. The dielectric layer 102 may be a single layer or a multi-layer, which may include silicon oxide, silicon nitride, or a combination thereof, and the dielectric layer 102 is a planarization layer planarized by a planarization process. The conductive layer 100 is, for example, any metal layer (conductive layer) of a metal interconnect structure formed on a substrate, such as the first metal layer closest to the substrate. The substrate may be a semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The metal layer is, for example, tungsten, aluminum, copper or a combination thereof formed by physical vapor deposition. Other components, such as transistors, may be included between the substrate and the metal layer.

The

vias

108 and 109 may include a barrier layer 104 and a plug (plug)106, respectively. The barrier layer 104 and the plug 106 may be formed by, for example, first forming a via opening (not shown) in the dielectric layer 102. Then, a barrier material layer is formed on the dielectric layer 102 and the via opening, and then the conductive layer is filled into the via opening. Thereafter, a Chemical Mechanical Polishing (CMP) process or an etch-back process is performed to remove the barrier material layer and the conductive layer on the dielectric layer 102. The barrier layer 104 may be formed of tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof, for example, by chemical vapor deposition. The material of the plug 106 includes a metallic material. The metal material may be, for example, tungsten, and the formation method thereof may be, for example, chemical vapor deposition. Although the cell area 10A in fig. 1A only shows two vias and the peripheral area 10B only shows one via, the invention is not limited thereto, and the number of vias may be adjusted as required in other embodiments.

Referring to fig. 1A and 1B, a surface treatment process 105 is performed to react the surface of the plug 106 to form a sacrificial layer 107. The treatment process 105 is, for example, an oxidation process. In one embodiment, the oxidation process may be a wet oxidation process. The wet oxidation process may use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of phosphoric acid as an oxidizing agent. When the treatment process 105 is an oxidation process, the sacrificial layer 107 is a metal oxide, such as tungsten oxide.

Referring to fig. 1B and 1C, an etching process is performed to remove the sacrificial layer 107 and expose the plug 106 a. The plug 106a and the barrier layer 104 form a recess 110. The depth T1 of the groove 110 is, for example, 40 nanometers (nm) to 100 nm. The etching process is, for example, a wet etching process. When the sacrificial layer 107 is a metal oxide, ammonia may be used as an etchant.

Referring to fig. 1C and 1D, a protection layer 112 is formed in the recess 110. The material of the protective layer 112 is different from that of the plug 106 a. The material of the protective layer 112 includes a conductor material. The conductive material is, for example, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), platinum (Pt), aluminum (Al) or a combination thereof formed by pvd or cvd. The protection layer 112 is formed by, for example, forming a protection material layer on the dielectric layer 102 and the recess 110, and then planarizing the protection material layer by a chemical mechanical polishing process or an etch-back process to remove the protection material layer on the dielectric layer 102. The top surface of the protective layer 112 may be coplanar with the top surface of the dielectric layer 102. The passivation layer 112 protects the underlying plug 106a during the planarization process, thereby preventing the etching solution or slurry used in the planarization process from flowing into the gap of the plug 106 a.

Then, a first electrode layer 114, a variable resistance layer 118, a second electrode layer 120 and a cap layer 122 are sequentially formed on the dielectric layer 102 and the protection layer 112. The materials of the first electrode layer 114 and the second electrode layer 120 may include metals and metal nitrides. The material of the first electrode layer 114 and the second electrode layer 120 includes titanium nitride (TiN), platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Y), manganese (Mo), or a combination thereof, and the formation method thereof may be, for example, a physical vapor deposition method or a chemical vapor deposition method. The first electrode layer 114 and the second electrode layer 120 may be a single layer or a plurality of layers. In some embodiments, the second electrode layer 120 may further include one or more barrier layers. The material of the barrier layer includes a metal oxide such as titanium oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. The barrier layer can prevent the phenomenon of non-uniformity of the conductive filaments caused by larger current flowing through the second electrode when setting or resetting.

The material of the variable resistance layer 118 may include a metal oxide, such as hafnium oxide (which may be HfO or HfO, for example)₂Etc.), lanthanum oxide, gadolinium oxide, yttrium oxide, zirconium oxide, titanium oxide, tantalum oxide, nickel oxide, tungsten oxide, copper oxide, cobalt oxide, iron oxide, aluminum oxide, or a combination thereof, a forming method thereofThe method is, for example, a chemical vapor deposition method. The thickness T2 of the variable resistance layer 118 is greater than the thickness T1 of the protective layer 112. When the thickness T1 is, for example, 40nm to 100nm, the thickness T2 is, for example, 50nm to 120 nm. The cap layer 122 can protect the second electrode layer 120 from being damaged by the plasma in the subsequent etching process. In addition, the cap layer 122 may also be an anti-reflective layer in a subsequent photolithography process. The material of the cap layer 122 is, for example, silicon oxynitride, silicon nitride or a combination thereof formed by chemical vapor deposition. Cap layer 122 may be a single layer or a plurality of layers.

Referring to fig. 1E, a photolithography and etching process is performed to pattern the cap layer 122 and the second electrode layer 120, so as to form a cap layer 122a and a second electrode 120A in the memory cell region 10A. The etching process includes an anisotropic etching process, such as a reactive ion etching process. Etching gases used in reactive ion etching processes are, for example, methane, boron trichloride (BCl)₃) Carbon tetrafluoride (CF)₄) Trifluoromethane (CHF)₃) Or a combination thereof. The cap layer 122a and the second electrode 120a have substantially vertical sidewalls, and the cap layer 122a has a dome shape.

Referring to fig. 1F, an etching process is performed to pattern the variable resistance layer 118 and the first electrode layer 114, so as to form a variable resistance layer 118a and a first electrode 114a in the memory cell region 10A. The variable resistance layer 118a and the first electrode 114a each have inclined sidewalls due to a difference in etching characteristics. In addition, the etching process may be performed excessively to ensure that the first electrodes 114a of the adjacent memory cells in the memory cell region 10A are completely separated, and thus, a portion of the dielectric layer 102 may also be etched. Since the material of the protection layer 112 is different from the material of the variable resistance layer 118 and the first electrode layer 114, and the etching rate is different, the protection layer 112 in the peripheral region 10B can protect the plug 106a below, so as to prevent the plug 106a from being damaged by etching. Therefore, a Process margin (Process Window) may be increased by the formation of the protective layer 112.

In some embodiments, the first electrode 114a, the variable resistance layer 118a, the second electrode 120A and the cap layer 122a in the memory cell region 10A constitute a memory cell 50. In other embodiments, the protection layer 112 in the memory cell region 10A can also be considered as a part of the memory cell 50. The second electrode 120A serves as the upper electrode 120A of the memory element 50, and the passivation layer 112 and the first electrode 114a in the memory cell region 10A can be collectively referred to as the lower electrode 116 of the memory element 50.

Referring to fig. 1G, a barrier layer 124 and a dielectric layer 126 are formed in the memory cell region 10A and the peripheral region 10B. The material of the barrier layer 124 includes a metal oxide, such as hafnium oxide, lanthanum oxide, gadolinium oxide, yttrium oxide, zirconium oxide, titanium oxide, tantalum oxide, nickel oxide, tungsten oxide, copper oxide, cobalt oxide, iron oxide, aluminum oxide, or a combination thereof, and the formation method thereof may be, for example, an atomic layer deposition method or a chemical vapor deposition method. The material of the dielectric layer 126 may include silicon oxide, silicon nitride, or a combination thereof, and the formation method thereof may be, for example, a chemical vapor deposition method. The dielectric layer 126 may be a single layer or multiple layers. The material of the dielectric layer 126 may include silicon oxide, silicon nitride, or a combination thereof, and the formation method thereof may be, for example, a chemical vapor deposition method. The dielectric layer 126 may be a planarization layer planarized via a CMP process.

Referring to fig. 1H, a photolithography and etching process is performed to remove a portion of the dielectric layer 126, the barrier layer 124 and the cap layer 122a in the memory cell region 10A, thereby forming a via opening 128 exposing the second electrode 120A. In addition, the dielectric layer 126, the barrier layer 124 and the passivation layer 112 in the peripheral region 10B are removed to form a via opening 130 exposing the plug 106 a.

During the etching process, the cap layer 122 may serve as an etching stop layer because the material of the cap layer 122 is different from the material of the dielectric layer 126 and has a smaller etching rate. After the passivation layer 112 in the peripheral region 10B is exposed, the cap layer 122 in the memory cell region 10A is removed. Then, the protection layer 112 in the peripheral region 10B is removed. In the process of removing the protection layer 112 in the peripheral region 10B, even though a part of the second electrode 120a is etched, since the thickness T2 of the second electrode 120a is greater than the thickness T1 of the protection layer 112 in the peripheral region 10B, a sufficient thickness of the second electrode 120a is still remained after the protection layer 112 in the peripheral region 10B is completely removed.

Referring to fig. 1I, vias 136 and 138 are formed in via

openings

128 and 130, respectively. The

vias

136 and 138 may include the barrier layer 132 and the plug 134, respectively. The barrier layer 132 and plug 134 may be formed, for example, by forming a barrier material layer on the dielectric layer 126 and the via

openings

128 and 130, and then forming a conductive layer. Thereafter, a chemical mechanical polishing process or an etch-back process is performed to remove the barrier material layer and the conductive layer on the dielectric layer 126. The material of the barrier material layer may be, for example, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof, and the forming method thereof is, for example, chemical vapor deposition. The material of the conductive layer includes a metal material, the metal material may be tungsten, for example, and the forming method may be a chemical vapor deposition method, for example.

Thereafter, a dielectric layer and metal features electrically connected to

vias

136 and 138, respectively, may be formed on dielectric layer 126. The metal feature is a portion of a metal interconnect structure, which may be a metal layer, such as a second metal layer.

In the present embodiment, the via 136 is electrically connected to and physically contacts the second electrode 120 a. Via 138 extends through dielectric layer 126 and into dielectric layer 102, electrically connecting and physically contacting via 109. The variable resistance layer 118 and the first electrode 114a have inclined sidewalls. The bottom area of the variable-resistance layer 118 is substantially the same as the top area of the first electrode 114 a.

The first electrode 114a covers and is in physical contact with the passivation layer 112, the barrier layer 104, and a portion of the dielectric layer 102. The passivation layer 112 is embedded in the via 108, and physically contacts the plug 106 and the barrier layer 104 of the via 108 and is surrounded by the plug 106 and the barrier layer 104 of the via 108.

Referring to fig. 2A, the present embodiment is very similar to the first embodiment, and according to the method of the first embodiment, after the dielectric layer 126 (fig. 1G) is formed, via openings 128 and 130A are formed in the memory cell region 10A and the peripheral region 10B, respectively. The via opening 128 penetrates the dielectric layer 126, the barrier layer 124 and the cap layer 122a to expose the second electrode 120 a. The via opening 130a exposes the passivation layer 112. In other words, the passivation layer 112 in the peripheral region 10B is retained without being etched and removed during the formation of the via

openings

128 and 130 a.

Referring to fig. 2B, vias 136 and 138a are formed in the via

openings

128 and 130a, respectively, according to the method of the above embodiment. The

vias

136 and 138a may include the barrier layer 132 and the plug 134, respectively. The via 136 is electrically connected to and physically contacts the second electrode 120 a. The via 138a and the via 109 are not in physical contact, but are electrically connected through the passivation layer 112. The passivation layer 112 is embedded in the via 109. The passivation layer 112 is in physical contact with the plug 106 and the barrier layer 104 of the via 109 and is surrounded by the plug 106 and the barrier layer 104 of the via 109.

Referring to fig. 3, the present embodiment is very similar to the first embodiment, and according to the method of the first embodiment, after the protection layer 112 is formed in the groove 110, the first electrode layer 114 is not formed, and the variable resistance layer 118, the second electrode layer 120 and the cap layer 122 are directly formed (fig. 1C and 1D). Then, vias 136 and 138 are formed according to the method of the first embodiment.

The structure of the semiconductor device of this embodiment is very similar to that of the semiconductor device of the first embodiment, and the difference is that: in the present embodiment, the passivation layer 112 in the memory cell region 10A is used as a first electrode (or bottom electrode) of the memory device. Thus, the first electrode (the passivation layer 112) of the memory device is in physical contact with the plug 106 and the barrier layer 104 of the via 108 and is surrounded by the plug 106 and the barrier layer 104 of the via 108. The variable resistance layer 118a has a thickness of

The second electrode 120a has an inclined sidewall. In other words, the size of the top surface of the variable resistance layer 118a is smaller than the size of the bottom surface.

On the other hand, the via opening for forming the via 108 may have vertical sidewalls or sidewalls inclined toward the conductor layer 100. Thus, the first electrode (the passivation layer 112) may have a vertical sidewall or a sidewall inclined to the conductor layer 100. Therefore, the size of the top surface of the first electrode (protective layer 112) may be greater than or equal to the size of the bottom surface of the first electrode (protective layer 112).

The first electrode (protective layer 112) is discontinuous with the sidewall of the variable-resistance layer 118 a. The top area of the first electrode (protective layer 112) is smaller than the bottom area of the variable resistance layer 118. The first electrode (passivation layer 112), the barrier layer 104, and a portion of the dielectric layer 102 are covered by and in physical contact with the variable resistance layer 118.

Since the first electrode (passivation layer 112) is formed in the via 108 in a damascene manner and is self-aligned to the via 108, it can be considered a self-aligned process. In addition, since the first electrode (the protection layer 112) is formed in a damascene manner, the problem that the first electrode is difficult to etch is not confronted in the process. In addition, the distance between the two adjacent first electrodes does not need to be increased to ensure that the two adjacent first electrodes cannot be disconnected due to the inclined side walls of the two adjacent first electrodes. Since the size of the first electrode (protective layer 112) is small, the distance between the memory elements can be reduced.

Referring to fig. 4, the present embodiment is very similar to the third embodiment, and the difference is: in the present embodiment, the passivation layer 112 remains during the formation of the via opening in the peripheral region 10B without etching and removing. Therefore, the structure of the semiconductor device of this embodiment is very similar to that of the semiconductor device of the third embodiment, and the difference is as follows: the via 138a in this embodiment is electrically connected to and physically contacts the passivation layer 112 through the dielectric layer 126 and the barrier layer 124. In other words, the via 138a and the via 109 are not in physical contact, but are electrically connected through the passivation layer 112.

In the embodiment of the invention, the grooves can be formed on the dielectric layer windows on the lower layer through the surface treatment process and the etching process, and the protective layers can be formed in the grooves. The formation of the protective layer can prevent the dielectric layer window from being damaged by etching, and increase the process margin.

Furthermore, in some embodiments, the passivation layer may be completely removed, so that the upper and lower vias formed in the peripheral region may have good contact therebetween, thereby avoiding problems such as too high contact resistance or abnormal contact.

In addition, in other embodiments, the passivation layer may be left as the first electrode of the memory device, and the process steps and costs may be reduced because the passivation layer may be self-aligned to the underlying via without the need for an additional photomask. On the other hand, since the size of the protective layer as the first electrode is small, the pitch between the memory elements can be reduced.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, but rather, may be embodied in many different forms without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of first dielectric windows in the first dielectric layer in the memory cell area and the peripheral area;

performing surface treatment on the first dielectric windows to form a plurality of sacrificial layers;

removing the sacrificial layers to form grooves;

forming a plurality of protective layers in the plurality of grooves;

forming a memory element on the first dielectric layer of the memory cell region;

forming a second dielectric layer on the memory element and on the first dielectric layer; and

forming a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory elements in the memory cell region and the first vias in the peripheral region, respectively.

2. The manufacturing method of a semiconductor element according to claim 1, wherein forming the memory element comprises:

forming a first electrode layer, a variable resistance layer, a second electrode layer and a top cover layer on the first dielectric layer and the protective layer; and

and patterning the top cover layer, the second electrode layer, the variable resistance layer and the first electrode layer to form the storage element in contact with the protective layer.

3. The manufacturing method of a semiconductor element according to claim 1, wherein forming the memory element comprises:

taking the protective layer as a first electrode layer;

forming a variable resistance layer, a second electrode layer and a top cover layer on the protective layer; and

and patterning the second electrode layer, the variable resistance layer and the first electrode layer to form the memory element in contact with the first via.

4. The method of claim 1, further comprising removing the protection layer in the peripheral region before forming the second via, wherein the second via in the peripheral region is in physical contact with the first via.

5. The method of claim 1, wherein the second via and the first via in the peripheral region are electrically connected through the passivation layer.

6. A semiconductor component, comprising:

a plurality of first dielectric windows in the first dielectric layer in the memory cell region and the peripheral region, respectively;

a plurality of passivation layers embedded in the first via holes; and

a memory element on the protective layer and the first dielectric layer of the memory cell region;

a second dielectric layer on the memory element and on the first dielectric layer; and

a plurality of second vias in the second dielectric layer in the memory cell region and the peripheral region, wherein the second vias in the memory cell region are electrically connected to the memory elements, and the second vias in the peripheral region are electrically connected to the first vias through the protection layer.

7. The semiconductor device as defined in claim 6, wherein a material of the protection layer comprises a different conductive material than the first vias.

8. The semiconductor element according to claim 6, wherein the protective layer serves as a first electrode of the memory element.

9. The semiconductor element according to claim 6, wherein the protective layer is in contact with a first electrode of the memory element.

10. The semiconductor element according to claim 8 or 9, wherein a thickness of the protective layer is smaller than a thickness of the second electrode of the memory element.