CN111952446B - Structure of resistive random access memory and forming method thereof - Google Patents
Structure of resistive random access memory and forming method thereof Download PDFInfo
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- CN111952446B CN111952446B CN201910403390.XA CN201910403390A CN111952446B CN 111952446 B CN111952446 B CN 111952446B CN 201910403390 A CN201910403390 A CN 201910403390A CN 111952446 B CN111952446 B CN 111952446B
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- 238000000034 method Methods 0.000 title claims abstract description 81
- 239000010410 layer Substances 0.000 claims abstract description 256
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000011241 protective layer Substances 0.000 claims abstract description 39
- 230000008859 change Effects 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 60
- 239000007772 electrode material Substances 0.000 claims description 39
- 238000005530 etching Methods 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- -1 silicon carbide nitride Chemical class 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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Abstract
A structure of a resistance random access memory and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate; forming a bottom electrode on the substrate; forming a resistive layer on the bottom electrode; forming a top electrode on the resistive layer; and forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistance change layer. The performance of the formed RRAM is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a structure of a resistive random access memory and a method for forming the same.
Background
Among Integrated Circuit (IC) devices, resistive random access memory (RESISTIVE RANDOM ACCESS MEMORY, simply RRAM) is an emerging technology for next generation non-volatile memory devices. A resistive random access memory is a memory structure including an array of resistive random access memory cells, each of which uses a resistance value instead of a charge to store a small amount of data. Specifically, each of the resistive random access memory cells includes a resistive material layer, and the resistance of the resistive material layer may be adjusted to display a logic "0" or a logic "1".
In advanced technology nodes, the size of the components is scaled down and the size of the memory device is correspondingly reduced, which requires a corresponding increase in the precision of each process for forming the resistive random access memory, so as to meet the requirement for high performance of the resistive random access memory.
However, the performance of the existing resistive random access memory needs to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a structure of a resistive random access memory and a forming method thereof, which can improve the performance of the resistive random access memory.
In order to solve the above technical problems, the present invention provides a method for forming a resistive random access memory cell, including: providing a substrate; forming a bottom electrode on the substrate; forming a resistive layer on the bottom electrode; forming a top electrode on the resistive layer; and forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistance change layer.
Optionally, the process of forming the first protective layer includes: and (5) a deposition process.
Optionally, the material of the first protective layer includes nitride, carbide or carbonitride.
Optionally, the material of the first protection layer includes silicon nitride or silicon carbide nitride.
Optionally, the thickness range of the first protective layer includes: 100 nm-200 nm.
Optionally, before forming the first protective layer, the method further includes: forming a second protective layer on the surface of the top electrode; and forming the first protective layer on the second protective layer.
Optionally, after forming the first protection layer on the top surface of the top electrode, the sidewall surface of the top electrode, and the sidewall surface of the resistive layer, the method further includes: an isolation layer is formed on the substrate and the first protection layer surface.
Optionally, the forming method of the resistive layer and the top electrode includes: forming a resistive layer material on the surface of the substrate and the surface of the bottom electrode; forming a top electrode material layer on the resistive layer material; forming a first mask layer on the top electrode material layer, wherein the first mask layer exposes a part of the top electrode material layer; and etching the top electrode material layer and the resistive layer material by taking the first mask layer as a mask to form the top electrode and the resistive layer.
Optionally, before forming the resistive layer material on the surface of the substrate and the surface of the bottom electrode, the method further comprises: an etch stop layer is formed on the substrate, the etch stop layer also being located on a sidewall surface of the bottom electrode, and the etch stop layer surface being below or flush with a top surface of the bottom electrode.
Optionally, the forming method of the bottom electrode includes: forming a bottom electrode material layer on the surface of the substrate; forming a second mask layer on the surface of the bottom electrode material layer, wherein the second mask layer exposes part of the surface of the bottom electrode material layer; and etching the bottom electrode material layer by taking the second mask layer as a mask until the surface of the substrate is exposed, and forming the bottom electrode on the substrate.
Optionally, the substrate includes: a substrate; the device layer comprises a device structure, an interconnection structure and a dielectric layer, wherein the device structure is arranged on the substrate, the interconnection structure is electrically connected with the device structure, the dielectric layer is arranged on the surface of the substrate, the surface of the device structure and the surface of the interconnection structure, and the dielectric layer exposes the top surface of the interconnection structure; the bottom electrode is located on the surface of the interconnection structure.
Optionally, the material of the bottom electrode comprises a metal; the metal comprises tungsten or titanium nitride.
Optionally, the material of the resistive layer comprises a transition metal oxide; the transition metal oxide includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, or titanium oxide.
Optionally, the material of the top electrode comprises a metal comprising copper, aluminum, tungsten or titanium nitride.
Correspondingly, the invention also provides a resistive random access memory unit formed by adopting any one of the methods, which comprises the following steps: a substrate; a bottom electrode on the substrate; a resistive layer on the bottom electrode; a top electrode on the resistive layer; and the first protection layer is positioned on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistance change layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the side wall of the resistance change layer is protected by forming the protective layer on the side wall of the resistance change layer, and the protective layer can prevent external impurities from invading the resistance change layer, so that the side wall of the resistance change layer is not easy to oxidize in a subsequent process, the shape and the material of the resistance change layer are not easy to change in a subsequent process, and the shape and the size uniformity of the resistance change layer and the stability of the material of the resistance change layer are improved. Therefore, by forming the protective layer, the uniformity of the resistance change layer in each resistance change random access memory unit can be improved, and the uniformity of the electrical performance of each resistance change random access memory unit is further improved, so that the performance of the resistance change random access memory is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a RRAM structure according to the present invention;
fig. 2 to 9 are schematic cross-sectional views illustrating a process of forming a resistive random access memory according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the resistive random access memory formed by the prior art needs to be improved. The analysis will now be described in connection with the structure of a resistive random access memory.
FIG. 1 is a schematic cross-sectional view of a RRAM structure.
Referring to fig. 1, a substrate 100 is provided, and the substrate 100 has a resistive random access memory structure thereon, wherein the resistive random access memory structure includes a bottom electrode 101 on the substrate 100, a resistive layer 102 on the bottom electrode 101, a top electrode 103 on the resistive layer 102, and a dielectric layer 104 on the substrate 100, which covers the top and the side walls of the top electrode 103 and the side walls of the resistive layer 102.
In the resistive random access memory structure, the material of the dielectric layer 104 is silicon oxide, the material of the resistive layer 102 is a transition metal oxide, and the transition metal oxide is an incompletely oxidized transition metal oxide.
After forming the top electrode 103 and the resistive layer 102, a dielectric layer 104 that completely covers the resistive random access memory structure needs to be formed on the substrate for a subsequent process, where the process of forming the dielectric layer 104 is a chemical vapor deposition process. Since the material of the dielectric layer generally includes an oxide, the reaction gas of the chemical vapor deposition process includes an oxygen-containing gas, and since the material of the resistive random access memory 102 is a transition metal oxide that is not completely oxidized, oxygen oxidizes the resistive random access memory 102 from the position of the sidewall of the resistive random access memory 102, and after the sidewall of the resistive random access memory 102 is oxidized, the volume of the resistive random access memory 102 becomes larger, and the thickness of the sidewall of the resistive random access memory 102 becomes larger in the direction perpendicular to the horizontal direction of the substrate 100, thereby causing uneven thickness of the resistive random access memory 102, causing uneven resistance of the resistive random access memory, and further causing uneven electrical performance of the resistive random access memory cells, and affecting the performance of the resistive random access memory.
In order to solve the problems, the invention provides a resistive random access memory and a forming method thereof, wherein the side wall of the resistive random access memory is protected by forming a protective layer on the side wall of the resistive layer, so that the resistive layer is not oxidized in the subsequent process of forming a dielectric layer, the problem that the thickness of the resistive layer is uneven due to the fact that the thickness of the side wall of the resistive layer is changed due to the fact that the side wall of the resistive layer is oxidized is avoided, and the resistance of the resistive layer of each resistive random access memory unit is uneven is solved, and accordingly the consistency of the electrical performance of each resistive random access memory unit is improved, and the performance of the resistive random access memory is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic cross-sectional views illustrating a process of forming a resistive random access memory according to an embodiment of the invention.
Referring to fig. 2, a substrate is provided.
In this embodiment, the substrate includes a base 200, a device layer 300 on the base 200, the device layer 300 includes a device structure (not shown) on the base 200, an interconnect structure (not shown) electrically connected to the device structure, and a dielectric layer (not shown) on a surface of the base 200, a surface of the device structure, and a surface of the interconnect structure, and the dielectric layer exposes a top surface of the interconnect structure.
The material of the substrate 200 includes monocrystalline silicon, polycrystalline silicon, amorphous silicon or silicon, germanium, silicon germanium, gallium arsenide semiconductor material; in this embodiment, the substrate 200 is made of monocrystalline silicon.
In this embodiment, the material of the dielectric layer includes silicon oxide; in other embodiments, the material of the dielectric layer comprises silicon nitride.
In this embodiment, the device structure includes a gate structure; in other embodiments, the device structure can be other than a gate structure.
In this embodiment, the interconnect structure includes a metal wire; in other embodiments, the interconnect structure can be other than a metal wire.
In other embodiments, the substrate includes a base and a dielectric layer on the base, and the substrate can be devoid of a device layer on the base.
In this embodiment, a bottom electrode is subsequently formed on the substrate. Please refer to fig. 3 to fig. 4.
Referring to fig. 3, a bottom electrode material layer 201 is formed on the surface of the substrate; a second mask layer 202 is formed on the surface of the bottom electrode material layer 201, and the second mask layer 202 exposes a portion of the surface of the bottom electrode material layer 201.
The process of forming the bottom electrode material layer 201 includes a physical vapor deposition process, an electroplating process, or an electroless plating process. In this embodiment, the process of forming the bottom electrode material layer 201 includes a physical vapor deposition process.
The material of the bottom electrode material layer 201 includes tungsten or titanium nitride.
The material of the second mask layer 202 includes photoresist.
Referring to fig. 4, the bottom electrode material layer 201 is etched with the second mask layer 202 as a mask until the surface of the substrate is exposed, the bottom electrode 204 is formed on the substrate, and the bottom electrode 204 is located on the surface of the interconnection structure in the substrate.
In this embodiment, the process of etching the bottom electrode material layer 201 includes an anisotropic dry etching process.
In this embodiment, after forming the bottom electrode 204, the second mask layer 202 is removed; the process of removing the second mask layer 202 includes an ashing process.
Referring to fig. 5, after the second mask layer 202 is removed, an etching stop layer 205 is formed on the substrate, and the etching stop layer 205 is further located on a sidewall surface of the bottom electrode 204.
The method for forming the etching stop layer 205 includes: forming the etch stop layer material (not shown) on the substrate surface and the sidewalls and top surface of the bottom electrode 204; the etch stop layer material is polished using a chemical mechanical polishing process until the top surface of the bottom electrode 204 is exposed.
In this embodiment, the material of the etching stop layer 205 includes silicon nitride or silicon carbide nitride; the process of forming the etch stop layer material includes a chemical vapor deposition process.
The etching stop layer 205 is used for protecting the substrate from being damaged by etching when the resistive layer and the top electrode are formed on the bottom electrode 204 later.
In this embodiment, the surface of the etch stop layer 205 is flush with the top surface of the bottom electrode 204; in other embodiments, the etch stop layer 205 surface is lower than the top surface of the bottom electrode 204.
The etch stop layer 205 surface is lower or flush with the top surface of the bottom electrode 204 in the sense that: if the surface of the etching stop layer 205 is higher than the top surface of the bottom electrode 204, the contact area between the resistive layer formed on the surface of the bottom electrode 204 and the bottom electrode 204 is too small or is not in contact with the resistive layer, and the contact area between the resistive layer and the bottom electrode 204 is small, so that the contact resistance between the resistive layer and the bottom electrode 204 is increased, thereby increasing the power consumption of the device and being unfavorable for improving the performance of the device; and failure of the resistive layer to contact the bottom electrode 204 can result in open circuits that affect device performance.
In this embodiment, after the etching stop layer 205 is formed, a resistive layer is formed on the bottom electrode 204; a top electrode is formed on the resistive layer. Please refer to fig. 6 to fig. 7.
Referring to fig. 6, a resistive layer material layer 210 is formed on the surface of the substrate and the surface of the bottom electrode 204; forming a top electrode material layer 211 on the resistive layer material layer 210; a first mask layer 213 is formed on the top electrode material layer 211, the first mask layer 213 exposing a portion of the top electrode material layer 211.
In this embodiment, before forming the first mask layer 213, a second protective layer material layer 212 is further formed on the surface of the top electrode material layer 211.
The material of the resistive layer material layer comprises transition metal oxide; in this embodiment, the material of the resistive layer material layer includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide or titanium oxide; the process of forming the resistive layer material layer 210 includes a chemical vapor deposition process.
The material of the top electrode material layer comprises a metal; in this embodiment, the material of the top electrode material layer includes copper, aluminum, tungsten, or titanium nitride.
The process of forming the top electrode material layer 211 includes a physical vapor deposition process, an electroplating process, or an electroless plating process; in this embodiment, the process of forming the top electrode material layer 211 includes a physical vapor deposition process.
In this embodiment, a second protective layer material layer 212 is formed on the surface of the top electrode material layer 211. The second protective layer material comprises silicon nitride or silicon carbide nitride; the process of forming the second protective layer material 212 includes a chemical vapor deposition process. The second protective layer material is used to protect the top electrode material layer 211 from damage during subsequent processes.
In other embodiments, the top electrode material layer 211 surface can also be free of the second protective layer material layer 212.
In this embodiment, the first mask layer 213 includes a patterned photoresist.
Referring to fig. 7, the first mask layer 213 is used as a mask to etch the top electrode material layer 211 and the resistive layer material layer 210, so as to form a resistive layer 310 and a top electrode 311 on the surface of the resistive layer.
In this embodiment, before etching the top electrode material layer 211, the method further includes etching the second protection layer material layer 212 with the first mask layer 213 as a mask, so as to form a second protection layer 312 on the surface of the top electrode 311.
In the present embodiment, the process of etching the second protective layer material layer 212, the top electrode material layer 211 and the resistive layer material layer 210 includes an anisotropic dry etching process.
In this embodiment, during the process of etching the second protective layer material layer 212, the top electrode material layer 211 and the resistive layer material layer 210, a portion of the etching stop layer 205 is also etched.
In this embodiment, the second protection layer 312 is used to protect the top surface of the top electrode 311 from being damaged by etching or oxidized in the subsequent process, thereby affecting the performance of the device. In other embodiments, the second protective layer 312 may be absent.
In this embodiment, after the second protection layer 312, the top electrode 311 and the resistive layer 310 are formed, the first mask layer 213 is removed; the process of removing the first mask layer 213 includes an ashing process.
Referring to fig. 8, a first protective layer 401 is formed on the top surface of the second protective layer 312, the sidewall surface of the top electrode 311, and the sidewall surface of the resistive layer 310.
The material of the first protective layer 401 includes nitride, carbide, or carbonitride; in this embodiment, the material of the first protection layer 401 includes silicon nitride or silicon carbide nitride.
In this embodiment, the process of forming the first protection layer 401 includes a deposition process.
In this embodiment, the thickness range of the first protective layer includes: 100 nm-200 nm.
The meaning of forming the first protection layer 401 on the top surface of the second protection layer 312, the sidewall surface of the top electrode 311, and the sidewall surface of the resistive layer 310 is that: the first protection layer 401 formed on the surface of the side wall of the resistive layer 310 protects the side wall of the resistive layer 310, and prevents the side wall of the resistive layer 310 from being oxidized in the subsequent process of forming the isolation layer, so that the side wall of the resistive layer 310 cannot be changed in thickness due to the fact that the volume of the side wall of the resistive layer 310 is increased due to oxidization, the uniformity of the thickness of the resistive layer 310 is improved, the uniformity of the resistance of the resistive layer of each resistive random access memory unit is improved, and the uniformity of the electrical performance of each resistive random access memory unit is improved, and the performance of the resistive random access memory is improved.
The significance of selecting silicon nitride or silicon carbide nitride as the material of the first protective layer 401 is that: the silicon nitride or silicon carbide nitride is not involved in oxygen in the formation process, so that the side wall of the resistive layer 310 is prevented from being oxidized due to contact with oxygen; meanwhile, the silicon nitride or silicon carbide nitride has compact structure, and can effectively block oxygen in the subsequent isolation layer forming process, so that the side wall of the resistive layer 310 is prevented from being oxidized due to contact with oxygen.
The meaning of selecting the thickness range of the first protection layer 401 to be 100nm to 200nm is that: if the thickness of the first protection layer 401 is smaller than 100nm, the protection effect of the first protection layer 401 on the sidewall of the resistive layer 310 is weak, meaning of forming the first protection layer 401 on the surface of the sidewall of the resistive layer 310 is lost, the first protection layer 401 does not play an expected role, and meanwhile, the thickness is too small to be accurately controlled in a process; if the thickness of the first protection layer 401 is greater than 200nm, the thicker first protection layer 401 is not compatible with the logic of the circuit, which affects the performance during the process.
Referring to fig. 9, after forming the first protective layer 401, an isolation layer 402 is formed on the substrate and on the first protective layer 401.
In this embodiment, after forming the first protection layer 401 and before forming the isolation layer 402, forming a second stop layer (not shown) on the substrate and on the surface of the first protection layer 401; in other embodiments, the second stop layer may not be formed.
In this embodiment, the material of the isolation layer 402 includes silicon oxide; the process of forming the isolation layer 402 includes a chemical vapor deposition process.
In this embodiment, the isolation layer 402 serves as a mutual isolation for semiconductor structures subsequently formed on the substrate.
Correspondingly, the embodiment of the invention also provides a resistive random access memory formed by adopting the method, please continue to refer to fig. 9, which includes:
A substrate;
a bottom electrode 204 located on the substrate;
a resistive layer 310 located on the bottom electrode 204;
a top electrode 311 on the resistive layer 310;
A first protection layer 401 located on the top surface and the sidewall surface of the top electrode 311 and the sidewall surface of the resistive layer 310.
The following description will be made with reference to the accompanying drawings.
In this embodiment, the substrate includes a base 200 and a device layer 300 on the base 200.
In this embodiment, the substrate further has an etching stop layer 205 thereon, the bottom electrode 204 is located in the etching stop layer 205, the etching stop layer 205 is further located on a sidewall surface of the bottom electrode 204, and the etching stop layer 205 is lower than or flush with a top surface of the bottom electrode 204.
In this embodiment, further comprising: the second protection layer 312 is located on the surface of the top electrode 311, and the first protection layer 401 is located on the second protection layer 312.
In this embodiment, further comprising: an isolation layer 402 on the substrate and on the surface of the first protection layer 401.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a resistive random access memory cell, comprising:
Providing a substrate;
Forming a bottom electrode on the substrate;
Forming an etch stop layer on the substrate, the etch stop layer also being located on a sidewall surface of the bottom electrode, and the etch stop layer surface being lower than or flush with a top surface of the bottom electrode;
forming a resistive layer on the bottom electrode and on the etch stop layer;
forming a top electrode on the resistive layer;
And forming a first protective layer on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistance change layer.
2. The method of forming a resistive random access memory cell of claim 1, wherein forming the first protective layer comprises: and (5) a deposition process.
3. The method of forming a resistive random access memory cell of claim 1, wherein the material of the first protective layer comprises a nitride, carbide, or carbonitride.
4. The method of claim 3, wherein the material of the first protective layer comprises silicon nitride or silicon carbide nitride.
5. The method of forming a resistive random access memory cell of claim 1, wherein the range of thicknesses of the first protective layer comprises: 100 nm-200 nm.
6. The method of forming a resistive random access memory cell of claim 1, further comprising, prior to forming the first protective layer: forming a second protective layer on the surface of the top electrode;
And forming the first protective layer on the second protective layer.
7. The method of forming a resistive random access memory cell of claim 1, further comprising, after forming a first protective layer on a top surface of the top electrode, a sidewall surface of the top electrode, and a sidewall surface of the resistive layer: an isolation layer is formed on the substrate and the first protection layer surface.
8. The method of forming a resistive random access memory cell of claim 1, wherein the method of forming a resistive layer and a top electrode comprises: forming a resistive layer material on the surface of the substrate and the surface of the bottom electrode; forming a top electrode material layer on the resistive layer material; forming a first mask layer on the top electrode material layer, wherein the first mask layer exposes a part of the top electrode material layer; and etching the top electrode material layer and the resistive layer material by taking the first mask layer as a mask to form the top electrode and the resistive layer.
9. The method of forming a resistive random access memory cell of claim 1, wherein the method of forming the bottom electrode comprises: forming a bottom electrode material layer on the surface of the substrate; forming a second mask layer on the surface of the bottom electrode material layer, wherein the second mask layer exposes part of the surface of the bottom electrode material layer; and etching the bottom electrode material layer by taking the second mask layer as a mask until the surface of the substrate is exposed, and forming the bottom electrode on the substrate.
10. The method of forming a resistive random access memory cell of claim 1, wherein the substrate comprises: a substrate and a device layer on the substrate; the device layer comprises a device structure positioned on the surface of the substrate, an interconnection structure electrically connected with the device structure and a dielectric layer; the dielectric layer is positioned on the surface of the substrate, the surface of the device structure and the surface of the interconnection structure, and the dielectric layer exposes the top surface of the interconnection structure; the bottom electrode is located on the surface of the interconnection structure.
11. The method of forming a resistive random access memory cell of claim 1, wherein the material of the bottom electrode comprises a metal; the metal comprises tungsten or titanium nitride.
12. The method of forming a resistive random access memory cell of claim 1, wherein the material of the resistive layer comprises a transition metal oxide; the transition metal oxide includes hafnium oxide, zirconium oxide, aluminum oxide, nickel oxide, tantalum oxide, or titanium oxide.
13. The method of forming a resistive random access memory cell of claim 1, wherein the material of the top electrode comprises a metal comprising copper, aluminum, tungsten, or titanium nitride.
14. A resistive random access memory cell formed by the method of any one of claims 1 to 13, comprising:
A substrate;
A bottom electrode on the substrate;
a resistive layer on the bottom electrode;
A top electrode on the resistive layer;
and the first protection layer is positioned on the top surface of the top electrode, the side wall surface of the top electrode and the side wall surface of the resistance change layer.
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