CN112864249A - Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof - Google Patents
Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 15
- 238000005280 amorphization Methods 0.000 claims description 13
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
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- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
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- 238000004519 manufacturing process Methods 0.000 claims 3
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Abstract
The invention relates to a low-grid-leakage-charge groove type power semiconductor device and a preparation method thereof. The non-crystallization area is arranged right below the bottom of the cell groove, the non-crystallization area bombards the crystal grain single crystal silicon with the same crystal face orientation at the bottom of the cell groove into a non-crystallization state with different crystal face orientations by controlling a hydrogen injection method, the crystal material of the non-crystallization area is subjected to non-crystallization transformation due to too large crystal lattice damage density, so that after the crystal material is grown by a thermal oxidation furnace tube process, a bottom insulating gate oxide layer can be formed through the non-crystallization area, the thickness of the bottom insulating gate oxide layer is 1.4 times of that of an upper insulating gate oxide layer, the thickness of the insulating gate oxide layer covering the bottom of the cell groove can be increased, the width of a table top at the bottom of the cell groove is effectively increased, the effective area of parasitic capacitance is reduced, the gate leakage charge Qgd is reduced, and the non.
Description
Technical Field
The invention relates to a trench type power semiconductor device and a preparation method thereof, in particular to a trench type power semiconductor device with low grid leakage charges and a preparation method thereof.
Background
With the continuous development of semiconductor integrated circuits, the chip size is continuously reduced, and the working voltage is also smaller and smaller, so that the requirement on power management is higher and higher, especially the efficiency of low-voltage dc-dc step-down conversion. The application of high-efficiency and small-volume switch mode power supplies is popularized, and the application in the fields of PCs and notebook computers, electric vehicles, hybrid electric vehicles (new energy vehicles), quick charging, wireless charging and the like is rapidly emerging. Power MOSFETs are used in almost all of these areas, and trench power MOSFET devices are one of the important members of this large family. The trench power MOSFET device can save the device area and obtain lower on-resistance, thereby having lower on-loss. However, as the cell density of the device is gradually increased, the channel area is increased, thereby causing an increase in gate charge, which affects the high frequency characteristics and switching loss of the device.
As is well known, in the application of power MOSFET products, the power loss of the device itself is composed of conduction loss and switching loss, and in a high-frequency operating environment, the power loss is mainly the switching loss, and the switching loss is mainly determined by the gate oxide charge Qg of the device. The gate-oxide charges Qg include gate-source charges Qgs and gate-drain charges Qgd, and when the power MOSFET is switched between an on state and an off state, the voltage change of the gate-drain charges Qgd is much larger than that of the gate-source charges Qgs, so that the gate-drain charges Qgd have a large influence on switching loss.
For power MOSFET devices operating at high frequencies, there is a need to pay more attention to how to reduce the gate-drain charge Qgd to improve the switching characteristics of the device. In general, in order to reduce the switching loss of the device in a high-frequency operating environment, the gate-drain charge Qgd needs to be reduced, but the characteristic on-resistance Rsp of the device is also increased, that is, the on-loss is increased. Therefore, it is very important to reduce the gate-drain charge Qgd without losing the on-resistance and current capability, which is also a current problem.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a low-grid-leakage-charge trench type power semiconductor device and a preparation method thereof, which can effectively increase the width of a table board at the bottom of a cell trench and reduce the effective area of parasitic capacitance, thereby reducing grid leakage charge Qgd, and are compatible with the prior art, safe and reliable.
According to the technical scheme provided by the invention, the low-grid-leakage-charge trench type power semiconductor device comprises an active region positioned on a semiconductor substrate and a terminal protection region positioned on the outer ring of the active region on the top plane of the semiconductor device; in the cross section of the semiconductor device, the semiconductor substrate is provided with a first main surface and a second main surface corresponding to the first main surface, a first conductive type substrate and a first conductive type epitaxial layer adjacent to the first conductive type substrate are arranged between the first main surface and the second main surface, and a second conductive type well layer is arranged at the upper part in the first conductive type epitaxial layer; the active area comprises a plurality of active cells, and the active cells adopt a groove structure;
the active unit cell comprises a unit cell groove, the unit cell groove is positioned in the second conduction type well layer, and the bottom of the unit cell groove is positioned in the first conduction type epitaxial layer below the second conduction type well layer; arranging a trench gate structure in the cell trench, wherein the trench gate structure comprises a trench gate insulating oxide layer and gate conductive polycrystalline silicon filled in the cell trench, and the gate conductive polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell trench through the trench gate insulating oxide layer;
the trench gate insulating oxide layer comprises a bottom insulating gate oxide layer and an upper insulating gate oxide layer connected with the bottom insulating gate oxide layer, the bottom insulating gate oxide layer covers the bottom wall of the cell trench, and the upper insulating gate oxide layer covers the rest side walls of the cell trench; the upper end part of the bottom insulating gate oxide layer is positioned below the second conduction type well layer, and the thickness of the bottom insulating gate oxide layer is larger than that of the upper insulating gate oxide layer.
Arranging an insulating medium layer at the notch of the cell groove, wherein the insulating medium layer covers the notch of the cell groove and supports the first main surface, and arranging a source metal layer on the insulating medium layer, wherein the source metal layer is in ohmic contact with the second conductive type well layer and the first conductive type source region in the second conductive type well layer; in the second conductive type well layer, the first conductive type source region is in contact with the upper side wall outside the cell groove.
The upper insulating gate oxide layer and the bottom insulating gate oxide layer are formed in the same process step, when the upper insulating gate oxide layer is prepared through a thermal oxidation process of a furnace tube, the bottom insulating gate oxide layer can be formed through an amorphous region at the bottom of a cell groove, and the thickness of the bottom insulating gate oxide layer is 1.4 times that of the upper insulating gate oxide layer.
The amorphization region is formed by implanting high-concentration hydrogen ions into the position of the bottom of the cell groove, and the concentration of the implanted hydrogen ions is 4e 16; the height of the non-crystallization area is 1.4 times of the thickness of the upper insulation gate oxide layer.
And arranging a drain metal layer on the second main surface of the semiconductor substrate, wherein the drain metal layer is in ohmic contact with the first conduction type substrate.
A preparation method of a low grid leakage charge groove type power semiconductor device is characterized by comprising the following steps:
and 11, preparing a drain metal layer on the second main surface, wherein the drain metal layer is in ohmic contact with the first conductive type substrate.
The material of the semiconductor substrate comprises silicon.
In step 3, the concentration of implanted hydrogen ions is 4e 16; the height of the non-crystallization area is 1.4 times of the thickness of the upper insulation gate oxide layer.
In step 5, during thermal oxidation, thermal oxidation is performed through a high-temperature furnace tube process.
The insulating dielectric layer comprises a silicon dioxide layer.
In both the "first conductivity type" and the "second conductivity type", for an N-type power semiconductor device, the first conductivity type refers to an N-type, and the second conductivity type is a P-type; for a P-type power semiconductor device, the first conductivity type and the second conductivity type refer to the opposite type of the N-type semiconductor device.
The invention has the advantages that: the method is characterized in that an amorphization area is arranged right below the bottom of a cell groove, the amorphization area bombards crystal grain monocrystalline silicon with the same crystal face orientation at the bottom of the cell groove into an amorphization state with different crystal face orientations by controlling a hydrogen injection method, and crystal materials of the crystal grain monocrystalline silicon undergo amorphization transformation due to too large crystal lattice damage density, so that after the crystal grains grow through a thermal oxidation furnace tube process, a bottom insulating gate oxide layer can be formed through the amorphization area, the thickness of the bottom insulating gate oxide layer is 1.4 times of that of an upper insulating gate oxide layer, the thickness of the insulating gate oxide layer covering the bottom of the cell groove can be increased, the width of a table top at the bottom of the cell groove is effectively increased, the effective area of parasitic capacitance is reduced, the gate leakage charge Qgd is reduced, and the method is compatible with.
Drawings
FIG. 1 is a schematic structural diagram of the present invention.
FIGS. 2-8 are cross-sectional views of process steps for practicing the present invention, wherein
FIG. 2 is a schematic diagram of a cell trench prepared according to the present invention.
FIG. 3 is a schematic diagram of an amorphized region produced according to the present invention.
FIG. 4 is a schematic diagram of the cell trench after being etched according to the present invention.
Fig. 5 is a schematic diagram of the invention after an insulating gate oxide layer is prepared.
Fig. 6 is a schematic diagram of an insulating dielectric layer prepared according to the present invention.
Fig. 7 is a schematic diagram of a source metal layer prepared according to the present invention.
Fig. 8 is a schematic diagram of a drain metal layer prepared according to the present invention.
Description of reference numerals: the structure comprises a 1-drain metal layer, a 2-N type substrate, a 3-N type epitaxial layer, a 4-upper insulating gate oxide layer, a 5-gate conductive polycrystalline silicon, a 6-P well layer, a 7-N + source region, an 8-insulating dielectric layer, a 9-source metal layer, a 10-non-crystallization region, an 11-cellular trench, a 12-mask layer, a 13-surface insulating oxide layer and a 14-bottom insulating gate oxide layer.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1 and 8: in order to reduce the gate-drain charge Qgd, taking an N-type power semiconductor device as an example, the invention comprises an active region located on a semiconductor substrate and a terminal protection region located at the outer ring of the active region on a top plane of the semiconductor device; in the cross section of the semiconductor device, the semiconductor substrate has a first main surface and a second main surface corresponding to the first main surface, an N-type substrate 2 and an N-type epitaxial layer 3 adjacent to the N-type substrate 2 are arranged between the first main surface and the second main surface, and a P-well layer 6 is arranged on the upper part in the N-type epitaxial layer 3; the active area comprises a plurality of active cells, and the active cells adopt a groove structure;
the active unit cell comprises a unit cell groove 11, wherein the unit cell groove 11 is positioned in the P well layer 6, and the bottom of the unit cell groove 11 is positioned in the N-type epitaxial layer 3 below the P well layer 6; a trench gate structure is arranged in the cell trench 11, the trench gate structure comprises a trench gate insulating oxide layer and gate conductive polysilicon 5 filled in the cell trench 11, and the gate conductive polysilicon 5 is insulated and isolated from the side wall and the bottom wall of the cell trench 11 through the trench gate insulating oxide layer;
the trench gate insulating oxide layer comprises a bottom insulating gate oxide layer 14 and an upper insulating gate oxide layer 4 connected with the bottom insulating gate oxide layer 14, the bottom insulating gate oxide layer 14 covers the bottom wall of the cell trench 11, and the upper insulating gate oxide layer 4 covers the rest side walls of the cell trench 11; the upper end part of the bottom insulating gate oxide layer 14 is positioned below the P well layer 6, and the thickness of the bottom insulating gate oxide layer 11 is larger than that of the upper insulating gate oxide layer 4.
Specifically, the active region is located in a central region of the semiconductor substrate, the terminal protection region surrounds the active region, the active region is used for forming a functional region of the power semiconductor device, the terminal protection region is used for protecting the active region, active cells in the active region adopt a trench structure, the active cells in the active region are connected in parallel to form a whole, and a matching relationship between the active region and the terminal protection region is well known to those skilled in the art and is not described herein again. The semiconductor substrate may be made of a material commonly used in the art, such as silicon, a first main surface is generally a front surface of the semiconductor substrate, a second main surface is generally a back surface of the semiconductor substrate, an N-type substrate 2 and an N-type epitaxial layer 3 are disposed between the first main surface and the second main surface, a thickness of the N-type epitaxial layer 3 is generally greater than a thickness of the N-type substrate 2, the N-type epitaxial layer 3 and the N-type substrate 2 are adjacent to each other, and a specific matching relationship between the N-type substrate 2 and the N-type epitaxial layer 3 is consistent with a conventional relationship, which is well known to those skilled in the art and will not be described herein again.
Typically, the back surface of the N-type substrate 2 forms the second main surface, the front surface of the N-type epitaxial layer 3 forms the first main surface, the P-well layer 6 is located within the N-type epitaxial layer 3, the depth of the P-well layer 6 is less than the thickness of the N-type epitaxial layer 3, and the P-well layer 6 extends generally vertically downward from the first main surface. In the embodiment of the present invention, the active cell adopts a trench structure, the cell trench 11 is located in the P-well layer 6, the bottom of the cell trench 11 is located in the N-type epitaxial layer 3, and generally, the notch of the cell trench 11 is located on the first main surface. The cell trench 11 is provided with a trench gate structure, and the specific form of the trench gate structure may be selected according to actual needs, and is specifically known to those skilled in the art, and will not be described herein again.
In the embodiment of the invention, the trench gate structure comprises a trench gate insulating oxide layer and a gate conductive polysilicon 5 filled in the cell trench 11, and the gate conductive polysilicon 5 is insulated and isolated from the side wall and the bottom wall of the cell trench 11 through the trench gate insulating oxide layer. In specific implementation, the bottom insulating gate oxide layer 14 covers the side wall and the bottom wall of the lower part of the cell trench 11, and the upper insulating gate oxide layer 4 covers the rest side walls of the cell trench 11; the lower end part of the upper insulating gate oxide layer 4 is connected with the upper end part of the bottom insulating gate oxide layer 14, the upper end part of the bottom insulating gate oxide layer 14 is positioned below the P well layer 7, and the thickness of the bottom insulating gate oxide layer 14 is larger than that of the upper insulating gate oxide layer 4.
Further, an insulating medium layer 8 is arranged at a notch of the cell trench 11, the insulating medium layer 8 covers the notch of the cell trench 11 and supports the first main surface, a source metal layer 9 is arranged on the insulating medium layer 8, and the source metal layer 9 is in ohmic contact with the P-well layer 7 and the N + source region 7 located in the P-well layer 7; in the P-well layer 7, the N + source region 7 is in contact with the upper sidewall outside the cell trench 11.
In the embodiment of the invention, the bottom insulating gate oxide layer 14 and the upper insulating gate oxide layer 4 are silicon dioxide layer walls. The gate conductive polysilicon 5 is filled in the cell trench 11, the gate conductive polysilicon 5 is generally smaller than the depth of the cell trench 11, and the active cells in the active region are connected with each other through the gate conductive polysilicon 5 in the cell trench 11 into a whole, which is specifically consistent with the prior art, specifically well known by those skilled in the art, and will not be described herein again.
In specific implementation, the insulating dielectric layer 8 is disposed at the notch of the cell trench 11, the insulating dielectric layer 8 may be a silicon dioxide layer, and of course, the insulating dielectric layer 8 also covers the first main surface. The source metal layer 9 is disposed on the insulating dielectric layer 8, the source metal layer 9 may specifically be made of a conventional metal material, and the source metal layer 9 is in ohmic contact with the P-well layer 6 and the N + source region 7, that is, a source electrode of the power semiconductor device can be formed through the source metal layer 9. The manner of forming the gate electrode using the gate conductive polysilicon 5 is consistent with the prior art, and is well known to those skilled in the art, and will not be described herein. The positions and corresponding connection relationships between the P-well layer 6 and the N + source region 7 and between the cell trenches 11 are the same as those in the prior art, and are well known to those skilled in the art, and are not described herein again.
Furthermore, a drain metal layer 1 is provided on the second main surface of the semiconductor substrate, and the drain metal layer 1 is in ohmic contact with the N-type substrate 2. The drain electrode of the power semiconductor device can be formed through the drain metal layer 1, which is specifically consistent with the prior art and is well known to those skilled in the art, and will not be described herein again.
Further, the upper insulating gate oxide layer 4 and the bottom insulating gate oxide layer 14 are formed in the same process step, when the upper insulating gate oxide layer 4 is prepared through a thermal oxidation process of a furnace tube, the bottom insulating gate oxide layer 14 can be formed through the non-crystallization area 10 at the bottom of the cell groove 11, and the thickness of the bottom insulating gate oxide layer 14 is 1.4 times that of the upper insulating gate oxide layer 4.
In the embodiment of the present invention, the amorphized region 10 is formed by implanting high concentration hydrogen ions into the bottom of the cell trench 11, where the concentration of the implanted hydrogen ions is 4e 16; the height of the amorphized region 10 is 1.4 times the thickness of the upper insulating gate oxide layer 4. In specific implementation, when hydrogen ions are implanted, the specific concentration may also be selected according to actual needs, and generally, the implantation of high-concentration hydrogen ions with a concentration exceeding 1.0E16cm-3 orders of magnitude is all possible, and is not described herein again.
In the embodiment of the present invention, when high-concentration hydrogen ions are implanted into the bottom of the cell trench 11, the region of the implanted N-type epitaxial layer 3 can be amorphized. The bottom insulation gate oxide layer 14 can be formed through the non-crystallization area 10, so that the thickness of the bottom insulation gate oxide layer of the cellular trench 11 is increased, the gate leakage charge Qgd between the gate end and the drain end can be reduced, and the purposes of improving the switching speed of the power semiconductor device and reducing the switching loss are achieved.
As shown in fig. 2 to 8, the trench type power semiconductor device may be prepared by the following process steps, specifically, the preparation method includes the following steps:
specifically, the semiconductor substrate may be silicon, but of course, other commonly used semiconductor materials may also be used, and the type of the specific material may be selected according to actual needs. For the specific relationship between the first main surface and the second main surface and the N-type substrate 2 and the N-type epitaxial layer 3, reference may be made to the above description, and details are not described here.
specifically, the mask layer 12 may adopt a conventional form, and specifically, a process of disposing the mask layer 12 on the first main surface is the same as that in the related art, which is well known to those skilled in the art and will not be described herein again. The mask layer 12 covers the first main surface, and by means of a technique commonly used in the art, the mask layer 12 can be selectively masked and etched to obtain a plurality of windows penetrating through the mask layer 12, and the windows are used to perform trench etching on the first main surface, so that the desired cell trench 11 can be prepared, as shown in fig. 2. The specific processes of etching the mask layer 12 and obtaining the cell trench 11 by etching are the same as those in the prior art, and are well known to those skilled in the art, and will not be described herein again.
specifically, when hydrogen ions are implanted, the mask layer 12 is used as a mask, so that the hydrogen ions are only implanted into the entire bottom of the cell trench 11, and the rest of the positions are not implanted with hydrogen ions. The concentration of the implanted hydrogen ions is 4e16, and the concentration of the implanted hydrogen ions is determined to enable the silicon material in the implanted region to be in an amorphous state, which is well known in the art and will not be described herein again. After hydrogen ions are implanted, the hydrogen ions are accelerated to enter silicon by an electric field, the high-speed hydrogen ions enter the silicon and collide with crystal grains with the same orientation, and an amorphization region 10 with different crystal plane orientations is formed right below the bottom of the cellular trench 11 by the bombardment effect in the morning, as shown in fig. 3. The height of the amorphized region 10 can be controlled by controlling the accelerating voltage, etc., and the height of the amorphized region 10 is generally 1.4 times the thickness of the insulating gate oxide 4 covering the side wall of the cell trench 11.
specifically, the mask layer 12 is removed by a common technical means in the technical field, the cell trench 11 is etched after the mask layer 12 is removed, specifically, an etching process common in the technical field can be adopted, the etching time can be 10 s-30 s, and after the cell trench 11 is etched, the bottom of the cell trench 11 can be more smooth, as shown in fig. 4. When the bottom of the cellular trench 11 is smooth, the concentration of the electric field at the tip can be avoided.
specifically, when a thermal oxidation process is adopted, a high-temperature furnace tube is adopted, the temperature of high-temperature thermal oxidation can be 1000 ℃, and the specific temperature can be selected according to actual needs. After thermal oxidation, an insulating gate oxide layer 4 can be prepared on the side wall of the cell trench 11, and a surface insulating oxide layer 13 can be formed on the first main surface; a bottom insulating gate oxide layer 14 can be prepared at the bottom of the cell trench 11 by using the amorphized region 10. During thermal oxidation, the crystal plane orientation is different due to the impact of high-speed hydrogen ions on the bottom of the cell trench 11, so that the thickness of the bottom insulating gate oxide 14 at the bottom of the cell trench 11 is 1.4 times the thickness of the upper insulating gate oxide 4 covering the sidewall of the cell trench 11, as shown in fig. 5.
specifically, the cell trench 11 can be filled with the gate conductive polysilicon 5 by a common technical means in the technical field, and the gate conductive polysilicon 5 is located below the notch of the cell trench 11.
specifically, P-type impurity ion implantation is performed by a technical means commonly used in the technical field, so that a P-well layer 6 can be obtained in the N-type epitaxial layer 3, and the P-well layer 6 is located at the upper part in the N-type epitaxial layer 3 and above the bottom of the cell trench 11. After the P-well layer 6 is obtained, the N + source region 7 can be obtained by injecting N-type impurity ions, the N + source region 7 contacts with the sidewall above the outside of the adjacent cell trench 11, and the process and process conditions for specifically preparing the P-well layer 6 and the N + source region 7 are consistent with those of the prior art, which are well known to those skilled in the art and are not described herein again.
specifically, the insulating dielectric layer 8 can be prepared by a technical means commonly used in the technical field, and the insulating dielectric layer 8 covers the first main surface, so that the notches of the cell trenches 11 can be covered by the insulating dielectric layer 8, as shown in fig. 6.
specifically, by adopting a technical means commonly used in the technical field, the contact hole etching can be performed on the insulating dielectric layer 8 so as to prepare a required source contact hole, and the source contact hole penetrates through the insulating dielectric layer 8.
specifically, a metal layer can be prepared by a common technical means in the technical field, and the metal layer covers the insulating medium layer 8. The prepared metal layer generally comprises a source metal layer 9, and of course, the prepared metal layer can also comprise a gate metal layer, and the source metal layer is insulated and isolated from the gate metal layer. The prepared source metal layer 9 covers the insulating dielectric layer 8 and can be filled in the source contact hole, and the source metal layer 9 filled in the source contact hole is in ohmic contact with the P-well layer 6 and the N + source region 7, as shown in fig. 7.
And 11, preparing a drain metal layer 1 on the second main surface, wherein the drain metal layer 1 is in ohmic contact with the N-type substrate 2.
Specifically, the drain metal layer 1 can be prepared by a conventional technical means in the field, the drain metal layer 1 is in ohmic contact with the N-type substrate 2, and a drain electrode can be formed through the drain metal layer 1, which is specifically consistent with the prior art and is well known in the field, and is not described herein again.
In summary, the amorphization region 10 is arranged right below the bottom of the cell trench 11, the amorphization region 10 bombards the crystal grain monocrystalline silicon with the same crystal face orientation at the bottom of the cell trench 11 into an amorphization state with different crystal face orientations by controlling a hydrogen injection method, and the crystal material of the amorphization region undergoes amorphization transformation due to too large crystal lattice damage density, so that after the crystal material grows by a thermal oxidation furnace tube process, a bottom insulating gate oxide layer 14 with a larger thickness can be formed, thereby the thickness of the insulating gate oxide layer covering the bottom of the cell trench 11 can be increased, the mesa width at the bottom of the cell trench is effectively increased, the effective area of parasitic capacitance is reduced, and the gate leakage charge Qgd is reduced, and the process is compatible with the prior art.
Claims (10)
1. A trench type power semiconductor device with low grid leakage charge comprises an active region located on a semiconductor substrate and a terminal protection region located on the outer ring of the active region, wherein the terminal protection region is located on the upper plane of the semiconductor device; in the cross section of the semiconductor device, the semiconductor substrate is provided with a first main surface and a second main surface corresponding to the first main surface, a first conductive type substrate and a first conductive type epitaxial layer adjacent to the first conductive type substrate are arranged between the first main surface and the second main surface, and a second conductive type well layer is arranged at the upper part in the first conductive type epitaxial layer; the active area comprises a plurality of active cells, and the active cells adopt a groove structure; the method is characterized in that:
the active unit cell comprises a unit cell groove, the unit cell groove is positioned in the second conduction type well layer, and the bottom of the unit cell groove is positioned in the first conduction type epitaxial layer below the second conduction type well layer; arranging a trench gate structure in the cell trench, wherein the trench gate structure comprises a trench gate insulating oxide layer and gate conductive polycrystalline silicon filled in the cell trench, and the gate conductive polycrystalline silicon is insulated and isolated from the side wall and the bottom wall of the cell trench through the trench gate insulating oxide layer;
the trench gate insulating oxide layer comprises a bottom insulating gate oxide layer and an upper insulating gate oxide layer connected with the bottom insulating gate oxide layer, the bottom insulating gate oxide layer covers the bottom wall of the cell trench, and the upper insulating gate oxide layer covers the rest side walls of the cell trench; the upper end part of the bottom insulating gate oxide layer is positioned below the second conduction type well layer, and the thickness of the bottom insulating gate oxide layer is larger than that of the upper insulating gate oxide layer.
2. The low gate-drain charge trench power semiconductor device of claim 1, wherein: arranging an insulating medium layer at the notch of the cell groove, wherein the insulating medium layer covers the notch of the cell groove and supports the first main surface, and arranging a source metal layer on the insulating medium layer, wherein the source metal layer is in ohmic contact with the second conductive type well layer and the first conductive type source region in the second conductive type well layer; in the second conductive type well layer, the first conductive type source region is in contact with the upper side wall outside the cell groove.
3. The low gate-drain charge trench power semiconductor device of claim 1 or 2, wherein: the upper insulating gate oxide layer and the bottom insulating gate oxide layer are formed in the same process step, when the upper insulating gate oxide layer is prepared through a thermal oxidation process of a furnace tube, the bottom insulating gate oxide layer can be formed through an amorphous region at the bottom of a cell groove, and the thickness of the bottom insulating gate oxide layer is 1.4 times that of the upper insulating gate oxide layer.
4. The low gate-drain charge trench power semiconductor device of claim 3, wherein: the amorphization region is formed by implanting high-concentration hydrogen ions into the position of the bottom of the cell groove, and the concentration of the implanted hydrogen ions is 4e 16; the height of the non-crystallization area is 1.4 times of the thickness of the upper insulation gate oxide layer.
5. The low gate-drain charge trench power semiconductor device of claim 1 or 2, wherein: and arranging a drain metal layer on the second main surface of the semiconductor substrate, wherein the drain metal layer is in ohmic contact with the first conduction type substrate.
6. A preparation method of a low grid leakage charge groove type power semiconductor device is characterized by comprising the following steps:
step 1, providing a semiconductor substrate with two opposite main surfaces, wherein the two opposite main surfaces comprise a first main surface and a second main surface corresponding to the first main surface, and a first conductive type substrate and a first conductive type epitaxial layer adjacent to the first conductive type substrate are arranged between the first main surface and the second main surface;
step 2, a mask layer is arranged on the first main surface and covers the first main surface; selectively masking and etching the mask layer, and performing groove etching on the first conductive type epitaxial layer by using the etched mask layer so as to prepare a plurality of required cell grooves;
step 3, injecting hydrogen ions above the first main surface, and preparing non-crystallization areas with different crystal orientation directions under the bottom of the cellular groove by utilizing the shielding of a mask layer, wherein the non-crystallization areas cover the bottom of the cellular groove;
step 4, removing the mask layer, and performing groove etching on the cellular groove to enable the groove bottom of the cellular groove to be smooth;
step 5, performing a required thermal oxidation process on the first main surface to obtain an upper insulating gate oxide layer covering the side wall of the cellular trench, and forming a bottom insulating gate oxide layer covering the bottom wall of the cellular trench through the non-crystallization area, wherein the upper end of the bottom insulating gate oxide layer is connected with the lower end of the upper insulating gate oxide layer;
step 6, filling the cell grooves to obtain grid conductive polycrystalline silicon, wherein the grid conductive polycrystalline silicon is insulated and isolated from the side walls and the bottom walls of the cell grooves through insulating grid oxide layers;
step 7, performing ion implantation on the first main surface to obtain a second conduction type well layer in the first conduction type epitaxial layer, wherein the second conduction type well layer is positioned above the bottom of the cell groove, a first conduction type source region can be prepared in the second conduction type well layer, and the first conduction type source region is contacted with the side wall of the adjacent cell groove;
step 8, depositing on the first main surface to obtain an insulating medium layer, wherein the insulating medium layer covers the first main surface and covers the notch of the cellular groove;
step 9, preparing a required source electrode contact hole, wherein the source electrode contact hole penetrates through the insulating medium layer;
step 10, arranging a metal layer on the insulating medium layer, wherein the metal layer comprises a source electrode metal layer, the source electrode metal layer covers the insulating medium layer and can be filled in the source electrode contact hole, and the source electrode metal layer filled in the source electrode contact hole is in ohmic contact with the second conductive type well layer and the first conductive type source region;
and 11, preparing a drain metal layer on the second main surface, wherein the drain metal layer is in ohmic contact with the first conductive type substrate.
7. The method for manufacturing a low gate-to-drain charge trench power semiconductor device as claimed in claim 6, wherein the material of said semiconductor substrate comprises silicon.
8. The method for manufacturing a low gate-to-drain charge trench power semiconductor device as claimed in claim 6, wherein in step 3, the concentration of implanted hydrogen ions is 4e 16; the height of the non-crystallization area is 1.4 times of the thickness of the upper insulation gate oxide layer.
9. The method for manufacturing a low gate-to-drain charge trench power semiconductor device as claimed in claim 6, wherein in step 5, the thermal oxidation is performed by a high temperature furnace process during the thermal oxidation.
10. The method of claim 6 wherein the dielectric layer comprises a silicon dioxide layer.
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