CN118380475A - Silicon carbide MOSFET power device and preparation method thereof - Google Patents
Silicon carbide MOSFET power device and preparation method thereof Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 72
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 13
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000009616 inductively coupled plasma Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910001069 Ti alloy Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000009828 non-uniform distribution Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000009827 uniform distribution Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 238000010009 beating Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention discloses a silicon carbide MOSFET power device and a preparation method thereof, wherein the silicon carbide MOSFET power device comprises a drain electrode, and a substrate, an epitaxial layer well region and a source region are sequentially arranged on the surface of the drain electrode; a gate groove is arranged on the epitaxial layer, the well region and the source region, the gate groove comprises a first groove and a second groove, and a dielectric layer and a gate electrode are coaxially arranged in the gate groove; the dielectric layer comprises a first dielectric layer and a second dielectric layer, and the thickness of the first dielectric layer is larger than that of the second dielectric layer; the surface of the grid electrode, the dielectric layer and the source region is provided with an isolation dielectric layer, and the surface of the first conduction type source region is also provided with a source electrode. The invention does not damage the crystal structure of the SiC epitaxial layer, obviously improves the electrical property of the device and can accurately control the thickness of the gate dielectric; and by utilizing different oxidation rates of various crystal faces of the SiC material, a thickened first dielectric layer is formed at the bottom corner of the groove, so that the breakdown resistance is remarkably improved, and the failure risk is greatly reduced.
Description
Technical Field
The invention relates to a power device and a manufacturing method thereof, in particular to a silicon carbide MOSFET power device and a manufacturing method thereof.
Background
The development of power electronics systems has placed higher demands on the performance of semiconductor devices, in particular in the areas of high temperature, high frequency, radiation resistance, high voltage, etc. As a representative of the third generation semiconductor material, siC has a larger forbidden bandwidth, a higher electron saturation drift velocity, a stronger irradiation resistance, a higher breakdown electric field and a higher thermal conductivity, so that it has a wide application prospect in the fields of power electronic equipment, aerospace systems, high-speed rail traction equipment, military electronic communication systems and the like.
Compared with a planar gate type SiC MOSFET device, the trench type SiC MOSFET device has the advantages that the channel mobility is improved, the JFET effect is eliminated, the on-resistance of the device is obviously reduced, the cell size is reduced, and the power density is increased by forming the channel on the side wall of the trench.
But the gate oxide quality of trench SiC MOSFET devices has been a key factor limiting commercial production. The characteristic that each crystal face of the SiC material has different oxidation rates enables the thickness of the gate oxide layer on the side wall of the groove to be 3-4 times that of the gate oxide layer on the bottom of the groove, and in the off state, the curvature effect enables the thinner gate oxide layer on the bottom corner of the groove to bear higher electric field intensity, so that destructive failure is caused.
At present, the gate dielectric materials of the SiC MOSFET devices which can be commercially produced are SiO 2, and one of the methods for solving the problem that the gate dielectric bears an excessively high electric field is to thicken the gate dielectric so as to improve the breakdown resistance of the SiO 2 layer. The existing method for thickening the gate dielectric layer comprises the steps of beating SiC in a gate dielectric region into an amorphous state through heavy-dose ion implantation, forming a thickened gate dielectric by utilizing the characteristic of higher oxidation rate of the amorphous SiC, depositing polysilicon at the bottom of a groove, and forming the thickened gate dielectric layer through a thermal oxidation process. However, the former can damage the crystal structure of the SiC epitaxial layer near the gate dielectric, and damage the electrical performance of the device; the latter cannot accurately control the gate dielectric thickness because it is difficult to control the oxidation rate of polysilicon.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention aims to provide the silicon carbide MOSFET power device with remarkably improved breakdown resistance and reduced failure risk, and the invention also aims to provide a preparation method of the silicon carbide MOSFET power device which is simple and convenient and can be produced in a high-performance batch manner.
The technical scheme is as follows: the silicon carbide MOSFET power device comprises a drain electrode, wherein a substrate, an epitaxial layer, a well region and a source region are sequentially arranged on the surface of the drain electrode; a gate groove is arranged on the epitaxial layer, the well region and the source region, the gate groove comprises a first groove and a second groove, the diameter of the first groove is larger than that of the second groove, and a coaxial dielectric layer and a gate electrode are arranged in the gate groove; the dielectric layer comprises a first dielectric layer arranged in the first groove and a second dielectric layer arranged in the second groove, and the thickness of the first dielectric layer is larger than that of the second dielectric layer; the surface of the grid electrode, the dielectric layer and the source region is provided with an isolation dielectric layer, and the surface of the source region is also provided with a source electrode.
Further, the diameter of the first groove is 0.1-0.5 mu m larger than that of the second groove, and the design can utilize the characteristic that each crystal face of the SiC material has different oxidation rates, so that a thickened first dielectric layer is formed at the bottom corner of the groove. The depth-to-width ratio of the first groove is less than or equal to 2:1, and the side wall angle is more than or equal to 80 degrees. The depth-to-width ratio of the second groove is more than or equal to 1.5:1, and the side wall angle is more than or equal to 80 degrees.
Further, a distance between adjacent first grooves is not less than 1 [ mu ] m. The width of the first groove is 0.7-2 mu m, and the depth is 0.2-1.0 mu m; the width of the second groove is 0.5-1.8 mu m, and the depth is 0.5-2.0 mu m.
Further, the dielectric layer further comprises a third dielectric layer, and the third dielectric layer is arranged at the center of the bottom of the gate groove and has a thickness of 40-150 nm. The dielectric layer is made of silicon dioxide material.
Further, the substrate is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the substrate is 10-1000 mu m, the doping concentration is 1e18cm -3~5e19cm-3, and the doping elements are N, P and other elements.
Further, the epitaxial layer is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the epitaxial layer is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3.
Further, the substrate, the epitaxial layer, the well region and the source region are all of N type or P type.
Further, the depth of the well region is 0.5-1.0 mu m, the doping distribution of the well region can be uniform distribution or non-uniform distribution, and the average doping concentration is 5e16cm -3~5e17cm-3.
Further, the isolation medium layer is made of silicon nitride material and has a thickness of 0.5-10 mu m so as to form a source window. Evaporating metal through the source window, wherein the metal is Ti/Al alloy, and then annealing at 300-1100 ℃ to form source ohmic contact. And forming a drain ohmic contact on the bottom layer of the substrate, forming a source electrode on the surface of the source ohmic contact, and forming a drain electrode on the surface of the drain ohmic contact layer.
The invention relates to a preparation method for a silicon carbide MOSFET power device, which comprises the following steps:
sequentially growing an epitaxial layer, a well region and a source region on a substrate;
Performing inductively coupled plasma etching on the epitaxial layer to remove part of the epitaxial layer and form grooves penetrating through the well region and the source region;
Performing isotropic etching on the bottom of the groove, and performing high-temperature annealing passivation at 1400-1800 ℃ to form a gate groove;
Forming a first dielectric layer at two bottom corners of the gate trench, forming a second dielectric layer at the side wall of the gate trench, and performing high-temperature annealing at 900-1300 ℃;
And fifthly, forming a gate electrode in the dielectric layer, forming an isolation dielectric layer and a source electrode on the surfaces of the gate electrode and the source region, and forming a drain electrode on the substrate.
In order to further improve the breakdown resistance of the gate dielectric layer, the fourth step is replaced by: and forming a substitute layer at the center of the bottom of the gate trench, forming a first dielectric layer at two bottom corners of the gate trench, forming a second dielectric layer at the side wall of the gate trench, and performing high-temperature annealing at 900-1300 ℃ to form a third dielectric layer by thermal oxidation of the substitute layer.
Further, in the first step, the well region and the source region are formed by adopting an ion implantation method, and the specific steps include: preparing a patterned mask layer on the surface of the epitaxial layer, then injecting impurities of the first conductivity type or the second conductivity type, removing the mask, and annealing at the temperature of 1400-2200 ℃ for 2-30 min.
Further, in the third step, the gas used for high-temperature annealing passivation is one or more of SiH 4、H2 and Ar.
Further, in the fourth step, the high-temperature annealing gas is one or more of NO and N 2O、H2、NH3.
In the fifth step, the gate electrode is polysilicon, amorphous silicon or amorphous silicon, and the impurity is Al, N, P or B. The method of forming the gate electrode is atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, or sputtering.
Working principle: in the off state, the breakdown resistance of the thickened first dielectric layer is greatly enhanced, the risk that the breakdown voltage of the device cannot reach the expected value due to early breakdown of the gate dielectric is avoided, and the reliability of the device is effectively improved.
The beneficial effects are that: compared with the prior art, the invention has the following remarkable characteristics:
1. the crystal structure of the SiC epitaxial layer is not damaged, the electrical property of the device is obviously improved, and the thickness of the gate dielectric can be accurately controlled;
2. The first groove and the second groove which are communicated form a gate groove, a first dielectric layer at the bottom corner of the gate groove and a second dielectric layer at the side wall of the second groove are formed through thermal oxidation, and a thickened first dielectric layer is formed at the bottom corner of the groove by utilizing the characteristic that each crystal face of a SiC material has different oxidation rates, so that the breakdown resistance of the bottom corner dielectric layer is remarkably improved, and the failure risk of a device is greatly reduced;
3. The preparation method is compatible with the existing manufacturing process of the SiC trench gate type MOSFET power device, only one-step isotropic etching process is added, and compared with the existing improved structure, the preparation method obviously reduces the process complexity and can be used for realizing the batch production of the high-performance trench gate type silicon carbide MOSFET device.
Drawings
FIG. 1 is a flow chart of the preparation of example 1 of the present invention;
FIG. 2 is a schematic view showing the structure of a substrate 2 according to embodiment 1 of the present invention;
FIG. 3 is a schematic structural diagram of the product obtained in step S1 of example 1 of the present invention;
FIG. 4 is a schematic structural diagram of the product obtained in step S2 of example 1 of the present invention;
FIG. 5 is a schematic structural diagram of the product obtained in step S3 of example 1 of the present invention;
FIG. 6 is a schematic structural diagram of the product obtained in step S4 of example 1 of the present invention;
FIG. 7 is a schematic structural diagram of the product obtained in step S5 of example 1 of the present invention;
FIG. 8 is a schematic structural diagram of the product obtained in step S6 of example 1 of the present invention;
FIG. 9 is a flow chart of the preparation of example 2 of the present invention;
Fig. 10 is a schematic view of the structure of a substrate 2 according to embodiment 2 of the present invention;
FIG. 11 is a schematic structural diagram of the product obtained in step S1 of the present invention;
FIG. 12 is a schematic structural diagram of the product obtained in step S2 of example 2 of the present invention;
FIG. 13 is a schematic structural diagram of the product obtained in step S3 of example 2 of the present invention;
FIG. 14 is a schematic structural diagram of the product obtained in step S4 of example 2 of the present invention;
FIG. 15 is a schematic structural diagram of the product obtained in step S5 of example 2 of the present invention;
FIG. 16 is a schematic structural diagram of the product obtained in step S6 of example 2 of the present invention;
FIG. 17 is a schematic diagram showing the structure of the product obtained in step S7 of example 2 of the present invention.
Detailed Description
The experimental methods described in the examples, unless otherwise specified, are all conventional; reagents and materials, unless otherwise specified, are commercially available.
Example 1
Referring to fig. 1, a method for manufacturing a silicon carbide MOSFET power device includes the steps of:
S1, as shown in fig. 2-3, an epitaxial layer 3 is formed on a substrate 2 through epitaxial growth, the thickness of the silicon carbide epitaxial layer 3 is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3. The substrate 2 is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC material, the thickness is 10-1000 mu m, the doping concentration is 1e18cm -3~5e19cm-3, and the doping elements are N, P and the like. The epitaxial layer is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the epitaxial layer 3 is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3.
S2, as shown in FIG. 4, an ion implantation mask layer is formed on the surface of the epitaxial layer 3 through a chemical vapor deposition process, then a patterned etching mask layer is formed through a photoetching process, and the patterned ion implantation mask layer is utilized to carry out ion implantation on the epitaxial layer 3 so as to form a well region 6. The depth of the well region 6 is 0.5 mu m-1.0 mu m, the doping distribution can be uniform distribution or nonuniform distribution, and the average doping concentration is 5e16cm -3~5e17cm-3. After removing the mask, a source region 7 is formed in the same mode, the depth of the source region 7 is 0.1 mu m-0.5 mu m, and the doping concentration is 1e19cm -3~5e20cm-3. And after the injection is completed, annealing the prepared device for 2-30 min at the temperature of 1400-2200 ℃. The substrate 2, the epitaxial layer 3, the well region 6 and the source region 7 are all of N type or P type.
S3, as shown in FIG. 5, an etching mask layer is formed on the surface of the epitaxial layer 3 through chemical vapor deposition, then a patterned etching mask layer is formed through a photolithography process, the patterned etching mask layer is used for carrying out inductively coupled plasma etching on the epitaxial layer 3, part of the epitaxial layer 3 is removed, a second groove 402 penetrating through the well region 6 and the source region 7 is formed, and then the etching mask layer is removed. The width of the second groove 402 is 0.5-1.8 [ mu ] m, and the depth is 0.5 [ mu ] m-2.0 [ mu ] m. The depth of the second trench 402 is greater than the depth of the well region 6 by a difference of not less than 0.1 μm.
S4, as shown in FIG. 6, an etching mask layer is formed on the surface of the epitaxial layer 3 and the side wall and the bottom of the second trench 402 by chemical vapor deposition, then a patterned etching mask layer is formed by a photolithography process, and the bottom of the second trench 402 is isotropically etched by using the patterned etching mask layer, so as to form a first trench 401 communicated with the second trench 402. And then removing the etching mask layer, passivating the groove by a high-temperature annealing process, wherein the gas can be one or more of SiH 4、H2, ar and the like, and the annealing temperature is 1400-1800 ℃. The first trench 401 and the second trench 402 constitute a gate trench 4. The width of the first groove 401 is 0.7-2 mu m, the depth is 0.2-1.0 mu m, the width of the second groove 402 is 0.5-1.8 mu m, and the depth is 0.5-2.0 mu m. The width of the first grooves 401 is larger than the width of the second grooves 402, and the distance between adjacent first grooves 401 is not smaller than 1 [ mu ] m. The side wall angles of the first groove 401 and the second groove 402 are more than or equal to 80 degrees.
S5, as shown in FIG. 7, a first dielectric layer 501 is formed at two bottom corners of the gate trench 4 through a thermal oxidation process, a second dielectric layer 502 is formed at the side wall of the second trench 402, the quality of the dielectric layer 5 is improved through a high-temperature annealing process, the annealing gas can be one or more of NO, N 2O、H2、NH3 and other gases, and the annealing temperature is 900-1300 ℃. The thickness of the first dielectric layer 501 is 70nm to 200nm, and the thickness of the second dielectric layer 502 is 40nm to 100nm.
S6, as shown in FIG. 8, forming a gate electrode 8 through a chemical vapor deposition process, a photoetching process and an etching process, wherein polysilicon is selected as a material of the gate electrode 8, polysilicon injection is carried out, and the surface of the polysilicon is flattened through a CMP process. The patterned isolation medium layer 10 is formed through a chemical vapor deposition process, a photoetching process and an etching process, silicon nitride is selected as a material of the isolation medium layer 10, and the thickness is 0.5-10 mu m, so that a source electrode window is formed. Evaporating metal through the source window, wherein the metal is Ti/Al alloy, and then annealing at 300-1100 ℃ to form source ohmic contact. A drain ohmic contact is formed on the bottom layer of the substrate 2, a source electrode 9 is formed on the surface of the source ohmic contact, and a drain electrode 1 is formed on the surface of the drain ohmic contact.
The silicon carbide MOSFET power device obtained in this embodiment is sequentially, from bottom to top, a drain electrode 1, a substrate 2, an epitaxial layer 3, a well region 6, and a source region 7, and a gate trench 4 penetrates the well region 6 and the source region 7 and extends into the epitaxial layer 3. A first dielectric layer 501 is disposed in the first trench 401 of the gate trench 4, and a second dielectric layer 502 is disposed in the second trench 402. A gate electrode 8 is provided in the hollow inside the dielectric layer 5. The upper surfaces of the gate electrode 8, the second dielectric layer 502 and the source region 7 are flush. The isolation dielectric layer 10 covers the gate electrode 8, the surface of the second dielectric layer 502 and a part of the upper surface of the source region 7. Also on the source region 7 is a source electrode 9.
Example 2
Referring to fig. 9, a method for manufacturing a silicon carbide MOSFET power device includes the steps of:
S1, as shown in fig. 10-11, an epitaxial layer 3 is formed on a substrate 2 through epitaxial growth, the thickness of the silicon carbide epitaxial layer 3 is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3. The substrate 2 is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC material, the thickness is 10-1000 mu m, the doping concentration is 1e18cm -3~5e19cm-3, and the doping elements are N, P and the like. The epitaxial layer is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the epitaxial layer 3 is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3.
S2, as shown in FIG. 12, an ion implantation mask layer is formed on the surface of the epitaxial layer 3 through a chemical vapor deposition process, a patterned etching mask layer is formed through a photoetching process, and the epitaxial layer 3 is subjected to ion implantation by utilizing the patterned ion implantation mask layer, so that a well region 6 is formed. The depth of the well region 6 is 0.5 mu m-1.0 mu m, the doping distribution can be uniform distribution or nonuniform distribution, and the average doping concentration is 5e16cm -3~5e17cm-3. After removing the mask, a source region 7 is formed in the same mode, the depth of the source region 7 is 0.1 mu m-0.5 mu m, and the doping concentration is 1e19cm -3~5e20cm-3. And after the injection is completed, annealing the prepared device for 2-30 min at the temperature of 1400-2200 ℃. The substrate 2, the epitaxial layer 3, the well region 6 and the source region 7 are all of N type or P type.
S3, as shown in FIG. 13, an etching mask layer is formed on the surface of the epitaxial layer 3 through chemical vapor deposition, then a patterned etching mask layer is formed through a photolithography process, the patterned etching mask layer is used for carrying out inductively coupled plasma etching on the epitaxial layer 3, part of the epitaxial layer 3 is removed, a second groove 402 penetrating through the well region 6 and the source region 7 is formed, and then the etching mask layer is removed. The width of the second groove 402 is 0.5-1.8 [ mu ] m, and the depth is 0.5 [ mu ] m-2.0 [ mu ] m. The depth of the second trench 402 is greater than the depth of the well region 6 by a difference of not less than 0.1 μm.
S4, as shown in FIG. 14, an etching mask layer is formed on the surface of the epitaxial layer 3 and the side wall and the bottom of the second trench 402 by chemical vapor deposition, then a patterned etching mask layer is formed by a photolithography process, and the bottom of the second trench 402 is isotropically etched by using the patterned etching mask layer, so as to form a first trench 401 communicated with the second trench 402. And then removing the etching mask layer, passivating the groove by a high-temperature annealing process, wherein the gas can be one or more of SiH 4、H2, ar and the like, and the annealing temperature is 1400-1800 ℃. The first trench 401 and the second trench 402 constitute a gate trench 4. The width of the first groove 401 is 0.7-2 mu m, the depth is 0.2-1.0 mu m, the width of the second groove 402 is 0.5-1.8 mu m, and the depth is 0.5-2.0 mu m. The width of the first grooves 401 is larger than the width of the second grooves 402, and the distance between adjacent first grooves 401 is not smaller than 1[ mu ] m. The side wall angles of the first groove 401 and the second groove 402 are more than or equal to 80 degrees.
S5, as shown in FIG. 15, a substitute layer 11 is formed at the bottom of the first trench 401 through a chemical vapor deposition process, a photolithography process and an etching process, the substitute layer 11 may be made of polysilicon or amorphous silicon, and the thickness of the substitute layer 11 is 50 nm-0.5 [ mu ] m.
S6, as shown in FIG. 16, a first dielectric layer 501 is formed at two bottom corners of the gate trench through a thermal oxidation process, a second dielectric layer 502 is formed at the side wall of the second trench 402, a third dielectric layer 503 is formed at the bottom of the first trench 401 far away from the bottom corners, and then the quality of the dielectric layer 5 is improved through a high-temperature annealing process, wherein the annealing gas can be one or more of NO, N 2O、H2、NH3 and the like, and the annealing temperature is 900-1300 ℃. The thickness of the first dielectric layer 501 is 70 nm-200 nm, the thickness of the second dielectric layer 502 is 40 nm-100 nm, the thickness of the third dielectric layer 503 is 40 nm-150 nm, the third dielectric layer 503 is formed by thermal oxidation of the substitution layer 11, and the breakdown resistance of the gate dielectric (dielectric layer 5) can be further improved.
S7, as shown in FIG. 17, forming a gate electrode 8 through a chemical vapor deposition process, a photoetching process and an etching process, wherein polysilicon is selected as a material of the gate electrode 8, polysilicon injection is carried out, and the surface of the polysilicon is flattened through a CMP process. The patterned isolation medium layer 10 is formed through a chemical vapor deposition process, a photoetching process and an etching process, silicon nitride is selected as a material of the isolation medium layer 10, and the thickness is 0.5-10 mu m, so that a source electrode window is formed. Evaporating metal through the source window, wherein the metal is Ti/Al alloy, and then annealing at 300-1100 ℃ to form source ohmic contact. A drain ohmic contact is formed on the bottom layer of the substrate 2, a source electrode 9 is formed on the surface of the source ohmic contact, and a drain electrode 1 is formed on the surface of the drain ohmic contact.
The silicon carbide MOSFET power device obtained in this embodiment is identical to the rest of the structure of the device obtained in embodiment 1, except that: the dielectric layer 5 comprises a first dielectric layer 501, a second dielectric layer 502 and a third dielectric layer 503, wherein the third dielectric layer 503 is arranged at the bottom center of the gate trench 4, and the thickness is 40-150 nm. The dielectric layers 5 are each made of a silicon dioxide material.
Claims (10)
1. A silicon carbide MOSFET power device, characterized by: the semiconductor device comprises a drain electrode (1), wherein a substrate (2), an epitaxial layer (3), a well region (6) and a source region (7) are sequentially arranged on the surface of the drain electrode (1); a gate groove (4) is arranged on the epitaxial layer (3), the well region (6) and the source region (7), the gate groove (4) comprises a first groove (401) and a second groove (402), the diameter of the first groove (401) is larger than that of the second groove (402), and a coaxial dielectric layer (5) and a gate electrode (8) are arranged in the gate groove (4); the dielectric layer (5) comprises a first dielectric layer (501) arranged in the first groove (401) and a second dielectric layer (502) arranged in the second groove (402), and the thickness of the first dielectric layer (501) is larger than that of the second dielectric layer (502); the surface of the grid electrode (8), the dielectric layer (5) and the source region (7) is provided with an isolation dielectric layer (10), and the surface of the source region (7) is also provided with a source electrode (9).
2. A silicon carbide MOSFET power device according to claim 1, wherein: the diameter of the first groove (401) is 0.1-0.5 mu m larger than that of the second groove (402).
3. A silicon carbide MOSFET power device according to claim 2, wherein: the depth-to-width ratio of the first groove (401) is less than or equal to 2:1, and the side wall angle is more than or equal to 80 degrees.
4. A silicon carbide MOSFET power device according to claim 2, wherein: the depth-to-width ratio of the second groove (402) is more than or equal to 1.5:1, and the side wall angle is more than or equal to 80 degrees.
5. A silicon carbide MOSFET power device according to claim 1, wherein: the dielectric layer (5) further comprises a third dielectric layer (503), and the third dielectric layer (503) is arranged at the bottom center of the gate groove (4) and has a thickness of 40-150 nm.
6. A silicon carbide MOSFET power device according to claim 1, wherein: the dielectric layer (5) is made of a silicon dioxide material.
7. A silicon carbide MOSFET power device according to claim 1, wherein: the substrate (2) is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the substrate (2) is 10-1000 mu m, and the doping concentration is 1e18cm -3~5e19cm-3.
8. A silicon carbide MOSFET power device according to claim 1, wherein: the epitaxial layer (3) is made of 3C-SiC, 4H-SiC, 6H-SiC or 15R-SiC materials, the thickness of the epitaxial layer (3) is 8-200 mu m, and the doping concentration is 1e14cm -3~1e16cm-3.
9. A method of making a silicon carbide MOSFET power device according to claim 1 or 5, comprising the steps of:
sequentially growing an epitaxial layer (3), a well region (6) and a source region (7) on a substrate (2);
performing inductively coupled plasma etching on the epitaxial layer (3) to remove part of the epitaxial layer (3) and form grooves penetrating through the well region (6) and the source region (7);
Performing isotropic etching on the bottom of the groove, and performing high-temperature annealing passivation at 1400-1800 ℃ to form a gate groove (4);
forming a first dielectric layer (501) at two bottom corners of the gate trench (4), forming a second dielectric layer (502) at the side wall of the gate trench (4), and performing high-temperature annealing at 900-1300 ℃;
Fifthly, forming a gate electrode (8) in the dielectric layer (5), forming an isolation dielectric layer (10) and a source electrode (9) on the surfaces of the gate electrode (8) and the source region (7), and forming a drain electrode (1) on the substrate (2).
10. The method for manufacturing a silicon carbide MOSFET power device according to claim 9, wherein: the fourth step is replaced by: and forming a substitute layer (11) at the center of the bottom of the gate trench (4), forming a first dielectric layer (501) at two bottom corners of the gate trench (4), forming a second dielectric layer (502) at the side wall of the gate trench (4), and performing high-temperature annealing at 900-1300 ℃, wherein the substitute layer (11) is subjected to thermal oxidation to form a third dielectric layer (503).
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| CN112735953A (en) * | 2020-12-28 | 2021-04-30 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench MOSFET |
| CN112864249A (en) * | 2021-01-11 | 2021-05-28 | 江苏东海半导体科技有限公司 | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof |
| CN116154000A (en) * | 2023-01-30 | 2023-05-23 | 中国电子科技集团公司第五十五研究所 | Multistage groove type SiC MOSFET device and manufacturing method thereof |
| CN117525154A (en) * | 2024-01-05 | 2024-02-06 | 南京第三代半导体技术创新中心有限公司 | Double-groove silicon carbide MOSFET device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112735953A (en) * | 2020-12-28 | 2021-04-30 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench MOSFET |
| CN112864249A (en) * | 2021-01-11 | 2021-05-28 | 江苏东海半导体科技有限公司 | Low-grid-leakage-charge groove type power semiconductor device and preparation method thereof |
| CN116154000A (en) * | 2023-01-30 | 2023-05-23 | 中国电子科技集团公司第五十五研究所 | Multistage groove type SiC MOSFET device and manufacturing method thereof |
| CN117525154A (en) * | 2024-01-05 | 2024-02-06 | 南京第三代半导体技术创新中心有限公司 | Double-groove silicon carbide MOSFET device and manufacturing method thereof |
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