CN112685241A - Multi-granularity memory detection method, memory device and electronic device - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 410
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- 238000005070 sampling Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 36
- 238000012360 testing method Methods 0.000 claims description 14
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- 230000004044 response Effects 0.000 claims 1
- 235000019580 granularity Nutrition 0.000 description 39
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- ZXQYGBMAQZUVMI-GCMPRSNUSA-N gamma-cyhalothrin Chemical compound CC1(C)[C@@H](\C=C(/Cl)C(F)(F)F)[C@H]1C(=O)O[C@H](C#N)C1=CC=CC(OC=2C=CC=CC=2)=C1 ZXQYGBMAQZUVMI-GCMPRSNUSA-N 0.000 description 7
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- 230000008569 process Effects 0.000 description 3
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- 230000004048 modification Effects 0.000 description 1
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Abstract
The technical scheme of the application discloses a multi-granularity memory detection method, memory equipment and electronic equipment, and can detect a memory module in an Soc chip when the Soc chip runs, wherein the memory module is divided into a plurality of memory sub-modules, and each memory sub-module comprises a plurality of memory units; the memory detection method comprises the following steps: when a new memory detection task exists, judging whether a memory detection condition is met; if yes, obtaining a memory detection strategy and a correspondingly configured granularity parameter; and performing sampling detection on the memory units in the memory sub-modules based on the memory detection strategy and the granularity parameters. According to the technical scheme, the memory modules are separated to form a plurality of memory sub-modules, based on the memory detection strategy and the granularity parameters, the memory units in the memory sub-modules are subjected to sampling detection, the detection flexibility can be improved, and the system overhead is balanced.
Description
Technical Field
The present disclosure relates to the field of integrated circuit verification and testing technologies, and more particularly, to a multi-granularity memory detection method, a memory device, and an electronic device.
Background
With the rapid development of the internet of things technology, the internet of things equipment is widely used. The analysis reported in 2019 of McKensin states that 250 billion devices have internet access in 2015, and by 2025, this figure would exceed 400 billion. The user uses the Internet of things equipment, so that the life becomes convenient and fast; the Internet of things equipment relies on a user, and provides various services for the user while collecting personal information (such as contact persons, positions, health information and the like) of the user. The close connection between "people" and "things" has become a distinct feature of the present society. However, close contact provides both convenience and a degree of security threat to life.
A System on Chip (SoC) is a hardware basis of the internet of things device, and a memory is an important component of the SoC Chip, and if a fault is contained or an attack such as a hardware trojan is received, functions of the device can be changed, or personal information of a user can be revealed, or even loss of lives and properties of the user can be brought.
Disclosure of Invention
In view of this, the present application provides a multi-granularity memory detection method, a memory device, and an electronic device, and the scheme is as follows:
a multi-granularity memory detection method is used for detecting a memory module in an Soc chip when the Soc chip runs, wherein a storage module is divided into a plurality of memory sub-modules, and each memory sub-module comprises a plurality of memory units;
the memory detection method comprises the following steps:
when a new memory detection task exists, judging whether a memory detection condition is met;
if yes, obtaining a memory detection strategy and a correspondingly configured granularity parameter;
and performing sampling detection on the memory units in the memory sub-modules based on the memory detection strategy and the granularity parameters.
Preferably, in the memory detection method, the method for determining whether a new memory detection task is available includes:
scanning a security policy engine;
and judging whether a new memory detection task exists or not based on the scanning result.
Preferably, in the memory detection method, if the security policy engine obtains a trigger condition for triggering a new memory detection task, a flag bit representing that the new memory detection task is present is generated.
Preferably, in the memory detection method, the method of determining whether the memory detection condition is satisfied includes:
judging whether the memory module is responding to the read-write operation of the bus or not;
and if so, meeting the memory detection condition.
Preferably, in the memory detection method, the method for dividing the memory module into a plurality of memory sub-modules includes:
and taking a storage space consistent with the bit width of the bus as one memory unit, taking n memory units as one memory submodule, wherein n is a positive integer greater than 1.
Preferably, in the memory detection method, the method for obtaining the memory detection policy and the granularity parameter configured correspondingly includes:
acquiring the memory detection strategy and the granularity parameter from the security strategy engine;
the memory detection strategy comprises P grain size modes, wherein the P grain size modes are from a 1 st grain size mode to a P P grain size mode in sequence, and P is a positive integer greater than 1; the ith granularity mode is randomly extracted from each memory submodule
Detecting the memory units, if the memory units extracted from the memory sub-modules have no errors, representing that the memory sub-modules have no faults, wherein i is a positive integer not greater than P; n is the number of the memory units in the memory submodule.
Preferably, in the above memory detection method, the method for performing sampling detection on the memory cells in the memory sub-module includes:
calculating the detection address range of the memory module divided into a plurality of memory sub-modules;
and randomly sampling the address of the memory unit to be detected in each memory sub-module according to the granularity parameter, detecting the memory unit to be detected, and recording the detection result.
Preferably, in the memory detection method, after randomly sampling the address of the memory unit to be detected in each memory sub-module, detecting the memory unit to be detected, and recording the detection result, the method includes:
after the address of the memory unit to be detected is obtained, backing up memory data corresponding to the corresponding memory unit;
after the memory data backup is completed, detecting the memory unit to be detected;
and after the detection of the current memory unit to be detected is finished, writing back the backup memory data, recording the detection result, and detecting the next memory unit to be detected until all the memory units to be detected are detected.
Preferably, in the memory detection method, the method further includes:
and generating a detection result report after the detection of all the memory units to be detected is completed.
The present application further provides a memory device, the memory device capable of being based on an external security policy engine, the memory device comprising:
the memory module is divided into a plurality of memory sub-modules, and each memory sub-module comprises a plurality of memory units;
the control circuit is used for responding to the control of the security policy engine, executing any one of the memory detection methods and detecting the memory module;
and the memory access gating module is used for selectively responding to an external bus request or a memory detection request of the security policy engine, and is also used for backing up data taken out of the memory unit to be detected by the control circuit when the memory module is detected.
The application also provides an electronic device, which comprises the memory device.
As can be seen from the above description, the technical scheme of the present application is a multi-granularity security detection scheme based on a preset memory detection strategy, and aims at the problem that a memory module in an SoC chip is vulnerable to faults and hardware trojan attacks, etc., the memory module is divided into a plurality of memory sub-modules, and each memory sub-module includes a plurality of memory units; the memory detection method comprises the following steps: when a new memory detection task exists, judging whether a memory detection condition is met; if yes, obtaining a memory detection strategy and a correspondingly configured granularity parameter; and performing sampling detection on the memory units in the memory sub-modules based on the memory detection strategy and the granularity parameters. This application technical scheme is through dividing the memory module, forms a plurality of memory sub-modules, based on memory detection strategy and the granularity parameter is right in the memory sub-module the memory unit carries out the sampling inspection to this accomplishes the sampling inspection, judges whether the memory module has the trouble or suffers the attack when moving according to the algorithm result, detection scheme when this application technical scheme one kind is moved, through the detection scheme of many granularities, can realize different detection overhead demands, nimble adaptation operation in-process, the memory detection demand of probably dynamic change can improve and detect the flexibility ratio, balanced system overhead.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.
Fig. 1 is a schematic flowchart of a multi-granularity memory detection method according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a method for performing sampling detection on the memory cells in the memory sub-module according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for detecting a memory cell to be detected according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of another multi-granularity memory detection method according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a memory device according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As described in the background, if a fault is contained or a hardware trojan or other attacks are received, the function of the device is changed, or personal information of the user is revealed, or even loss of lives and properties is brought to the user. Therefore, how to detect the memory device is a problem to be solved in the technical field of verification and test of integrated circuits, aiming at the problems that the memory in the system-on-chip is easy to have faults and is attacked by hardware trojans and the like.
Research shows that when a trigger circuit of the hardware Trojan horse is implanted into a cache (cache), and a certain specific address in the cache is accessed for N times, the hardware Trojan horse is activated, and confidential information in a key memory is leaked. The hardware trojan is specially designed, and the intrinsic safety strategy of the CPU cannot be detected. Such attacks can be detected by verifying the read-write technique after read/write.
In the related technology, various hardware trojans in a memory, fault behaviors and trigger modes of the hardware trojans are listed, and a traditional March algorithm for detecting the hardware trojans in the memory is introduced, namely, in a silicon post-test, certain units in the memory are subjected to sequential operations of writing 0, reading 0, writing 1 and reading 1, so that whether faults exist in the units is judged.
The memory faults can be divided into concepts and implementation modes of static faults and dynamic faults, and different March algorithms are respectively designed for detection according to the characteristics of the two faults. However, with the increase of memory fault types and the complication of memory attack modes, the detection efficiency and the detection overhead of the March algorithm after silicon are simply depended on are linearly increased with the increase of the memory density and the scale, and the operation faults and the attacks in the memory cannot be completely detected. Therefore, development of flexible runtime memory detection has gradually become a trend of memory detection.
And marking bits can be added to the data in the memory, marking bit propagation rules are formulated, and memory destruction attacks are detected by adding the marking bits in the processor core for inspection.
At present, in the chip memory detection technology, the attack and protection requirements of the memory are various, only one granularity detection method is applied, and errors of detection results may be caused for the memory requiring the fine detection granularity. For memories requiring coarse detection granularity, additional overhead such as power consumption or performance may be incurred for the system. If the system can flexibly configure the granularity of memory detection according to the attack level and the protection requirement, the balance between equipment safety and performance overhead can be realized. In addition, a large number of failures or attacks bypass the traditional post-silicon test using runtime conditions or device aging models, and runtime detection schemes must be deployed to extend the security memory detection to the entire device lifecycle.
The existing related memory detection mainly adopts a post-silicon test method, so that the detection in operation cannot be carried out, and the security strategies contained in the framework supporting the detection in operation cannot be flexibly configured, so that the memory detection capability of the framework is limited to a great extent. In addition, the efficiency and system overhead of the conventional memory detection scheme are linearly increased with the increase of the memory size, and the granularity cannot be flexibly selected according to the protection requirement and the resource condition. In order to obtain compromise between safety and performance, the technical scheme is a multi-granularity memory detection scheme based on Match C-sampling, multi-granularity memory detection can be performed according to the content of a safety strategy when the SoC is deployed and operated, and the fact that no inherent fault exists in a system or the fault is caused by attack in operation is judged.
Based on the above description, the technical scheme of the embodiment of the application mainly solves the related problems of memory failure, low detection efficiency of attack during operation, high overhead and the like existing in the SoC chip. This application technical scheme provides a many granularities memory security detection scheme based on predetermine memory detection strategy, to the problem that the memory in the system on chip is easy to exist the trouble and is suffered attacks such as hardware trojan horse, through dividing the memory module, forms a plurality of memory sub-modules, based on memory detection strategy and granularity parameter provides the memory cell sampling scheme of many granularities, right in the memory sub-module the memory cell carries out the sampling test, can improve and detect the flexibility ratio, balanced system overhead.
According to the technical scheme, the memory detection strategy and the granularity parameters can be configured on line, multi-granularity memory module detection is achieved, the relations of detection coverage rate, time complexity and the like are expressed and mapped according to the strategy parameters, and the detection efficiency and the detection cost can be balanced flexibly.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 1, fig. 1 is a schematic flow chart of a multi-granularity memory detection method provided in this embodiment, when an Soc chip runs, the memory detection method is used to detect a memory module in the Soc chip, where the memory module is divided into a plurality of memory sub-modules, and each memory sub-module includes a plurality of memory units. The memory detection method comprises the following steps:
step S11: and when a new memory detection task exists, judging whether a memory detection condition is met.
Step S12: if so, acquiring the memory detection strategy and the corresponding configured granularity parameter.
If the memory detection condition is not met, after the timer waits for a certain time, whether a new memory detection task exists is determined again.
Step S13: and performing sampling detection on the memory units in the memory sub-modules based on the memory detection strategy and the granularity parameters.
In the memory detection method according to the embodiment of the present application, as shown in fig. 1, the method for determining whether a new memory detection task exists includes:
step S101: a security policy engine is scanned.
Step S102: and judging whether a new memory detection task exists or not based on the scanning result.
And if the security policy engine obtains a trigger condition for triggering the new memory detection task, generating a flag bit representing that the new memory detection task is available. And when the flag bit is detected, representing that a new memory detection task exists, and if the flag bit cannot be detected, representing that the new memory detection task does not exist. If there is a new memory check task, step S11 is executed. And if the new memory detection task does not exist, normally finishing the subsequent operation of the system.
In the memory detection method according to the embodiment of the present application, the method for determining whether the memory detection condition is satisfied includes: judging whether the memory module is responding to the read-write operation of the bus or not; if yes, the memory detection condition is met; otherwise, the memory detection condition is not satisfied. It should be noted that the method for determining whether the foot memory detection condition is satisfied includes, but is not limited to, the foregoing method, and may also be other methods, for example, whether the memory detection condition is satisfied may be determined based on whether a detection instruction input by a user is received.
In the memory detection method according to the embodiment of the present application, the method for dividing the memory module into a plurality of memory sub-modules includes: and taking a storage space consistent with the bit width of the bus as one memory unit, taking n memory units as one memory submodule, wherein n is a positive integer greater than 1. If the bus bit width is 23 bits, the storage space of 32 bits is used as a memory unit.
In the memory detection method according to the embodiment of the present application, the method for obtaining the memory detection policy and the granularity parameter configured correspondingly includes: and acquiring the memory detection strategy and the granularity parameter from the security strategy engine. The memory detection strategy comprises P grain size modes, wherein the P grain size modes are from a 1 st grain size mode to a P P grain size mode in sequence, and P is a positive integer greater than 1; the ith granularity mode is randomly extracted from each memory submodule
Detecting the memory units, if the memory units extracted from the memory sub-modules have no errors, representing that the memory sub-modules have no faults, wherein i is a positive integer not greater than P; n is the number of the memory units in the memory submodule.
As shown in fig. 2, fig. 2 is a schematic flowchart of a method for performing sampling detection on the memory cells in the memory sub-module according to an embodiment of the present application, where the method includes:
step S21: and calculating the detection address range of the memory module divided into a plurality of memory sub-modules.
Step S22: and randomly sampling the address of the memory unit to be detected in each memory sub-module according to the granularity parameter, detecting the memory unit to be detected, and recording the detection result.
In the memory detection method according to the embodiment of the present application, after the address of the memory unit to be detected in each memory sub-module is randomly sampled, the method for detecting the memory unit to be detected and recording the detection result is shown in fig. 3.
As shown in fig. 3, fig. 3 is a flowchart of a method for detecting a memory cell to be detected according to an embodiment of the present disclosure, where the method includes:
step S31: and after the address of the memory unit to be detected is obtained, backing up the memory data corresponding to the corresponding memory unit.
Step S32: and after finishing memory data backup, detecting the memory unit to be detected.
Step S33: and after the detection of the current memory unit to be detected is finished, writing back the backup memory data, recording the detection result, and detecting the next memory unit to be detected until all the memory units to be detected are detected.
As shown in fig. 3, the method further includes:
step S34: and generating a detection result report after the detection of all the memory units to be detected is completed.
In the memory detection method in the embodiment of the application, a multi-granularity March algorithm based on sampling is performed in the specific detection process, and the detection granularity parameter is defined as the detection fineness of a memory unit in a memory submodule and is expressed by the sampling rate. The detection of the memory unit is to perform March detection on the memory unit.
The March algorithm is a general memory fault detection algorithm, and compared with other memory fault detection algorithms, such as a scanning image Method (MSAN), a checkerboard algorithm (Checkboard), a galloping pattern algorithm (GALPAT), and the like, the March algorithm is more flexible in test mode and higher in fault coverage rate. The March algorithm determines whether a failure exists in a memory cell by writing different values into different memory cells and comparing them with expected values. According to different fault models in the memory, the writing and reading modes of the March algorithm are different. The March algorithm has good expansibility, so that various versions of March algorithms are derived, including MATS, MATS + +, March X, March Y, March C-, March A and other algorithms. The March algorithms of different versions have different fault coverage rates for different fault models. The March C-algorithm is moderate in time complexity, and can detect various types of memory faults. And (4) integrating various considerations. Therefore, the March C-algorithm is selected as the memory detection algorithm in the patent.
Setting the memory depth N as an integer multiple of N, based on the granularity pattern in P defined in the present application, as follows:
particle size mode 1: extracting n memory units in each memory submodule to perform March detection, and if the extracted memory units in the memory submodules have no errors, representing that the memory submodules have no faults;
particle size mode 2: randomly extracting n/2 memory units from each memory submodule to perform March detection, and if the memory units extracted from the memory submodules have no errors, representing that the memory submodules have no faults;
particle size mode 3: randomly extracting n/4 memory units from each memory submodule to perform March detection, and if the memory units extracted from the memory submodules have no errors, representing that the memory submodules have no faults;
particle size mode 4: randomly extracting n/8 memory units from each memory submodule to perform March detection, and if the memory units extracted from the memory submodules have no errors, representing that the memory submodules have no faults;
……
the P grain size mode: randomly extracting from each of the memory sub-modules
And carrying out March detection on the memory units, and if the memory units extracted from the memory sub-modules have no errors, representing that the memory sub-modules have no faults.
From the above description, the particle size G is, in various particle size modes:
the larger the particle size G, the higher the degree of fineness of detection, and taking n as an example 8, the particle sizes of the 1 st to P th particle size modes are shown in table 1 below.
TABLE 1
| 1 |
2 nd granularity mode | 3 rd granularity mode | 4 th granularity | |
| Particle size | ||||
| 1 | 0.5 | 0.25 | 0.125 |
The March C-algorithm is executed in the detection process as follows:
the March C-algorithm has a time complexity of 10N, and can detect AF, SAF (Stuck-at Fault), TF (Transition Fault), CFin (Inversion Coupling Fault), and CFid (idempotent Coupling Fault) contained in the memory module. The specific detection flow of the algorithm is as follows:
①(w0)；②↑(r0，w1)；③↑(r1，w0)；④↓(r0，w1)；⑤↓(r1，w0)；⑥↓(r0)；
wherein "w" represents a write operation; "r" represents a read operation. "w 0" represents writing a 0 to a memory cell; "w 1" represents a 1 being written to a memory cell; "r 0" represents a read of 0 into a memory cell; "r 1" represents a read of a 1 into a memory cell. ")" × "represents an operation from the memory low address unit to the memory high address unit; "↓" represents the operation from the high address unit to the low address unit of the memory.
Based on the above description, it can be known that the actual meanings of operations (i) to (ii) of the March C-algorithm are as follows:
r ≈ e (w 0): operating from a low address to a high address of the memory unit, and sequentially writing 0;
② ↓ (r0, w 1): operating from the low address to the high address of the memory unit, sequentially reading the 0 written in the previous step, and then writing 1;
③ ≠ (r1, w 0): operating from the low address to the high address of the memory unit, sequentially reading the 1 written in the previous step, and then writing 0;
r ↓ (r0, w 1): operating from the high address to the low address of the memory unit, sequentially reading the 0 written in the last step, and then writing 1;
v ↓ (r1, w 0): operating from the high address to the low address of the memory unit, sequentially reading the 1 written in the previous step, and then writing 0;
sixthly ↓ (r 0): operating from a high address to a low address of the memory unit, and sequentially reading 0 written in the previous step;
depending on the type of failure, the data read during operation will vary. Therefore, the memory fault can be detected and the type of the memory fault can be distinguished by executing the algorithm.
As mentioned above, the memory depth is set to be N, and the number N of memory cells in each memory sub-module is taken as 8 as an example, and the comparison results of the fault coverage, the inspection coverage and the algorithm complexity in different granularity modes are shown in table 2 below.
TABLE 2
| Fault coverage rate | Inspection of coverage | Complexity of |
||
| 1 st granularity mode | 100％ | 100 | 10N | |
| 2 nd granularity mode | 100％ | 50％ | 5N | |
| 3 rd granularity mode | 100％ | 25％ | 2.5N | |
| 4 th granularity mode | 67％ | 12.5％ | 1.25N |
During detection, the change configuration with different granularities can be carried out in real time through the security strategy according to the checked fault coverage rate, the checked coverage rate requirement and the resource condition, so as to complete the corresponding memory check.
Based on the above description, a specific execution flow of the memory detection method according to the present application may be as shown in fig. 4, where fig. 4 is a schematic flow chart of another multi-granularity memory detection method provided in this embodiment of the present application.
According to the above description, the present application provides a security detection method for a multi-granularity memory module based on a preset detection strategy, which can be used for solving the problems that a memory module in a system-on-chip is prone to faults and attacks such as hardware trojans, and the like. The memory detection method can flexibly adapt to different memory detection requirements and balance the overhead.
Based on the foregoing embodiment, another embodiment of the present application further provides a memory device, as shown in fig. 5, where fig. 5 is a schematic structural diagram of a memory device provided in the embodiment of the present application, the memory device can be based on an external security policy engine SPC, and the memory device 11 includes:
the memory module 12, the memory module 12 is divided into a plurality of memory sub-modules, and the memory sub-modules include a plurality of memory units;
a control circuit 13, where the control circuit 13 is configured to respond to control of the security policy engine, execute the memory detection method described in the foregoing embodiment, and detect the memory module 12;
and the memory access gating module 14 is configured to select to respond to an external bus request or a memory detection request of the security policy engine SPC, and is further configured to backup data taken out from the memory unit to be detected by the control circuit 13 when the memory module 12 is detected.
As shown in fig. 5, the memory access gating module 14 includes: the device comprises a gating device Test _ MUX, a gating device Reg _ MUX, a first judging unit judge1, a second judging unit judge2 and a data register. The data register is connected to the gating device REG _ MUX through the PORT10_ REG. The first judgment unit judge1 is connected to the gating device Test _ MUX through the PORT0_ MEM, and connected to the gating device REG _ MUX through the PORT0_ REG, and can respond to the bus system access. The interface responding to bus system accesses is also connected to the control circuit 13. The first judgment unit judge1 is also connected to the port reg _ runnto of the control circuit 13. The second judgment unit judge2 is connected with the gating device Test _ MUX through the PORT1_ MEM and the gating device REG _ MUX through the PORT1_ REG, and can receive the detection and control signals of the security policy engine SPC. The interface receiving the security policy engine SPC detection and control signals is also connected to the control circuit 13. The gating device Test _ MUX is connected to the memory module 12 and also connected to the port Test _ now of the control circuit 13. The gating device Reg _ MUX is connected to the port copy _ remove of the control circuit 13. The control circuit 13 is connected with an address register.
The memory module comprises an original interface with AXI. The memory device 11 is controlled by an external security policy engine SPC to perform detection, and feeds back a detection result to the memory device, and meanwhile, retains an original bus interface connected to the AXI, and the interface responds to a bus read-write request of an original SoC system. The control circuit 13 is used for controlling the specific execution state of the memory detection, judging the detection and read-write conflict, processing redirection and the like, and the memory access gating module 14 has the functions of selecting and responding to an external bus request or a memory detection request of a security policy engine SPC, backing up data of a unit to be detected and the like. The specific method for detecting the memory during the operation comprises the following steps: when the first detection is started, the control circuit 13 takes out the data stored in the memory cell to be detected in the memory module 12 from the corresponding memory cell address, temporarily stores the data in the data register of the access gating module 14, and then starts the detection. When the system bus is to perform a read/write operation currently on the memory module 12, there are two operating conditions:
1) when the object of the read-write operation is the memory unit being detected, the control circuit 13 redirects the read-write operation to the data register corresponding to the backed-up original data for execution, and the detected memory unit continues to be detected by the security policy engine SPC. When the detection is completed, the security policy engine SPC writes back the value stored in the data register to the memory unit in which the detection is completed, and outputs a flag signal to notify the memory device 11 that the read/write request of the system bus is no longer redirected to the register.
2) When the object of the read/write operation is not the memory cell being tested, the control circuit 13 will send a flag signal to the security policy engine SPC, interrupting the memory test operation being performed and saving the relevant state. The access gating module 14 then responds to the read and write operations of the bus. When the read-write operation is completed, the security policy engine SPC continues the subsequent detection process, writes back the value stored in the data register to the memory unit that has completed the detection after completion, and outputs a flag signal to notify the memory device 11 that the read-write request of the system bus is no longer redirected to the register.
The memory device according to the embodiment of the present application can be used to implement the memory detection method according to the above embodiment, when performing memory detection, the memory module is partitioned into a plurality of memory sub-modules, the March-C algorithm that performs granularity sampling is performed on each memory sub-module, security detection during operation is sequentially completed, and whether a system memory module has a fault or is attacked during operation is determined according to the result of the algorithm. The memory detection method can flexibly adapt to different memory detection requirements and balance the overhead.
Based on the above embodiment, another embodiment of the present application further provides an electronic device, where the electronic device includes the memory device described in the above embodiment. The electronic device includes, but is not limited to, computers, smart phones, wearable devices, and other electronic devices.
The electronic device is provided with the memory device in the embodiment, the memory module is partitioned into a plurality of memory sub-modules, the March-C algorithm of required granularity sampling is executed on each memory sub-module, the safety detection in operation is sequentially completed, and whether the memory module of the system has a fault or suffers from operation attack is judged according to the algorithm result. The memory detection method can flexibly adapt to different memory detection requirements and balance the overhead.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. As for the electronic device and the memory device disclosed in the embodiments, since they correspond to the memory detection method disclosed in the embodiments, the description is relatively simple, and the relevant points can be described with reference to the relevant parts of the memory detection method.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. The multi-granularity memory detection method is characterized in that when an Soc chip runs, the memory detection method is used for detecting a memory module in the Soc chip, the memory module is divided into a plurality of memory sub-modules, and each memory sub-module comprises a plurality of memory units;
the memory detection method comprises the following steps:
when a new memory detection task exists, judging whether a memory detection condition is met;
if yes, obtaining a memory detection strategy and a correspondingly configured granularity parameter;
and performing sampling detection on the memory units in the memory sub-modules based on the memory detection strategy and the granularity parameters.
2. The memory detection method according to claim 1, wherein the method for determining whether there is a new memory detection task comprises:
scanning a security policy engine;
and judging whether a new memory detection task exists or not based on the scanning result.
3. The memory sensing method of claim 2, wherein if the security policy engine obtains a trigger condition for triggering a new memory sensing task, a flag bit indicating that the new memory sensing task is present is generated.
4. The method according to claim 1, wherein the step of determining whether the memory detection condition is satisfied comprises:
judging whether the memory module is responding to the read-write operation of the bus or not;
and if so, meeting the memory detection condition.
5. The method according to claim 1, wherein the step of dividing the memory module into a plurality of memory sub-modules comprises:
and taking a storage space consistent with the bit width of the bus as one memory unit, taking n memory units as one memory submodule, wherein n is a positive integer greater than 1.
6. The memory detection method according to claim 1, wherein the method for obtaining the memory detection policy and the granularity parameter configured correspondingly comprises:
acquiring the memory detection strategy and the granularity parameter from the security strategy engine;
the memory detection strategy comprises P grain size modes, wherein the P grain size modes are from a 1 st grain size mode to a P P grain size mode in sequence, and P is a positive integer greater than 1; the ith granularity mode is randomly extracted from each memory submodule
Detecting the memory units, if the memory units extracted from the memory sub-modules have no errors, representing that the memory sub-modules have no faults, wherein i is a positive integer not greater than P; n is the number of the memory units in the memory submodule.
7. The memory sensing method of any one of claims 1-6, wherein the step of performing a sampling test on the memory cells in the memory sub-module comprises:
calculating the detection address range of the memory module divided into a plurality of memory sub-modules;
and randomly sampling the address of the memory unit to be detected in each memory sub-module according to the granularity parameter, detecting the memory unit to be detected, and recording the detection result.
8. The method according to claim 7, wherein detecting the memory unit to be detected after randomly sampling the address of the memory unit to be detected in each of the memory sub-modules, and recording the detection result comprises:
after the address of the memory unit to be detected is obtained, backing up memory data corresponding to the corresponding memory unit;
after the memory data backup is completed, detecting the memory unit to be detected;
and after the detection of the current memory unit to be detected is finished, writing back the backup memory data, recording the detection result, and detecting the next memory unit to be detected until all the memory units to be detected are detected.
9. The memory detection method according to claim 8, further comprising:
and generating a detection result report after the detection of all the memory units to be detected is completed.
10. A memory device capable of being based on an external security policy engine, the memory device comprising:
the memory module is divided into a plurality of memory sub-modules, and each memory sub-module comprises a plurality of memory units;
a control circuit for performing the memory test method of any one of claims 1-9 to test the memory module in response to control of the security policy engine;
and the memory access gating module is used for selectively responding to an external bus request or a memory detection request of the security policy engine, and is also used for backing up data taken out of the memory unit to be detected by the control circuit when the memory module is detected.
11. An electronic device, characterized in that the electronic device comprises a memory device according to claim 10.
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