CN112270948B - Test method and device for supporting DRAM x16 particles and test equipment for DRAM memory - Google Patents
Test method and device for supporting DRAM x16 particles and test equipment for DRAM memory Download PDFInfo
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- CN112270948B CN112270948B CN202011193104.0A CN202011193104A CN112270948B CN 112270948 B CN112270948 B CN 112270948B CN 202011193104 A CN202011193104 A CN 202011193104A CN 112270948 B CN112270948 B CN 112270948B
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- 238000012360 testing method Methods 0.000 title claims abstract description 110
- 239000002245 particle Substances 0.000 title claims abstract description 49
- 238000010998 test method Methods 0.000 title claims description 9
- 238000013507 mapping Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000008187 granular material Substances 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 6
- 239000008188 pellet Substances 0.000 claims description 5
- 238000011084 recovery Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 abstract 1
- 238000004422 calculation algorithm Methods 0.000 description 10
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- 230000009286 beneficial effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
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Abstract
The invention relates to the technical field of memory testing, and discloses a testing method and a testing device for supporting DRAM x16 particles and testing equipment for a DRAM memory, wherein the method comprises the following steps: closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain; setting page attributes, closing Cache attributes, and establishing a memory page table; and accessing the address space of the lower bits of the DRAM x16 grain Bank Group to acquire the memory error information of the DRAM x16 grain. The method can realize the detection of the DRAM x16 particle type and acquire the error information of the DRAM x16 particle type, thereby improving the service performance of the DRAM.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a test method and device for supporting DRAM x16 particles and test equipment for a DRAM memory.
Background
Dram (dynamic Random Access memory), which is a dynamic Random Access memory, is the most common system memory. DRAM memory is one of the important components in computers, and it is the bridge to communicate with the CPU. All the programs in the computer are executed in the memory, so the performance of the memory bank has a great influence on the computer. How to test the memory bank is very important to ensure the normal operation of the memory.
In the prior art of KTI DRAM memory Test device KT-4MG, the Test method for DRAM memory mainly includes ATE (Automatic Test Equipment) and BTT (Behavior Test Technology). Existing tests of ATE have been able to cover all DDR4 particle types in the market, but tests of BBT only support x4, x8 types of particles, and cannot test x16 particle types.
Disclosure of Invention
The invention aims to provide a method and a device for testing DRAM x16 particles and DRAM memory testing equipment, which are used for solving the technical problem that the conventional DRAM memory testing method cannot test the x16 particle type.
In order to achieve the purpose, the invention adopts the following technical scheme:
a method of testing to support DRAM x16 pellets, the method comprising:
closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain;
setting page attributes, closing Cache attributes, and establishing a memory page table;
and accessing the address space of the lower bits of the DRAM x16 grain Bank Group to acquire the memory error information of the DRAM x16 grain.
Further, before turning off Bank XOR Enable, calculating the memory capacity of the DRAM x16 granule, and simultaneously establishing address mapping for the DRAM x16 granule, the method further includes:
double Rank Size, so that the mapping and the calculated memory capacity are twice the actual capacity of the DRAM x16 particles, and a full address test space is realized.
Further, the setting of the page attribute, closing the Cache attribute, and establishing the memory page table includes:
initializing memory management, entering memory page table attribute setting, and closing Cache attributes;
establishing a memory page table; the memory page table includes a kernel memory page table and/or a user process memory page table.
Further, the accessing the address space of the lower bits of the Bank Group of the DRAM x16 granule and the obtaining of the memory error information of the DRAM x16 granule include;
accessing the address space of the lower bits of the DRAM x16 grain Bank Group by using BTT test software;
sending a test instruction to the DRAM x16 granule;
and detecting the DRAM x16 particles to obtain error information of the DRAM x16 particles.
The present invention also provides a memory test apparatus supporting DRAM x16 pellets, the apparatus comprising:
the address mapping unit is used for closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain;
the page table establishing unit is used for setting page attributes, closing Cache attributes and establishing a memory page table;
and the memory error acquisition unit is used for accessing the address space of the lower bits of the Bank Group of the DRAM x16 grain and acquiring the memory error information of the DRAM x16 grain.
Further, the apparatus further comprises:
and the capacity expansion unit is used for Double Rank Size, so that the mapping and calculated memory capacity is twice of the actual capacity of the DRAM x16 particles, and a full address test space is realized.
Further, the page table establishing unit includes:
the Cache attribute closing module is used for initializing memory management, entering memory page table attribute setting and closing Cache attributes;
the page table establishing module is used for establishing a memory page table; the memory page table includes a kernel memory page table and/or a user process memory page table.
Further, the memory error obtaining unit includes:
an address space access module, configured to access an address space of lower bits of a Bank Group of the DRAM x16 grain by using BTT test software;
the test instruction sending module is used for sending a test instruction to the DRAM x16 granules;
and the error information acquisition module is used for detecting the DRAM x16 particles and acquiring the memory error information of the DRAM x16 particles.
The invention also provides a test device of the DRAM memory, which comprises a test host used for test control and a test interface board used for providing a test interface of the DRAM memory; the test host writes therein a program that executes a test method of a memory supporting DRAM x16 granules as described above.
Furthermore, the test mode of the test equipment comprises full-automatic test and manual test; wherein the DRAM memory speed may reach 3.2 GBits/sec.
The invention has the beneficial effects that: firstly, a full address test space is realized by Double Rank Size before address mapping is established and memory capacity is calculated, so that the mapped and calculated memory capacity is twice of the actual capacity of DRAM x16 particles; secondly, closing Bank XOR Enable when address mapping is carried out so as to avoid the influence of address conversion on Bank calculation; then closing the attribute of the Cache when establishing a memory page table in the firmware; and finally, detecting the DRAM x16 particles to acquire error information of the DRAM x16 particles. The method can detect the DRAM x16 particle type and acquire the error information of the DRAM x16 particle type, thereby improving the service performance of the DRAM.
Drawings
FIG. 1 is a schematic flow chart of a test method for supporting DRAM x16 particles according to the present invention;
FIG. 2 is a block diagram of a testing apparatus supporting DRAM x16 particles according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments obtained by a person skilled in the art based on the embodiments in the present specification without any inventive step are within the scope of protection of the present specification.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Example one
In the embodiment of the present invention, it should be noted that, since there is only one physical connection line for the DRAM x16 granule Bank Group, and there are 2 physical connection lines for the DRAM x4/x8 granule Bank Group, when the DRAM x16 granule is regarded as the DRAM x8 granule to perform a test, it is necessary to avoid accessing the physical connection line at the higher level of the Bank Group when accessing the DRAM x16 granule, so as to avoid illegally accessing an invalid address space. The specific implementation mode is as follows:
referring to fig. 1, a method for testing a memory supporting DRAM x16 grains, the method comprising:
in step S1, Double Rank Size, so that the mapped and calculated memory capacity is twice the actual capacity of the DRAM x16 particles, thereby implementing a full address test space.
In the embodiment of the invention, before testing the DRAM x16 granule, a DRAM x8 granule memory bar is used as a Base Module to guide the start test and enter the test program.
Step S2, closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 particle, and establishing address mapping for the DRAM x16 particle; the purpose of turning off Bank XOR Enable is to remove the influence of address translation on Bank calculation.
Step S3, setting page attributes, closing Cache attributes and establishing a memory page table;
in this embodiment of the present invention, preferably, the setting the page attribute, closing the Cache attribute, and establishing the memory page table includes:
A. initializing memory management, entering memory page table attribute setting, and closing Cache attributes;
B. establishing a memory page table; the memory page table includes a kernel memory page table and/or a user process memory page table.
Step S4, access the address space of the lower bits of the Bank Group of the DRAM x16 granule, and obtain the memory error information of the DRAM x16 granule.
In this embodiment of the present invention, preferably, the accessing the address space of the lower bits of the Bank Group of the DRAM x16 granule and the obtaining the memory error information of the DRAM x16 granule includes;
A. accessing the address space of the lower bits of the DRAM x16 grain Bank Group by using BTT test software;
B. sending a test instruction to the DRAM x16 pellet;
C. and detecting the DRAM x16 particles to obtain the memory error information of the DRAM x16 particles.
In the embodiment of the invention, the BTT test software comprises a BTT test architecture and a BTT test algorithm, wherein the BTT test algorithm works as an independent test unit in the BTT test architecture and aims to find out problematic memory errors; the BTT test architecture mainly starts from starting x86 CPU multi-core, initializes CPU, initializes interrupt mechanism, initializes memory controller, initializes memory management and the like, wherein a special software architecture added for DRAM x16 particles is in the memory management of the test, and when the test range is transmitted to each BTT test algorithm, a layer of memory management control is specially added to ensure that the test range transmitted to the BTT test algorithm is in an effective address space, thereby avoiding the BTT test algorithm from accessing illegal address space.
The invention has the beneficial effects that: firstly, a full address test space is realized by Double Rank Size before address mapping is established and memory capacity is calculated, so that the mapped and calculated memory capacity is twice of the actual capacity of DRAM x16 particles; secondly, closing Bank XOR Enable when address mapping is carried out so as to avoid the influence of address conversion on Bank calculation; then closing the attribute of the Cache when establishing a memory page table in the firmware; and finally, detecting the DRAM x16 particles to acquire error information of the DRAM x16 particles. The method can detect the DRAM x16 particle type and acquire the error information of the DRAM x16 particle type, thereby improving the service performance of the DRAM.
Example two
In the embodiment of the present invention, it should be noted that, since there is only one physical connection line for the DRAM x16 granule Bank Group, and there are 2 physical connection lines for the DRAM x4/x8 granule Bank Group, when the DRAM x16 granule is regarded as the DRAM x8 granule to perform a test, it is necessary to avoid accessing the physical connection line at the higher level of the Bank Group when accessing the DRAM x16 granule, so as to avoid illegally accessing an invalid address space. The specific implementation mode is as follows:
referring to fig. 2, the present invention further provides a testing apparatus 100 for supporting DRAM x16 granules, the apparatus 100 comprising:
and the capacity expansion unit 1 is used for Double Rank Size, so that the mapping and calculated memory capacity is twice of the actual capacity of the DRAM x16 particles, and a full address test space is realized.
In the embodiment of the invention, before testing the DRAM x16 granule, a DRAM x8 granule memory bar is used as a Base Module to guide the start test and enter the test program.
The address mapping unit 2 is used for closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain; the purpose of turning off Bank XOR Enable is to remove the influence of address translation on Bank calculation.
A page table establishing unit 3, configured to set a page attribute, close the Cache attribute, and establish a memory page table;
in this embodiment of the present invention, the page table establishing unit 3 includes:
a Cache attribute closing module 31, configured to initialize memory management, enter a memory page table attribute setting, and close a Cache attribute;
a page table establishing module 32, configured to establish a memory page table; the memory page table includes a kernel memory page table and/or a user process memory page table.
And the memory error acquisition unit 4 is configured to access the address space of the lower bits of the Bank Group of the DRAM x16 granule, and acquire the memory error information of the DRAM x16 granule.
Further, the memory error obtaining unit 3 includes:
an address space access module 41, configured to access an address space of lower bits of a Bank Group of the DRAM x16 grain by using BTT test software;
a test command sending module 42, configured to send a test command to the DRAM x16 granule;
an error information obtaining module 43, configured to detect the DRAM x16 granule, and obtain the memory error information of the DRAM x16 granule.
In the embodiment of the invention, the BTT test software comprises a BTT test architecture and a BTT test algorithm, wherein the BTT test algorithm works as an independent test unit in the BTT test architecture and aims to find out problematic memory errors; the BTT test architecture mainly starts from starting x86 CPU multi-core, initializes CPU, initializes interrupt mechanism, initializes memory controller, initializes memory management and the like, wherein a special software architecture added for DRAM x16 particles is in the memory management of the test, and when the test range is transmitted to each BTT test algorithm, a layer of memory management control is specially added to ensure that the test range transmitted to the BTT test algorithm is in an effective address space, thereby avoiding the BTT test algorithm from accessing illegal address space.
The invention has the beneficial effects that: firstly, a Double Rank Size is established before address mapping is established and memory capacity is calculated through a capacity expansion unit 1, so that the mapped and calculated memory capacity is twice of the actual capacity of DRAM x16 particles, and a full address test space is realized; secondly, the address mapping unit 2 closes Bank XOR Enable when performing address mapping so as to avoid the influence of address conversion on Bank calculation; then closing the attribute of the Cache when establishing a memory page table in the firmware; finally, the page table establishing unit 3 detects the DRAM x16 granules to obtain the error information thereof. The method can detect the DRAM x16 particle type and acquire the error information of the DRAM x16 particle type, thereby improving the service performance of the DRAM.
EXAMPLE III
The invention also provides a test device of the DRAM memory, which comprises a test host used for test control and a test interface board used for providing a test interface of the DRAM memory; the test host writes a program for executing a test method supporting DRAM x16 granules as described above.
In the embodiment of the invention, the test mode of the test equipment comprises full-automatic test and manual test; wherein the DRAM memory speed may reach 3.2 GBits/sec.
In the embodiment of the invention, the testing method supporting DRAM x16 particles can be operated by a computer device comprising a memory, a processor and a network interface; the computer equipment can be a terminal or a server, wherein the terminal can be an electronic equipment with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant and a wearable equipment. The server may be an independent server or a server cluster composed of a plurality of servers. The memory may include, among other things, a non-volatile storage medium and an internal memory. The processor is used to provide computational and control capabilities to support the operation of the overall computer device. The network interface is used for network communication with other devices.
It should be understood that in the embodiments of the present Application, the Processor may be a central processing unit, and the Processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that, when executed by a processor, implement the above-described testing method for supporting DRAM x16 pellets. The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention encompass such modifications and variations as would be within the scope of the present claims and their equivalents if the testing of particles or modules of X16 were performed in a similar manner on any board or instrument that does not support access to particles of the X16 type.
Claims (8)
1. A method for testing DRAM x16 dice, wherein a DRAM x8 dice memory bank is used as a Base Module to conduct a start test before testing DRAM x16 dice, the method comprising:
closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain;
setting page attributes, closing Cache attributes, and establishing a memory page table;
accessing the address space of the lower bits of the Bank Group of the DRAM x16 grain to acquire the memory error information of the DRAM x16 grain;
the closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 granule, and before establishing address mapping for the DRAM x16 granule, further comprising:
double Rank Size, so that the mapping and the calculated memory capacity are twice the actual capacity of the DRAM x16 particles, and a full address test space is realized.
2. The method as claimed in claim 1, wherein the setting of page attributes, closing of Cache attributes and establishing of the in-memory page table includes:
initializing memory management, entering memory page table attribute setting, and closing Cache attributes;
establishing a memory page table; the memory page table includes a kernel memory page table and/or a user process memory page table.
3. The method for supporting the testing of the DRAM x16 granule as claimed in claim 1, wherein said accessing the address space of the lower bits of the Bank Group of the DRAM x16 granule and obtaining the memory error information of the DRAM x16 granule comprises;
accessing the address space of the lower bits of the DRAM x16 grain Bank Group by using BTT test software;
sending a test instruction to the DRAM x16 granule;
and detecting the DRAM x16 particles to obtain the memory error information of the DRAM x16 particles.
4. A test apparatus for supporting DRAM x16 pellets, the apparatus comprising:
the address mapping unit is used for closing Bank XOR Enable, calculating the memory capacity of the DRAM x16 grain, and establishing address mapping for the DRAM x16 grain;
the page table establishing unit is used for setting page attributes, closing Cache attributes and establishing a memory page table;
a memory error obtaining unit, configured to access an address space of a lower bit of a Bank Group of the DRAM x16 granule, and obtain memory error information of the DRAM x16 granule;
the device further comprises:
and the capacity expansion unit is used for Double Rank Size, so that the mapping and calculated memory capacity is twice of the actual capacity of the DRAM x16 particles, and a full address test space is realized.
5. The device of claim 4, wherein the page table setup unit comprises:
the Cache attribute closing module is used for initializing memory management, entering memory page table attribute setting and closing Cache attributes;
the page table establishing module is configured to establish a memory page table, where the memory page table includes a kernel memory page table and/or a user process memory page table.
6. The device of claim 4, wherein the memory error recovery unit comprises:
an address space access module, configured to access an address space of lower bits of a Bank Group of the DRAM x16 grain by using BTT test software;
the test instruction sending module is used for sending a test instruction to the DRAM x16 granules;
and the memory error acquisition module is used for detecting the DRAM x16 particles and acquiring the memory error information of the DRAM x16 particles.
7. A test apparatus for a DRAM memory, characterized by: the test system comprises a test host used for test control and a test interface board used for providing a DRAM test interface; the test host writes a program for executing a test method for supporting DRAM x16 granules according to any one of claims 1 to 3.
8. The test equipment for the DRAM memory according to claim 7, wherein the test mode of the test equipment comprises fully automatic test and manual test; wherein the DRAM memory speed may reach 3.2 GBits/sec.
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| CN104123234A (en) * | 2013-04-27 | 2014-10-29 | 华为技术有限公司 | Memory access method and memory system |
| CN105589770A (en) * | 2015-07-20 | 2016-05-18 | 杭州昆海信息技术有限公司 | Fault detection method and apparatus |
| CN111159005A (en) * | 2018-11-07 | 2020-05-15 | 珠海全志科技股份有限公司 | Method and system for testing memory management function |
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| CN104123234A (en) * | 2013-04-27 | 2014-10-29 | 华为技术有限公司 | Memory access method and memory system |
| CN105589770A (en) * | 2015-07-20 | 2016-05-18 | 杭州昆海信息技术有限公司 | Fault detection method and apparatus |
| CN111159005A (en) * | 2018-11-07 | 2020-05-15 | 珠海全志科技股份有限公司 | Method and system for testing memory management function |
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Denomination of invention: Supporting testing methods and devices for DRAM x16 particles, as well as testing equipment for DRAM memory Granted publication date: 20211228 Pledgee: Shenzhen Branch of China Merchants Bank Co.,Ltd. Pledgor: Huanghu Testing Technology (Shenzhen) Co.,Ltd. Registration number: Y2024980042084 |