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CN112636708B - Carrier aggregation power amplifying circuit based on double switch capacitors and electronic equipment - Google Patents

Carrier aggregation power amplifying circuit based on double switch capacitors and electronic equipment Download PDF

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Publication number
CN112636708B
CN112636708B CN202011440355.4A CN202011440355A CN112636708B CN 112636708 B CN112636708 B CN 112636708B CN 202011440355 A CN202011440355 A CN 202011440355A CN 112636708 B CN112636708 B CN 112636708B
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transistor
phase
power amplifier
switch
signal
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CN112636708A (en
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李科举
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Fuman Microelectronics Group Co ltd
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Fuman Microelectronics Group Co ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides a carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment, wherein the carrier aggregation power amplification circuit based on double switch capacitors comprises a first switch capacitor power amplifier, a second switch capacitor power amplifier, a balun impedance transformer and an antenna, wherein two ends of the first switch capacitor power amplifier are respectively connected with a first input node and a first end of a primary coil of the balun impedance transformer; two ends of the second switched capacitor power amplifier are respectively connected with a second input node and a second end of the primary coil of the balun impedance transformer; two ends of a secondary coil of the balun impedance transformer are respectively connected with the antenna and the ground; the first input node is used for receiving a first input signal, and the second input node is used for receiving a second input signal; the first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies.

Description

Carrier aggregation power amplifying circuit based on double switch capacitors and electronic equipment
Technical Field
The present invention relates to the field of wireless communications, and in particular, to a carrier aggregation power amplifying circuit based on dual switch capacitors and an electronic device.
Background
Carrier aggregation (CarrierAggregation, CA for short) is a key technology in modern wireless communication systems because it enables a wider transmission Bandwidth (BW) with multiple concurrent channels across the fragmented spectrum. For example, IEEE 802.11ac supports aggregation of multiple WLAN channels, where the maximum bandwidth of each channel is 160MHz in the 5GHz band, and up to five channels (20 MHz per channel) can be aggregated when the total channel bandwidth is 100MHz in LTE-Advanced (LTE-a for short). With the development of 5G technology becoming more mature, the communication technology is more convenient and fast, and the peak-to-average power ratio (Peak to Average Power Ratio, abbreviated as PAPR) of signals is greatly improved compared with the previous indexes such as 4G, and the requirements on carrier aggregation technology are higher and higher, so that a radio frequency power amplifier with stronger performance is required to support the transmission of high-speed data.
In the prior art, the scheme for realizing carrier aggregation mainly comprises the following steps:
(1) Two independent power amplifier channels, the transmitter can include two radio frequency power amplifiers of the narrow-band channel, the baseband pre-Power Amplifier (PA) of the single broadband digital-to-analog converter (D/A converter, DAC for short) is used to combine or two single-channel radio frequency power amplifiers output and combine the frequency bands, but the linearity is limited, and the requirement of 5G communication is difficult to bear;
(2) Two-dimensional digital predistortion (2D-Digital Predistortion, abbreviated as 2D-DPD) techniques, due to strong coupling between the two channels, result in performance degradation, unwanted in-band and out-of-band (Out ofBand, abbreviated as OOB) intermodulation and intermodulation distortion frequency products, limited to in-band linearization, especially for widely spaced channels, because the entire third order distortion spectrum cannot be covered;
(3) Analog compensation signal injection techniques, combining relatively complex analog schemes with additional Radio Frequency (RF) components and feedback loops, are complex in circuitry, and are limited to in-band linearization only;
(4) The analog signal injection technique for out-of-band data (Out ofBand, abbreviated as OOB) third-order intermodulation distortion suppression is implemented in a current-mode post PA combining transmitter comprising two high-output-impedance PAs, and the high-impedance connection causes nonlinear interaction between the power amplifiers, which requires a special linearization technique and a two-dimensional digital predistortion technique, and is difficult to implement.
Disclosure of Invention
The invention provides a carrier aggregation power amplifying circuit based on double switch capacitors and electronic equipment, which are used for solving the problems of nonlinear interaction, intermodulation distortion, complex circuit and high implementation difficulty in carrier aggregation.
According to a first aspect of the present invention, there is provided a carrier aggregation power amplification circuit based on a dual switched capacitor, comprising a first switched capacitor power amplifier, a second switched capacitor power amplifier, a balun impedance transformer and an antenna, wherein an input end of the first switched capacitor power amplifier is connected with a first input node, and an output end of the first switched capacitor power amplifier is connected with a first end of a primary coil of the balun impedance transformer; the input end of the second switched capacitor power amplifier is connected with a second input node, and the output end of the second switched capacitor power amplifier is connected with the second end of the primary coil of the balun impedance transformer; one end of a secondary coil of the balun impedance transformer is connected with the antenna, and the other end of the secondary coil of the balun impedance transformer is connected with the ground;
the first input node is used for receiving a first input signal, and the second input node is used for receiving a second input signal;
the first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies.
Optionally, the first switched capacitor power amplifier includes a first transistor, a first load capacitor, and a first resistor; the second switched capacitor power amplifier comprises a second transistor, a second load capacitor and a second resistor;
The control electrode of the first transistor is connected with the first input node, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the first end of the primary coil of the balun impedance transformer, one end of the first load capacitor is connected with the second electrode of the first transistor, the other end of the first load capacitor is grounded, one end of the first resistor is connected with the second electrode of the first transistor, and the other end of the first resistor is grounded;
The control electrode of the second transistor is connected with the second input node, the first electrode of the second transistor is grounded, the second electrode of the second transistor is connected to the second end of the primary coil of the balun impedance transformer, one end of the second load capacitor is connected with the second electrode of the second transistor, the other end of the second load capacitor is grounded, one end of the second resistor is connected with the second electrode of the second transistor, and the other end of the second resistor is grounded.
Optionally, the carrier aggregation power amplifying circuit based on the double-switch capacitor further comprises a first switch, a second switch, a first impedance matching network and a second impedance matching network;
One end of the first switch is connected with the second pole of the first transistor, the other end of the first switch is connected with one end of the first impedance matching network, and the other end of the first impedance matching network is connected with the first end of the primary coil of the balun impedance transformer;
one end of the second switch is connected with a second pole of the second transistor, the other end of the second switch is connected with one end of the second impedance matching network, and the other end of the second impedance matching network is connected with a second end of the primary coil of the balun impedance transformer.
Optionally, the first impedance matching network includes M impedance matching units;
One end of the M impedance matching units connected in parallel is connected with the second end of the first switch and the first end of the primary coil of the balun impedance transformer, and the other end of the M impedance matching units connected in parallel is grounded; wherein M is an integer greater than or equal to 1.
Optionally, the second impedance matching network includes N impedance matching units;
one end of the N impedance matching units connected in parallel is connected with the second end of the second switch and the second end of the primary coil of the balun impedance transformer, and the other end of the N impedance matching units connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
Optionally, the carrier aggregation power amplifying circuit based on the double switch capacitors further comprises a phase control unit, a first phase shifter and a second phase shifter, wherein the phase control unit is respectively connected with a control end of the first phase shifter and a control end of the second phase shifter; a first end of the first phase shifter is connected with the first input node, and a second end of the first phase shifter is connected with a control electrode of the first transistor; the first end of the second phase shifter is connected with the second input node, and the second end of the second phase shifter is connected with the control electrode of the second transistor;
The phase control unit is used for:
generating a first phase control signal and a second phase control signal according to an input clock signal, sending the first phase control signal to the first phase shifter, and sending the second phase control signal to the second phase shifter;
the first phase shifter is configured to:
Adjusting the phase of the first input signal according to the first phase control signal, and sending the phase-adjusted first input signal to the control electrode of the first transistor;
The second phase shifter is configured to:
And adjusting the phase of the second input signal according to the second phase control signal, and sending the second input signal after phase adjustment to the control electrode of the second transistor.
Optionally, the phase control unit includes a phase controller, a first frequency divider and a second frequency divider; the phase controller is respectively connected with the input end of the first frequency divider and the input end of the second frequency divider, the output end of the first frequency divider is connected with the control end of the first phase shifter, and the output end of the second frequency divider is connected with the control end of the second phase shifter;
The phase controller is used for:
Generating a first clock signal with a first duty ratio according to the input clock signal and first phase information, and sending the first clock signal to the first frequency divider; the input clock signal is a signal of the first duty cycle;
Generating a second clock signal with the first duty ratio according to the input clock signal and second phase information, and sending the second clock signal to the second frequency divider;
The first frequency divider is used for:
Generating the first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter, wherein the first phase control signal is a signal with a second duty ratio;
The second frequency divider is used for:
Generating the second phase control signal according to the second clock signal, and sending the first phase control signal to the second phase shifter, wherein the second phase control signal is a signal with the second duty ratio; the second duty cycle is less than the first duty cycle.
Optionally, the carrier aggregation power amplifying circuit based on the double-switch capacitor further comprises an amplitude control unit, wherein the amplitude control unit is connected with the control electrode of the first transistor and the control electrode of the second transistor;
The amplitude control unit is used for controlling the signal amplitude of the control electrode of the first transistor and the control electrode of the second transistor.
Optionally, the magnetic core of the balun impedance transformer is 1500 μm, the resonance frequency of the balun impedance transformer is 2.4GHz, and the turns ratio of the primary coil and the secondary coil of the balun impedance transformer is 1:2.
According to a second aspect of the present invention, there is provided an electronic device comprising the dual switched capacitor based carrier aggregation power amplifying circuit of the first aspect of the present invention and alternatives thereof.
According to the carrier aggregation power amplification circuit and the electronic equipment based on the double-switch capacitors, the two switch capacitor power amplifiers (SWITCHING CAPACITORPOWER AMPLIFIER, SCPA for short) independently operate and do not interfere with each other, so that the interaction between the two switch capacitor power amplifiers is low, the nonlinear interaction in concurrent double-frequency operation is reduced, and the carrier aggregation power amplification circuit and the electronic equipment have a good inhibition effect on intermodulation distortion.
In the alternative scheme of the invention, the two impedance matching networks are included, so that the signal loss caused by reflection of the signal in the transmission process can be reduced.
In the alternative scheme of the invention, the phase control unit and the amplitude control unit are adopted to control the output power of the switched capacitor power amplifier, so that nonlinear interaction between the two switched capacitor power amplifiers can be reduced, and intermodulation distortion is restrained.
In an alternative of the invention, a balun impedance transformer is used to resonate at 2.4GHz, and the turns ratio of the primary coil to the secondary coil is 1:2, combining parasitic parameters introduced by the two switched capacitor power amplifiers, converting the antenna impedance into constant impedance, so that the switched capacitor power amplifiers are matched with the output ports.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 5 is a schematic diagram II of a carrier aggregation power amplifier circuit based on a double-switch capacitor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram III of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 7 is a circuit diagram of a carrier aggregation power amplifier circuit based on a dual switch capacitor according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 9 is a schematic diagram showing a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 10 is a schematic diagram showing a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a carrier aggregation power amplifier circuit based on dual switch capacitors according to an embodiment of the present invention;
Reference numerals illustrate:
1-a first impedance matching network;
2-a second impedance matching network;
a 3-phase control unit;
4-a first phase shifter;
5-a second phase shifter;
6-an amplitude control unit;
31-a phase controller;
32-a first frequency divider;
33-a second frequency divider;
SCPA 1-a first switched capacitor power amplifier;
SCPA 2-second switched capacitor power amplifier;
A T-balun impedance transformer;
IN 1-a first input node;
IN 2-a second input node;
IN 3-an input clock signal;
an ANT-antenna;
N1-a first transistor;
C1-a first load capacitance;
R1-a first resistor;
S1-a first switch;
an N2-second transistor;
C2-a second load capacitance;
r2-a second resistor;
S2-a second switch;
an 11-impedance matching unit;
a 21-impedance matching unit;
zs 1-switch;
zs 2-switch;
zc 1-capacitance;
Zc 2-capacitance;
zr 1-resistance;
zr 2-resistance.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
The carrier aggregation power amplification circuit based on the double-switch capacitor according to the embodiment of the invention is mainly applied to the field of wireless communication, and meanwhile, the possibility of applying the carrier aggregation power amplification circuit to other scenes is not excluded.
Referring to fig. 1, an embodiment of the present invention provides a carrier aggregation power amplification circuit based on dual switch capacitors, which includes a first switch capacitor power amplifier SCPA1, a second switch capacitor power amplifier SCPA2, a balun impedance transformer T and an antenna ANT, wherein an input end of the first switch capacitor power amplifier SCPA1 is connected to a first input node IN1, and an output end of the first switch capacitor power amplifier SCPA1 is connected to a first end of a primary coil of the balun impedance transformer T; the input end of the second switched capacitor power amplifier SCPA2 is connected with a second input node IN1, and the output end of the second switched capacitor power amplifier SCPA2 is connected with the second end of the primary coil of the balun impedance transformer T; one end of a secondary coil of the balun impedance transformer T is connected with an antenna ANT, and the other end of the secondary coil of the balun impedance transformer T is connected with ground;
the first input node IN1 is for receiving a first input signal, and the second input node IN2 is for receiving a second input signal;
The first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2 operate at different carrier frequencies.
The first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2 work on different carrier frequencies, that is, the working frequency ranges of the two switched capacitor power amplifiers are different, and the final carrier aggregation is realized by adopting the power amplifiers with different working frequency ranges and matching with balun resistance and a transformer T.
The balun impedance transformer T can synthesize and output signals amplified by the first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2, so as to implement carrier aggregation, and then transmit the signals through the antenna ANT.
The two switch capacitor power amplifiers independently operate without interference, so that the interaction between the two switch capacitor power amplifiers is lower, nonlinear interaction in concurrent double-frequency operation is reduced, and the two switch capacitor power amplifiers have a good inhibition effect on intermodulation distortion.
In one example, the impedance of the antenna ANT is 50Ω.
In one embodiment, the core of the balun transformer T is 1500 μm, the resonance frequency of the balun transformer T is 2.4GHz, and the turns ratio of the primary winding to the secondary winding of the balun transformer T is 1:2.
Taking the antenna ANT impedance as 50 Ω as an example, the core size of the balun transformer is 1500 μm, which is balanced with the power added efficiency (PowerAdded Efficiency, abbreviated as PAE) loss, and the loss is reduced as much as possible under the condition of ensuring the size as small as possible, and the PAE loss is 0.8dB under the size. The total capacitance introduced at the same time was 20pF. The balun impedance transformer was used to resonate at 2.4GHz with a primary to secondary turns ratio of 1:2, combining parasitic parameters introduced by each switch capacitor power amplifier, converting the 50Ω antenna into differential 8Ω impedance, so that the switch capacitor power amplifier is matched with the output port.
The power added efficiency is understood to be the ratio of the output power of the power amplifier to the dissipated dc power.
Referring to fig. 2 to 3, the first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2 can control their own on-off, signals are transmitted in a voltage mode, and the two switched capacitor power amplifiers are used as series load impedances, and each switched capacitor power amplifier supplies power to its corresponding load. Ideally, for the balun impedance transformer T on-resistance, the switched capacitor power amplifier and the output are completely shorted, which means that each switched capacitor power amplifier operates independently without interfering with the other switched capacitor power amplifier, thereby greatly reducing the interaction between the two channels and minimizing nonlinear interactions in concurrent dual frequency operation.
Specifically, referring to fig. 2, taking the second switched capacitor power amplifier SCPA2 in the off state as an example, when the second switched capacitor power amplifier SCPA2 is in the off state, it is equivalent to only the first switched capacitor power amplifier SCPA1 working, and the output end of the first switched capacitor power amplifier SCPA1 is connected to the ground through the primary winding of the balun impedance transformer T, that is, the first switched capacitor power amplifier SCPA1 independently operates at this time, so as to realize power amplification without disturbing the working of the second switched capacitor power amplifier SCPA 2. The same applies when the first switched capacitor power amplifier SCPA1 is in the off state.
Referring to fig. 4, in one embodiment, the first switched capacitor power amplifier SCPA1 includes a first transistor N1, a first load capacitor C1, and a first resistor R1; the second switched capacitor power amplifier SCPA2 comprises a second transistor N2, a second load capacitor C2 and a second resistor R2;
The control electrode of the first transistor N1 is connected with the first input node IN1, the first electrode of the first transistor N1 is grounded, the second electrode of the first transistor N1 is connected with the first end of the primary coil of the balun impedance transformer T, one end of the first load capacitor C1 is connected with the third electrode of the first transistor N1, the other end of the first load capacitor C1 is grounded, one end of the first resistor R1 is connected with the third electrode of the first transistor N1, and the other end of the first resistor R1 is grounded;
The control electrode of the second transistor N2 is connected with the second input node IN2, the first electrode of the second transistor N2 is grounded, the second electrode of the second transistor N2 is connected with the second end of the primary coil of the balun impedance transformer T, one end of the second load capacitor C2 is connected with the second electrode of the second transistor N2, the other end of the second load capacitor C2 is grounded, one end of the second resistor R2 is connected with the second electrode of the second transistor N2, and the other end of the second resistor R2 is grounded.
In one example, the first transistor N1 and the second transistor N2 are not identical, and the types and parameters of the first load capacitor C1, the first resistor R1, the second load capacitor C2, and the second resistor R2 are identical; in another example, the first transistor N1 and the second transistor N2 are not identical, and the types and parameters of the first load capacitor C1, the first resistor R1, the second load capacitor C2, and the second resistor R2 are not identical.
In one embodiment, the first transistor N1 and the second transistor N2 are 65 nm CMOS manufactured by taiwan integrated circuit manufacturing company, inc.
In the illustrated example, the first transistor N1 and the second transistor N2 are NMOS, and the control electrodes of the first transistor N1 and the second transistor N2 may be understood as gates of the first transistor N1 and the second transistor N2, and the first electrodes of the first transistor N1 and the second transistor N2 are sources of the first transistor N1 and the second transistor N2; the second electrodes of the first and second transistors N1 and N2 are drains of the first and second transistors N1 and N2.
Referring to fig. 5, in one embodiment, the circuit further includes a first switch S1, a second switch S2, a first impedance matching network 1, and a second impedance matching network 2;
The first end of the first switch S1 is connected with the second pole of the first transistor N1, the second end of the first switch S1 is connected with one end of the first impedance matching network 1, and the other end of the first impedance matching network 1 is connected with the first end of the primary coil of the balun impedance transformer T.
The first end of the second switch S2 is connected with the second pole of the second transistor N2, the second end of the second switch S2 is connected with one end of the second impedance matching network 2, and the other end of the second impedance matching network 2 is connected with the second end of the primary coil of the balun impedance transformer T.
Referring to fig. 6, in one embodiment, the first impedance matching network 1 includes M impedance matching units 11;
One end of the M impedance matching units 11 connected in parallel is connected to the first end of the first switch S1 and the first end of the primary coil of the balun impedance transformer T, and the other end of the M impedance matching units 11 connected in parallel is grounded; wherein M is an integer greater than or equal to 1.
In one embodiment, the second impedance matching network 2 includes N impedance matching units 21;
One end of the N impedance matching units 21 connected in parallel is connected with the first end of the second switch S2 and the second end of the primary coil of the balun impedance transformer T, and the other end of the N impedance matching units 21 connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
Referring to fig. 7, any one of the impedance matching units (e.g., the impedance matching unit 21, the impedance matching unit 11) includes a switch, a capacitor, and a resistor, for example, one of the impedance matching units 11 includes a switch Zs1, a capacitor Zc1, and a resistor Zr1, and the impedance matching unit 21 includes a switch Zs2, a capacitor Zc2, and a resistor Zr2.
The output capacitance can be adjusted by selecting to turn on or off the impedance matching unit, and the resonance frequency of the power amplifier can be selected by utilizing the inductance value of the balun impedance transformer T.
The first impedance matching network 1 and the second impedance matching network 2 can reduce signal reflection during transmission, resulting in signal loss.
Referring to fig. 8, in one embodiment, the carrier aggregation power amplifying circuit based on the dual switch capacitor further includes a phase control unit 3, a first phase shifter 4 and a second phase shifter 5, where the phase control unit 3 is connected to a control end of the first phase shifter 4 and a control end of the second phase shifter 5 respectively; a first end of the first phase shifter 4 is connected with the first input node IN1, and a second end of the first phase shifter 4 is connected with a control electrode of the first transistor N1; a first end of the second phase shifter 5 is connected with the second input node IN2, and a second end of the second phase shifter 5 is connected with a control electrode of the second transistor N2;
The phase control unit 3 is configured to:
Generating a first phase control signal and a second phase control signal according to an input clock signal IN3, sending the first phase control signal to a first phase shifter 4, and sending the second phase control signal to a second phase shifter 5;
the first phase shifter 4 is for:
adjusting the phase of the first input signal according to the first phase control signal, and transmitting the first input signal after phase adjustment to the control electrode of the first transistor N1;
The second phase shifter 5 is for:
the phase of the second input signal is adjusted according to the second phase control signal, and the second input signal with the adjusted phase is sent to the control electrode of the first transistor N2.
Referring to fig. 9, the phase control unit 3 includes a phase controller 31, a first frequency divider 32 and a second frequency divider 33; the phase controller 31 is respectively connected to the input end of the first frequency divider 32 and the input end of the second frequency divider 33, the output end of the first frequency divider 32 is connected to the control end of the first phase shifter 4, and the output end of the second frequency divider 33 is connected to the control end of the second phase shifter 5.
The phase controller 31 is configured to:
Generating a first clock signal with a first duty ratio according to the input clock signal IN3 and the first phase information, and transmitting the first clock signal to the first frequency divider 32; the input clock signal IN3 is a signal of a first duty cycle;
generating a second clock signal of the first duty ratio according to the input clock signal IN3 and the second phase information, and transmitting the second clock signal to the second frequency divider 33;
The first frequency divider 32 is configured to:
Generating a first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter 4, wherein the first phase control signal is a signal with a second duty ratio;
the second frequency divider 33 is configured to:
generating a second phase control signal according to the second clock signal, and transmitting the first phase control signal to the second phase shifter 5, wherein the second phase control signal is a signal with a second duty ratio; the second duty cycle is less than the first duty cycle.
In one example, the first duty cycle is 50% duty cycle, the second duty cycle is 25% duty cycle, i.e. the first phase control signal and the second phase control signal are phase control signals with 25% duty cycle, which may make the operating bandwidth of the power amplifying circuit larger and PAE higher. In other examples, the first duty cycle and the second duty cycle may be selected to have other values.
In one embodiment, the phase controller 31 may employ a 4-bit digital timing controller with an adjustment range of 80 picoseconds and a resolution of 5 picoseconds, which may allow timing synchronization over the entire frequency and allow full period tuning of 2.4 GHz. Wherein the 4-bit digital timing controller can be controlled based on the 4-bit control code.
Referring to fig. 10, in one embodiment, the carrier aggregation power amplifying circuit based on the dual switch capacitor further includes an amplitude control unit 6, where the amplitude control unit 6 is connected to the control electrode of the first transistor N1 and the control electrode of the second transistor N2;
The amplitude control unit 6 may be configured to control the gate of the first transistor and the signal amplitude of the gate of the second transistor, for example, the amplitude of the phase-adjusted first input signal and the phase-adjusted second input signal.
In one embodiment, the amplitude control unit 6 uses an 11-bit controller for amplitude control, and the layout placement uses a temperature mode arrangement (i.e., mos transistors, resistors, inductors, capacitors, uniform arrangement, and substantially identical device density on the chip) to minimize nonlinearity. Wherein the 11-bit controller can control based on the 11-bit control code.
Referring to fig. 11, taking the first switched capacitor power amplifier SCPA1 as an example, the working procedure of one embodiment of the present invention is as follows:
The first input signal is input from a first input node IN1, is transmitted to a first phase shifter 4, a 4-bit time sequence controller generates first phase information, controls an input clock signal IN3 with 50% duty ratio to carry out phase adjustment, and is adjusted to be a first clock signal, the first clock signal is divided by a first frequency divider 32 with 25% duty ratio to generate a first phase control signal with 25% duty ratio, and the first phase control signal is transmitted to the first phase shifter 4 to carry out phase adjustment on the first input signal;
The phase-adjusted first input signal is subjected to amplitude control through an 11-bit controller and then is transmitted to a grid electrode of a first transistor N1, the signal is subjected to power amplification through a switched capacitor power amplifier consisting of the first transistor N1, a first load capacitor C1 and a first resistor R1, then is transmitted to a first impedance matching network for impedance matching after passing through a first switch S1, the impedance-matched signal is transmitted to a first end of a primary coil of a balun impedance transformer T, and is subjected to carrier aggregation through the balun impedance transformer T together with a signal transmitted by a second impedance matching network, and the aggregated signal is transmitted through an antenna ANT.
Wherein the linear operation is achieved by a low output impedance of the switched capacitor power amplifier and an output impedance independent of the digital code word, such that the non-linear intermodulation effect between the switched capacitor power amplifiers constituting the transmitter is reduced. A signal with a center frequency of 2.4ghz and a 3db bandwidth of 600MHz for the transmitter operating band can reach a peak PAE of 18.5% at a maximum output power of 19 dBm. In the carrier interval range of more than 250MHz, the rejection performance of the carrier to the third-order intermodulation distortion components is more than 40dBc when the power compensation is 9 dB.
Since all switches in this embodiment are always connected to signal ground, the impedance seen from the output is constant regardless of its on/off state, and this effective impedance value is equal to R1/N. The balun impedance transformer was used to resonate at 2.4GHz with a primary to secondary turns ratio of 1:2, combining parasitic parameters introduced by each switch capacitor power amplifier, converting the 50 omega antenna into a differential resistance of 8 omega, so that the switch capacitor power amplifier is matched with an output port.
In the specific embodiment of the invention, the output power control of the switched capacitor power amplifier is regulated by a digital control code, and the amplitude control part and the phase control part are used for jointly controlling in a matched mode.
The carrier aggregation power amplifying circuit based on the double-switch capacitor provided by the embodiment of the invention has the advantages that the two paths of power amplifiers controlled by the switch capacitor independently operate and do not interfere with each other, so that the interaction between the two channels is relatively low, the nonlinear interaction in the concurrent double-frequency operation is reduced to the greatest extent, and the carrier aggregation power amplifying circuit has a good inhibition effect on intermodulation distortion; the balun transformer is used as output matching, and the input branch is controlled by the digital code, so that the output impedance can be constant, and the output impedance is always kept at the optimal impedance.
The embodiment of the invention also provides electronic equipment, which comprises the carrier aggregation power amplifying circuit based on the double-switch capacitor.
The above electronic device may be any electronic device with a communication function, for example, may be a mobile phone, a tablet computer, a computer, an intelligent wearable device, a network device, a vehicle-mounted device, an internet of things device, and other devices dedicated to communication or not dedicated to communication, and so on.
In the description of the present specification, reference to the description of the terms "one embodiment," "one embodiment," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (8)

1. The carrier aggregation power amplification circuit based on the double-switch capacitor is characterized by comprising a first switch capacitor power amplifier, a second switch capacitor power amplifier, a balun impedance transformer, an antenna, a phase control unit, a first phase shifter and a second phase shifter, wherein the input end of the first switch capacitor power amplifier is connected with a first input node, and the output end of the first switch capacitor power amplifier is connected with the first end of a primary coil of the balun impedance transformer; the input end of the second switched capacitor power amplifier is connected with a second input node, and the output end of the second switched capacitor power amplifier is connected with the second end of the primary coil of the balun impedance transformer; one end of a secondary coil of the balun impedance transformer is connected with the antenna, and the other end of the secondary coil of the balun impedance transformer is connected with the ground;
the phase control unit is respectively connected with the control end of the first phase shifter and the control end of the second phase shifter; a first end of the first phase shifter is connected with the first input node, and a second end of the first phase shifter is connected with a first pole of a first transistor; the first end of the second phase shifter is connected with the second input node, and the second end of the second phase shifter is connected with the control electrode of the second transistor;
the first input node is used for receiving a first input signal, and the second input node is used for receiving a second input signal;
The first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies;
The first switched capacitor power amplifier comprises: a first transistor, a first load capacitance, and a first resistance; the second switched capacitor power amplifier comprises: a second transistor, a second load capacitance, and a second resistance;
The control electrode of the first transistor is connected with the first input node, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the first end of the primary coil of the balun impedance transformer, one end of the first load capacitor is connected with the second electrode of the first transistor, the other end of the first load capacitor is grounded, one end of the first resistor is connected with the second electrode of the first transistor, and the other end of the first resistor is grounded;
The control electrode of the second transistor is connected with the second input node, the first electrode of the second transistor is grounded, the second electrode of the second transistor is connected to the second end of the primary coil of the balun impedance transformer, one end of the second load capacitor is connected with the second electrode of the second transistor, the other end of the second load capacitor is grounded, one end of the second resistor is connected with the second electrode of the second transistor, and the other end of the second resistor is grounded;
The phase control unit is used for:
generating a first phase control signal and a second phase control signal according to an input clock signal, sending the first phase control signal to the first phase shifter, and sending the second phase control signal to the second phase shifter;
the first phase shifter is configured to:
Adjusting the phase of the first input signal according to the first phase control signal, and sending the phase-adjusted first input signal to the control electrode of the first transistor;
The second phase shifter is configured to:
And adjusting the phase of the second input signal according to the second phase control signal, and sending the second input signal after phase adjustment to the control electrode of the second transistor.
2. The dual switched-capacitor based carrier aggregation power amplifier circuit of claim 1, further comprising a first switch, a second switch, a first impedance matching network, and a second impedance matching network;
A first end of the first switch is connected with a second pole of the first transistor, a second end of the first switch is connected with one end of the first impedance matching network, and the other end of the first impedance matching network is connected with a first end of a primary coil of the balun impedance transformer;
The first end of the second switch is connected with the second pole of the second transistor, the second end of the second switch is connected with one end of the second impedance matching network, and the other end of the second impedance matching network is connected with the second end of the primary coil of the balun impedance transformer.
3. The dual switched-capacitor based carrier aggregation power amplifier circuit of claim 2, wherein the first impedance matching network comprises M impedance matching units;
One end of the M impedance matching units connected in parallel is connected with the second end of the first switch and the first end of the primary coil of the balun impedance transformer, and the other end of the M impedance matching units connected in parallel is grounded; wherein M is an integer greater than or equal to 1.
4. The dual switched-capacitor based carrier aggregation power amplifier circuit of claim 3, wherein said second impedance matching network comprises N impedance matching units;
one end of the N impedance matching units connected in parallel is connected with the second end of the second switch and the second end of the primary coil of the balun impedance transformer, and the other end of the N impedance matching units connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
5. The dual switched capacitor based carrier aggregation power amplifier circuit of claim 1, wherein the phase control unit comprises a phase controller, a first frequency divider and a second frequency divider; the phase controller is respectively connected with the input end of the first frequency divider and the input end of the second frequency divider, the output end of the first frequency divider is connected with the control end of the first phase shifter, and the output end of the second frequency divider is connected with the control end of the second phase shifter;
The phase controller is used for:
Generating a first clock signal with a first duty ratio according to the input clock signal and first phase information, and sending the first clock signal to the first frequency divider; the input clock signal is a signal of the first duty cycle;
Generating a second clock signal with the first duty ratio according to the input clock signal and second phase information, and sending the second clock signal to the second frequency divider;
The first frequency divider is used for:
Generating the first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter, wherein the first phase control signal is a signal with a second duty ratio;
The second frequency divider is used for:
Generating the second phase control signal according to the second clock signal, and sending the first phase control signal to the second phase shifter, wherein the second phase control signal is a signal with the second duty ratio; the second duty cycle is less than the first duty cycle.
6. The dual switched-capacitor based carrier aggregation power amplifier circuit according to any one of claims 1 to 4, further comprising an amplitude control unit connecting a control electrode of the first transistor and a control electrode of the second transistor;
The amplitude control unit is used for controlling the signal amplitude of the control electrode of the first transistor and the control electrode of the second transistor.
7. The carrier aggregation power amplification circuit according to any one of claims 1 to 4, wherein the core of the balun impedance transformer is 1500 μm, the resonance frequency of the balun impedance transformer is 2.4GHz, and the turns ratio of the primary coil and the secondary coil of the balun impedance transformer is 1:2.
8. An electronic device comprising the dual switched capacitor based carrier aggregation power amplifier circuit of any one of claims 1 to 7.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105305973A (en) * 2015-11-30 2016-02-03 北京机械设备研究所 Low-distortion MOSFET high-power amplification circuit
CN108270407A (en) * 2016-12-30 2018-07-10 通用电气公司 A kind of planar Balun and a kind of multilayer circuit board
CN111600559A (en) * 2020-06-16 2020-08-28 锐石创芯(深圳)科技有限公司 Power amplifier output matching circuit, radio frequency front end module and wireless device
CN213783259U (en) * 2020-12-10 2021-07-23 富满微电子集团股份有限公司 Carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7129803B2 (en) * 2004-03-16 2006-10-31 Broadcom Corporation Tuned transformer balun circuit and applications thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105305973A (en) * 2015-11-30 2016-02-03 北京机械设备研究所 Low-distortion MOSFET high-power amplification circuit
CN108270407A (en) * 2016-12-30 2018-07-10 通用电气公司 A kind of planar Balun and a kind of multilayer circuit board
CN111600559A (en) * 2020-06-16 2020-08-28 锐石创芯(深圳)科技有限公司 Power amplifier output matching circuit, radio frequency front end module and wireless device
CN213783259U (en) * 2020-12-10 2021-07-23 富满微电子集团股份有限公司 Carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment

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