CN112636708A - Carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment - Google Patents
Carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment Download PDFInfo
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Abstract
The invention provides a carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment, wherein the carrier aggregation power amplification circuit based on the double switch capacitors comprises a first switch capacitor power amplifier, a second switch capacitor power amplifier, a balun impedance transformer and an antenna, wherein two ends of the first switch capacitor power amplifier are respectively connected with a first input node and a first end of a primary coil of the balun impedance transformer; two ends of the second switched capacitor power amplifier are respectively connected with a second input node and a second end of the primary coil of the balun impedance transformer; two ends of a secondary coil of the balun impedance transformer are respectively connected with the antenna and the ground; the first input node is configured to receive a first input signal and the second input node is configured to receive a second input signal; the first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to a carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment.
Background
Carrier Aggregation (CA) is a key technology in modern wireless communication systems because it enables a wider transmission Bandwidth (BW) with multiple concurrent channels across a fragmented spectrum. For example, IEEE 802.11ac supports aggregation of multiple WLAN channels, with a maximum bandwidth of 160MHz per channel in the 5GHz band, and up to five channels (20 MHz per channel) in LTE-Advanced (LTE-a) with a total channel bandwidth of 100 MHz. With the development of the 5G technology becoming more mature, the communication technology becomes more convenient and faster at high speed, the Peak to Average Power Ratio (PAPR) is greatly improved compared with the previous indexes such as 4G, and the requirement for the carrier aggregation technology becomes higher and higher, so that a radio frequency Power amplifier with higher performance is required to support the transmission of high-speed data.
In the prior art, the scheme for implementing carrier aggregation mainly includes:
(1) the transmitter may include two radio frequency power amplifiers of narrow band channels, and a baseband pre-Power Amplifier (PA) using a single wideband digital-to-analog converter (D/a converter, DAC for short) is used to combine or two single channel radio frequency power amplifiers output and then combine frequency bands, but the linearity is limited, and it is difficult to bear the requirement of 5G communication;
(2) two-dimensional Digital Predistortion (2D-DPD) technique, which is limited to in-band linearization, especially for widely spaced channels, because it cannot cover the entire third-order distortion spectrum, results in performance degradation due to strong coupling between two channels, resulting in unwanted in-band and Out-of-band (OOB) intermodulation and intermodulation distortion frequency products;
(3) the analog compensation signal injection technology combines a relatively complex analog scheme with an additional Radio Frequency (RF) component and a feedback loop, and has a complex circuit which is limited to in-band linearization;
(4) an analog signal injection technology for Out of band (OOB) third-order intermodulation distortion suppression is realized in a current mode post-PA combined transmitter comprising two high-output impedance PAs, and the high-impedance connection can cause nonlinear interaction between power amplifiers, so that a special linearization technology and a two-dimensional digital predistortion technology are required, and the realization difficulty is high.
Disclosure of Invention
The invention provides a carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment, and aims to solve the problems of nonlinear interaction, intermodulation distortion, complex circuit and high implementation difficulty in carrier aggregation.
According to a first aspect of the present invention, a carrier aggregation power amplification circuit based on a dual-switched capacitor is provided, including a first switched capacitor power amplifier, a second switched capacitor power amplifier, a balun impedance transformer, and an antenna, where an input end of the first switched capacitor power amplifier is connected to a first input node, and an output end of the first switched capacitor power amplifier is connected to a first end of a primary coil of the balun impedance transformer; the input end of the second switched capacitor power amplifier is connected with a second input node, and the output end of the second switched capacitor power amplifier is connected with the second end of the primary coil of the balun impedance transformer; one end of a secondary coil of the balun impedance transformer is connected with the antenna, and the other end of the secondary coil of the balun impedance transformer is connected with the ground;
the first input node is configured to receive a first input signal and the second input node is configured to receive a second input signal;
the first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies.
Optionally, the first switched capacitor power amplifier includes a first transistor, a first load capacitor, and a first resistor; the second switch capacitor power amplifier comprises a second transistor, a second load capacitor and a second resistor;
a control electrode of the first transistor is connected to the first input node, a first electrode of the first transistor is grounded, a second electrode of the first transistor is connected to a first end of a primary coil of the balun impedance transformer, one end of the first load capacitor is connected to the second electrode of the first transistor, the other end of the first load capacitor is grounded, one end of the first resistor is connected to the second electrode of the first transistor, and the other end of the first resistor is grounded;
a control electrode of the second transistor is connected to the second input node, a first electrode of the second transistor is grounded, a second electrode of the second transistor is connected to the second end of the primary coil of the balun impedance transformer, one end of the second load capacitor is connected to the second electrode of the second transistor, the other end of the second load capacitor is grounded, one end of the second resistor is connected to the second electrode of the second transistor, and the other end of the second resistor is grounded.
Optionally, the carrier aggregation power amplifying circuit based on the double-switch capacitor further includes a first switch, a second switch, a first impedance matching network, and a second impedance matching network;
one end of the first switch is connected to the second pole of the first transistor, the other end of the first switch is connected to one end of the first impedance matching network, and the other end of the first impedance matching network is connected to the first end of the primary coil of the balun impedance transformer;
one end of the second switch is connected to the second pole of the second transistor, the other end of the second switch is connected to one end of the second impedance matching network, and the other end of the second impedance matching network is connected to the second end of the primary coil of the balun impedance transformer.
Optionally, the first impedance matching network includes M impedance matching units;
one end of the M impedance matching units after being connected in parallel is connected with the second end of the first switch and the first end of the primary coil of the balun impedance transformer, and the other end of the M impedance matching units after being connected in parallel is grounded; wherein M is an integer greater than or equal to 1.
Optionally, the second impedance matching network includes N impedance matching units;
one end of the N impedance matching units after being connected in parallel is connected with the second end of the second switch and the second end of the primary coil of the balun impedance transformer, and the other end of the N impedance matching units after being connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
Optionally, the carrier aggregation power amplification circuit based on a dual-switch capacitor further includes a phase control unit, a first phase shifter and a second phase shifter, where the phase control unit is connected to a control end of the first phase shifter and a control end of the second phase shifter respectively; a first end of the first phase shifter is connected with the first input node, and a second end of the first phase shifter is connected with a control electrode of the first transistor; a first end of the second phase shifter is connected with the second input node, and a second end of the second phase shifter is connected with a control electrode of the second transistor;
the phase control unit is configured to:
generating a first phase control signal and a second phase control signal according to an input clock signal, and transmitting the first phase control signal to the first phase shifter and the second phase control signal to the second phase shifter;
the first phase shifter is configured to:
adjusting the phase of the first input signal according to the first phase control signal, and sending the phase-adjusted first input signal to a control electrode of the first transistor;
the second phase shifter is configured to:
and adjusting the phase of the second input signal according to the second phase control signal, and sending the phase-adjusted second input signal to a control electrode of the second transistor.
Optionally, the phase control unit includes a phase controller, a first frequency divider, and a second frequency divider; the phase controller is respectively connected with the input end of the first frequency divider and the input end of the second frequency divider, the output end of the first frequency divider is connected with the control end of the first phase shifter, and the output end of the second frequency divider is connected with the control end of the second phase shifter;
the phase controller is configured to:
generating a first clock signal with a first duty ratio according to the input clock signal and first phase information, and sending the first clock signal to the first frequency divider; the input clock signal is a signal of the first duty ratio;
generating a second clock signal with the first duty ratio according to the input clock signal and second phase information, and sending the second clock signal to the second frequency divider;
the first frequency divider is configured to:
generating the first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter, wherein the first phase control signal is a signal with a second duty ratio;
the second frequency divider is configured to:
generating the second phase control signal according to the second clock signal, and sending the first phase control signal to the second phase shifter, wherein the second phase control signal is a signal with the second duty ratio; the second duty cycle is less than the first duty cycle.
Optionally, the carrier aggregation power amplification circuit based on a double-switch capacitor further includes an amplitude control unit, where the amplitude control unit is connected to the control electrode of the first transistor and the control electrode of the second transistor;
the amplitude control unit is used for controlling the signal amplitude of the control electrode of the first transistor and the control electrode of the second transistor.
Optionally, a magnetic core of the balun impedance transformer is 1500 μm, a resonant frequency of the balun impedance transformer is 2.4GHz, and a turn ratio of a primary coil and a secondary coil of the balun impedance transformer is 1: 2.
according to a second aspect of the present invention, there is provided an electronic device comprising the dual-switched-capacitor based carrier aggregation power amplification circuit according to the first aspect of the present invention and its alternatives.
According to the carrier aggregation power amplification circuit based on the double-switch capacitor and the electronic equipment, the two Switch Capacitor Power Amplifiers (SCPA) operate independently and do not interfere with each other, so that the interaction between the two switch capacitor power amplifiers is low, the nonlinear interaction in concurrent double-frequency operation is reduced, and the cross modulation distortion is well inhibited.
In the alternative of the invention, two impedance matching networks are included, so that the signal loss caused by the reflection of the signal in the transmission process can be reduced.
In the alternative scheme of the invention, the phase control unit and the amplitude control unit are adopted to control the output power of the switched capacitor power amplifier, which can help to reduce the nonlinear interaction between the two switched capacitor power amplifiers and inhibit intermodulation distortion.
In the alternative of the invention, a balun impedance transformer is used for resonance at 2.4GHz, and the turn ratio of the primary coil to the secondary coil is 1: 2, and combining the parasitic parameters introduced by the two switched capacitor power amplifiers, converting the antenna impedance into a constant impedance, so that the switched capacitor power amplifier is matched with the output port.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a first schematic diagram of a frame of a carrier aggregation power amplifying circuit based on a dual-switch capacitor according to an embodiment of the present invention;
fig. 2 is a second schematic diagram of a frame of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 3 is a third schematic diagram of a frame of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 4 is a first schematic diagram illustrating a configuration of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 5 is a second schematic structural diagram of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 6 is a third schematic diagram illustrating a configuration of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 7 is a circuit diagram of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 10 is a sixth schematic diagram illustrating a configuration of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
fig. 11 is a seventh schematic diagram illustrating a configuration of a carrier aggregation power amplifying circuit based on two switching capacitors according to an embodiment of the present invention;
description of reference numerals:
1-a first impedance matching network;
2-a second impedance matching network;
3-a phase control unit;
4-a first phase shifter;
5-a second phase shifter;
6-an amplitude control unit;
31-phase controller;
32-a first frequency divider;
33-a second frequency divider;
SCPA 1-first switched capacitor power amplifier;
SCPA 2-second switched capacitor power amplifier;
a T-balun impedance transformer;
IN1 — first input node;
IN2 — second input node;
IN3 — input clock signal;
an ANT-antenna;
n1 — first transistor;
c1 — first load capacitance;
r1 — first resistance;
s1 — a first switch;
n2 — second transistor;
c2 — second load capacitance;
r2 — second resistance;
s2 — a second switch;
11-an impedance matching unit;
21-an impedance matching unit;
zs 1-switch;
zs 2-switch;
zc 1-capacitance;
zc 2-capacitance;
zr 1-resistance;
zr 2-resistance.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
The carrier aggregation power amplifying circuit based on the double-switch capacitor is mainly applied to the field of wireless communication, meanwhile, the possibility of applying the carrier aggregation power amplifying circuit to other scenes is not eliminated, and in addition, the carrier aggregation power amplifying circuit based on the double-switch capacitor can form independent chips and devices and can also be a part of circuits of the whole chips and devices.
Referring to fig. 1, an embodiment of the invention provides a carrier aggregation power amplifying circuit based on dual switched capacitors, including a first switched capacitor power amplifier SCPA1, a second switched capacitor power amplifier SCPA2, a balun impedance transformer T, and an antenna ANT, where an input end of the first switched capacitor power amplifier SCPA1 is connected to a first input node IN1, and an output end of the first switched capacitor power amplifier SCPA1 is connected to a first end of a primary coil of the balun impedance transformer T; the input end of the second switched capacitor power amplifier SCPA2 is connected to the second input node IN1, and the output end of the second switched capacitor power amplifier SCPA2 is connected to the second end of the primary coil of the balun impedance transformer T; one end of a secondary coil of the balun impedance transformer T is connected with the antenna ANT, and the other end of the secondary coil of the balun impedance transformer T is connected with the ground;
a first input node IN1 for receiving a first input signal, a second input node IN2 for receiving a second input signal;
the first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2 operate at different carrier frequencies.
The first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2 work on different carrier frequencies, namely the working frequency bands of the two switched capacitor power amplifiers are different, and the power amplifiers with different working frequency bands are adopted to cooperate with a potential resistance [ P ] transformer T to realize final carrier aggregation.
The balun impedance transformer T may synthesize and output signals after power amplification by the first switched capacitor power amplifier SCPA1 and the second switched capacitor power amplifier SCPA2, implement carrier aggregation, and then transmit the signals through the antenna ANT.
The two switched capacitor power amplifiers run independently and do not interfere with each other, so that the interaction between the two switched capacitor power amplifiers is low, the reduction of the nonlinear interaction in concurrent dual-frequency operation is facilitated, and the cross modulation distortion is well inhibited.
In one example, the impedance of the antenna ANT is 50 Ω.
In one embodiment, the magnetic core of the balun impedance transformer T is 1500 μm, the resonant frequency of the balun impedance transformer T is 2.4GHz, and the turn ratio of the primary coil and the secondary coil of the balun impedance transformer T is 1: 2.
taking the antenna ANT impedance as 50 Ω as an example, the core size of the balun impedance transformer is 1500 μm, which is obtained by balancing the loss of power added Efficiency (PAE for short), and reducing the loss as much as possible under the condition of ensuring the size as small as possible, and the loss of the PAE under the size is 0.8 dB. While introducing a total capacitance of 20 pF. Using a balun impedance transformer to resonate at 2.4GHz, the turn ratio of the primary coil to the secondary coil is 1: 2, and combining the parasitic parameters introduced by each switched capacitor power amplifier, the 50 Ω antenna is converted to a differential 8 Ω impedance, so that the switched capacitor power amplifier is matched with the output port.
The power added efficiency is understood to be the ratio of the output power of the power amplifier to the dissipated dc power.
Referring to fig. 2 to 3, the first switch capacitor power amplifier SCPA1 and the second switch capacitor power amplifier SCPA2 can control their on/off states, signals are transmitted in a voltage mode, the two switch capacitor power amplifiers are used as series load impedances, and each switch capacitor power amplifier supplies power to its corresponding load by using the series impedances. Ideally, for the on-resistance of the balun impedance transformer T, the switched capacitor power amplifier is completely short-circuited with the output, which means that each switched capacitor power amplifier operates independently without interfering with the other switched capacitor power amplifier, thereby greatly reducing the interaction between the two channels and minimizing the nonlinear interaction in concurrent dual-frequency operation.
Specifically, referring to fig. 2, taking the second switch-capacitor power amplifier SCPA2 in the off state as an example, when the second switch-capacitor power amplifier SCPA2 is in the off state, it is equivalent to that only the first switch-capacitor power amplifier SCPA1 works, and the output terminal of the first switch-capacitor power amplifier SCPA1 is connected to the ground through the primary coil of the balun impedance transformer T, that is, at this time, the first switch-capacitor power amplifier SCPA1 operates independently, so that power amplification is realized, and the work of the second switch-capacitor power amplifier SCPA2 is not disturbed. The same applies when the first switched capacitor power amplifier SCPA1 is in the off state.
Referring to fig. 4, in one embodiment, the first switch capacitor power amplifier SCPA1 includes a first transistor N1, a first load capacitor C1, and a first resistor R1; the second switched capacitor power amplifier SCPA2 includes a second transistor N2, a second load capacitor C2, and a second resistor R2;
a control electrode of the first transistor N1 is connected to the first input node IN1, a first electrode of the first transistor N1 is grounded, a second electrode of the first transistor N1 is connected to a first end of the primary winding of the balun impedance transformer T, one end of the first load capacitor C1 is connected to the third electrode of the first transistor N1, the other end of the first load capacitor C1 is grounded, one end of the first resistor R1 is connected to the third electrode of the first transistor N1, and the other end of the first resistor R1 is grounded;
a control electrode of the second transistor N2 is connected to the second input node IN2, a first electrode of the second transistor N2 is grounded, a second electrode of the second transistor N2 is connected to the second end of the primary winding of the balun impedance transformer T, one end of the second load capacitor C2 is connected to the second electrode of the second transistor N2, the other end of the second load capacitor C2 is grounded, one end of the second resistor R2 is connected to the second electrode of the second transistor N2, and the other end of the second resistor R2 is grounded.
In an example, the first transistor N1 and the second transistor N2 are not identical, and the types and parameters of the first load capacitor C1, the first resistor R1, the second load capacitor C2 and the second resistor R2 are identical; in another example, the first transistor N1 and the second transistor N2 are not identical, and the types and parameters of the first load capacitor C1, the first resistor R1, the second load capacitor C2 and the second resistor R2 are not identical.
In one embodiment, the first transistor N1 and the second transistor N2 are 65 nm CMOS of Taiwan integrated circuit manufacturing, Inc. (Taiwan integrated Circuit, Inc.), and have a chip area of 1.6 mm.
In the illustrated example, the first transistor N1 and the second transistor N2 are NMOS transistors, and the control electrodes of the first transistor N1 and the second transistor N2 can be understood as the gates of the first transistor N1 and the second transistor N2, and the first electrodes of the first transistor N1 and the second transistor N2 are the sources of the first transistor N1 and the second transistor N2; the second poles of the first transistor N1 and the second transistor N2 are the drains of the first transistor N1 and the second transistor N2.
Referring to fig. 5, in one embodiment, the impedance matching circuit further includes a first switch S1, a second switch S2, a first impedance matching network 1 and a second impedance matching network 2;
a first terminal of the first switch S1 is connected to the second pole of the first transistor N1, a second terminal of the first switch S1 is connected to one terminal of the first impedance matching network 1, and the other terminal of the first impedance matching network 1 is connected to a first terminal of the primary winding of the balun impedance transformer T.
A first terminal of the second switch S2 is connected to the second pole of the second transistor N2, a second terminal of the second switch S2 is connected to one terminal of the second impedance matching network 2, and the other terminal of the second impedance matching network 2 is connected to a second terminal of the primary winding of the balun impedance transformer T.
Referring to fig. 6, in one embodiment, the first impedance matching network 1 includes M impedance matching units 11;
one ends of the M impedance matching units 11 connected in parallel are connected to the first end of the first switch S1 and the first end of the primary coil of the balun impedance transformer T, and the other ends of the M impedance matching units 11 connected in parallel are grounded; wherein M is an integer greater than or equal to 1.
In one embodiment, the second impedance matching network 2 comprises N impedance matching units 21;
one end of the N impedance matching units 21 connected in parallel is connected to the first end of the second switch S2 and the second end of the primary coil of the balun impedance transformer T, and the other end of the N impedance matching units 21 connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
Referring to fig. 7, any one of the impedance matching units (e.g., the impedance matching unit 21, the impedance matching unit 11) includes a switch, a capacitor and a resistor, for example, one of the impedance matching units 11 includes a switch Zs1, a capacitor Zc1 and a resistor Zr1, and the impedance matching unit 21 includes a switch Zs2, a capacitor Zc2 and a resistor Zr 2.
The output capacitance can be adjusted by selectively turning on or off the impedance matching unit, and the resonant frequency of the power amplifier can be selected by using the inductance value of the balun impedance transformer T.
The first impedance matching network 1 and the second impedance matching network 2 can reduce signal loss caused by signal reflection in the transmission process.
Referring to fig. 8, in an embodiment, the carrier aggregation power amplifying circuit based on a dual-switch capacitor further includes a phase control unit 3, a first phase shifter 4 and a second phase shifter 5, where the phase control unit 3 is connected to a control end of the first phase shifter 4 and a control end of the second phase shifter 5, respectively; a first terminal of the first phase shifter 4 is connected to the first input node IN1, and a second terminal of the first phase shifter 4 is connected to a control electrode of the first transistor N1; a first end of the second phase shifter 5 is connected to the second input node IN2, and a second end of the second phase shifter 5 is connected to the control electrode of the second transistor N2;
the phase control unit 3 is configured to:
generating a first phase control signal and a second phase control signal according to the input clock signal IN3, and transmitting the first phase control signal to the first phase shifter 4 and the second phase control signal to the second phase shifter 5;
the first phase shifter 4 is configured to:
adjusting the phase of the first input signal according to the first phase control signal, and sending the phase-adjusted first input signal to the control electrode of the first transistor N1;
the second phase shifter 5 is configured to:
the phase of the second input signal is adjusted according to the second phase control signal, and the phase-adjusted second input signal is sent to the gate of the first transistor N2.
Referring to fig. 9, the phase control unit 3 includes a phase controller 31, a first frequency divider 32 and a second frequency divider 33; the phase controller 31 is connected to the input terminal of the first frequency divider 32 and the input terminal of the second frequency divider 33, respectively, the output terminal of the first frequency divider 32 is connected to the control terminal of the first phase shifter 4, and the output terminal of the second frequency divider 33 is connected to the control terminal of the second phase shifter 5.
The phase controller 31 is configured to:
generating a first clock signal with a first duty ratio according to the input clock signal IN3 and the first phase information, and sending the first clock signal to the first frequency divider 32; the input clock signal IN3 is a signal of a first duty cycle;
generating a second clock signal with the first duty ratio according to the input clock signal IN3 and the second phase information, and sending the second clock signal to the second frequency divider 33;
the first frequency divider 32 is configured to:
generating a first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter 4, wherein the first phase control signal is a signal with a second duty ratio;
the second frequency divider 33 is configured to:
generating a second phase control signal according to the second clock signal, and sending the first phase control signal to the second phase shifter 5, wherein the second phase control signal is a signal with a second duty ratio; the second duty cycle is less than the first duty cycle.
In one example, the first duty cycle is 50% duty cycle, and the second duty cycle is 25% duty cycle, that is, the first phase control signal and the second phase control signal are phase control signals with 25% duty cycle, so that the operating bandwidth of the power amplification circuit can be larger, and the PAE is higher. In other examples, other values of the first duty cycle and the second duty cycle may be selected.
In one embodiment, the phase controller 31 may employ a 4-bit digital timing controller, the adjustment range of the 4-bit digital timing controller is 80 picoseconds, the resolution is 5 picoseconds, the timing over the entire frequency can be synchronized and full period tuning of 2.4GHz is allowed. Wherein, the 4-bit digital time schedule controller can be controlled based on the 4-bit control code.
Referring to fig. 10, in an embodiment, the carrier aggregation power amplifying circuit based on dual-switch capacitors further includes an amplitude control unit 6, where the amplitude control unit 6 connects a control electrode of the first transistor N1 and a control electrode of the second transistor N2;
the amplitude control unit 6 may be configured to control the signal amplitudes of the control electrodes of the first transistor and the second transistor, for example, to control the amplitudes of the phase-adjusted first input signal and the phase-adjusted second input signal.
In one embodiment, the amplitude control unit 6 uses 11-bit controller for amplitude control, and the layout arrangement uses a temperature mode arrangement (i.e., mos transistors, resistors, inductors, capacitors, uniform arrangement, and substantially the same device density on a chip), which can minimize non-linearity. Wherein the 11-bit controller can perform control based on the 11-bit control code.
Referring to fig. 11, taking the first switch-capacitor power amplifier SCPA1 as an example, an embodiment of the present invention operates as follows:
a first input signal is input from a first input node IN1, transmitted to a first phase shifter 4, a 4-bit timing controller generates first phase information, controls an input clock signal IN3 with a duty ratio of 50% to perform phase adjustment, and is adjusted to be a first clock signal, the first clock signal is subjected to frequency division by a first frequency divider 32 with a duty ratio of 25% to generate a first phase control signal with a duty ratio of 25%, and the first phase control signal is transmitted to the first phase shifter 4 to perform phase adjustment on the first input signal;
the first input signal after phase adjustment is subjected to amplitude control through an 11-bit controller, then is transmitted to a gate of a first transistor N1, the signal enters a switched capacitor power amplifier consisting of a first transistor N1, a first load capacitor C1 and a first resistor R1 to be subjected to power amplification, then is transmitted to a first impedance matching network for impedance matching after passing through a first switch S1, the signal after impedance matching is transmitted to a first end of a primary coil of a balun impedance transformer T, and is subjected to carrier aggregation through the balun impedance transformer T together with a signal transmitted by a second impedance matching network, and the aggregated signal is transmitted out through an antenna ANT.
The linear operation is achieved by the low output impedance of the switched capacitor power amplifier and the digital codeword independent output impedance, such that the non-linear intermodulation between the switched capacitor power amplifiers comprising the transmitter is reduced. The central frequency of the transmitter operating band is 2.4GHz, and the peak PAE of 18.5% can be reached when the maximum output power of a signal with 3dB bandwidth of 600MHz is 19 dBm. In the carrier spacing range of more than 250MHz, the suppression performance of the carrier to the third-order intermodulation distortion component is more than 40dBc when the power compensation is 9 dB.
Since all switches in this embodiment are always connected to signal ground, the impedance seen from the output terminal is constant regardless of the on/off state thereof, and this impedance has an effective value equal to R1/N. Using a balun impedance transformer to resonate at 2.4GHz, the turn ratio of the primary coil to the secondary coil is 1: 2, and combining the parasitic parameters introduced by each switched capacitor power amplifier, the 50 Ω antenna is converted into 8 Ω differential resistance, so that the switched capacitor power amplifier is matched with the output port.
In the specific embodiment of the invention, the output power control of the switched capacitor power amplifier is regulated through a digital control code, and the amplitude control part and the phase control part are used for cooperating and controlling.
According to the carrier aggregation power amplification circuit based on the double-switch capacitor, the two paths of power amplifiers controlled by the switch capacitor operate independently without mutual interference, so that the interaction between the two paths is relatively low, the nonlinear interaction in concurrent double-frequency operation is reduced to the greatest extent, and the carrier aggregation power amplification circuit has a good inhibition effect on intermodulation distortion; the circuit uses a balun transformer as output matching, and controls an input branch circuit through a digital code, so that the output impedance can be constant, and the output impedance is always kept at the optimal impedance.
The embodiment of the invention also provides electronic equipment which comprises the carrier aggregation power amplifying circuit based on the double-switch capacitor.
The electronic device may be any electronic device with a communication function, and for example, the electronic device may be a mobile phone, a tablet computer, a computer, an intelligent wearable device, a network device, an in-vehicle device, an internet of things device, and other devices dedicated or not dedicated for communication, and the like.
In the description herein, references to the description of the term "one embodiment," "an embodiment," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A carrier aggregation power amplification circuit based on double switch capacitors is characterized by comprising a first switch capacitor power amplifier, a second switch capacitor power amplifier, a balun impedance transformer and an antenna, wherein the input end of the first switch capacitor power amplifier is connected with a first input node, and the output end of the first switch capacitor power amplifier is connected with the first end of a primary coil of the balun impedance transformer; the input end of the second switched capacitor power amplifier is connected with a second input node, and the output end of the second switched capacitor power amplifier is connected with the second end of the primary coil of the balun impedance transformer; one end of a secondary coil of the balun impedance transformer is connected with the antenna, and the other end of the secondary coil of the balun impedance transformer is connected with the ground;
the first input node is configured to receive a first input signal and the second input node is configured to receive a second input signal;
the first switched capacitor power amplifier and the second switched capacitor power amplifier operate at different carrier frequencies.
2. The dual-switched-capacitor-based carrier aggregation power amplification circuit of claim 1, wherein the first switched-capacitor power amplifier comprises: a first transistor, a first load capacitor and a first resistor; the second switched-capacitor power amplifier comprises: the second transistor, a second load capacitor and a second resistor;
a control electrode of the first transistor is connected to the first input node, a first electrode of the first transistor is grounded, a second electrode of the first transistor is connected to a first end of a primary coil of the balun impedance transformer, one end of the first load capacitor is connected to the second electrode of the first transistor, the other end of the first load capacitor is grounded, one end of the first resistor is connected to the second electrode of the first transistor, and the other end of the first resistor is grounded;
a control electrode of the second transistor is connected to the second input node, a first electrode of the second transistor is grounded, a second electrode of the second transistor is connected to the second end of the primary coil of the balun impedance transformer, one end of the second load capacitor is connected to the second electrode of the second transistor, the other end of the second load capacitor is grounded, one end of the second resistor is connected to the second electrode of the second transistor, and the other end of the second resistor is grounded.
3. The dual-switch capacitance based carrier aggregation power amplification circuit of claim 2, further comprising a first switch, a second switch, a first impedance matching network, and a second impedance matching network;
a first end of the first switch is connected to the second pole of the first transistor, a second end of the first switch is connected to one end of the first impedance matching network, and the other end of the first impedance matching network is connected to a first end of a primary coil of the balun impedance transformer;
a first end of the second switch is connected to the second pole of the second transistor, a second end of the second switch is connected to one end of the second impedance matching network, and the other end of the second impedance matching network is connected to a second end of the primary coil of the balun impedance transformer.
4. The dual-switched-capacitor-based carrier aggregation power amplification circuit of claim 3, wherein the first impedance matching network comprises M impedance matching units;
one end of the M impedance matching units after being connected in parallel is connected with the second end of the first switch and the first end of the primary coil of the balun impedance transformer, and the other end of the M impedance matching units after being connected in parallel is grounded; wherein M is an integer greater than or equal to 1.
5. The dual-switched-capacitor-based carrier aggregation power amplification circuit of claim 4, wherein the second impedance matching network comprises N impedance matching units;
one end of the N impedance matching units after being connected in parallel is connected with the second end of the second switch and the second end of the primary coil of the balun impedance transformer, and the other end of the N impedance matching units after being connected in parallel is grounded; wherein N is an integer greater than or equal to 1.
6. The carrier aggregation power amplifying circuit based on double-switch capacitor as claimed in any one of claims 2 to 5, further comprising a phase control unit, a first phase shifter and a second phase shifter, wherein the phase control unit is connected to a control terminal of the first phase shifter and a control terminal of the second phase shifter respectively; a first end of the first phase shifter is connected to the first input node, and a second end of the first phase shifter is connected to a first pole of the first transistor; a first end of the second phase shifter is connected with the second input node, and a second end of the second phase shifter is connected with a control electrode of the second transistor;
the phase control unit is configured to:
generating a first phase control signal and a second phase control signal according to an input clock signal, and transmitting the first phase control signal to the first phase shifter and the second phase control signal to the second phase shifter;
the first phase shifter is configured to:
adjusting the phase of the first input signal according to the first phase control signal, and sending the phase-adjusted first input signal to a control electrode of the first transistor;
the second phase shifter is configured to:
and adjusting the phase of the second input signal according to the second phase control signal, and sending the phase-adjusted second input signal to a control electrode of the second transistor.
7. The dual-switching-capacitance-based carrier aggregation power amplification circuit according to claim 6, wherein the phase control unit comprises a phase controller, a first frequency divider and a second frequency divider; the phase controller is respectively connected with the input end of the first frequency divider and the input end of the second frequency divider, the output end of the first frequency divider is connected with the control end of the first phase shifter, and the output end of the second frequency divider is connected with the control end of the second phase shifter;
the phase controller is configured to:
generating a first clock signal with a first duty ratio according to the input clock signal and first phase information, and sending the first clock signal to the first frequency divider; the input clock signal is a signal of the first duty ratio;
generating a second clock signal with the first duty ratio according to the input clock signal and second phase information, and sending the second clock signal to the second frequency divider;
the first frequency divider is configured to:
generating the first phase control signal according to the first clock signal, and sending the first phase control signal to the first phase shifter, wherein the first phase control signal is a signal with a second duty ratio;
the second frequency divider is configured to:
generating the second phase control signal according to the second clock signal, and sending the first phase control signal to the second phase shifter, wherein the second phase control signal is a signal with the second duty ratio; the second duty cycle is less than the first duty cycle.
8. The dual-switched capacitor-based carrier aggregation power amplification circuit according to any one of claims 1 to 5, further comprising an amplitude control unit, wherein the amplitude control unit is connected with the control electrode of the first transistor and the control electrode of the second transistor;
the amplitude control unit is used for controlling the signal amplitude of the control electrode of the first transistor and the control electrode of the second transistor.
9. The dual-switched-capacitor-based carrier aggregation power amplifying circuit according to any one of claims 1 to 5, wherein the magnetic core of the balun impedance transformer is 1500 μm, the resonant frequency of the balun impedance transformer is 2.4GHz, and the turn ratio of the primary coil and the secondary coil of the balun impedance transformer is 1: 2.
10. an electronic device comprising the dual-switched-capacitor-based carrier aggregation power amplification circuit of any one of claims 1 to 9.
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| CN213783259U (en) * | 2020-12-10 | 2021-07-23 | 富满微电子集团股份有限公司 | Carrier aggregation power amplification circuit based on double switch capacitors and electronic equipment |
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| US20050206471A1 (en) * | 2004-03-16 | 2005-09-22 | Shahla Khorram | Tuned transformer balun circuit and applications thereof |
| CN105305973A (en) * | 2015-11-30 | 2016-02-03 | 北京机械设备研究所 | Low-distortion MOSFET high-power amplification circuit |
| CN108270407A (en) * | 2016-12-30 | 2018-07-10 | 通用电气公司 | A kind of planar Balun and a kind of multilayer circuit board |
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