CN112635409A - Passivation layer of gallium oxide power device and passivation method thereof - Google Patents
Passivation layer of gallium oxide power device and passivation method thereof Download PDFInfo
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- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 71
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims abstract description 68
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/298—Semiconductor material, e.g. amorphous silicon
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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Abstract
The invention discloses a passivation layer of a gallium oxide power device and a passivation method thereof, belonging to the technical field of semiconductor power devices, wherein the preparation method of the passivation layer of the gallium oxide power device comprises the following steps: formation of Ga2O3An epitaxial layer; in the Ga2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer; and forming a gallium oxide power device passivation layer on the SIPOS passivation layer. That is, the present invention is achieved by adding Ga2O3The method for forming the oxygen-doped polycrystalline silicon passivation layer on the surface of the epitaxial layer can effectively shield the influence of factors such as defects and traps introduced by the existing passivation process on the terminal performance of the gallium oxide power device, thereby improving the quality of the passivation layer in the terminal area of the device, reducing the influence of factors such as interface states, interface traps and interface charges on the terminal structure of the device, improving the device performance, and having simple structure, simple process and low energy consumption, thereby greatly improving the high efficiency of preparing the gallium oxide power deviceThe performance and the reliability of the power device also improve the service life of the gallium oxide power device.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and relates to a gallium oxide power device passivation layer and a passivation method thereof.
Background
In recent years, beta-Ga2O3As a developed ultra-wide bandgap semiconductor material, n-type Ga having a thickness of 30 μm is used2O3The vertical Schottky diode (SBD) prepared by the material can reduce the switching loss of the device, improve the performance of a motor driver and simplify a protection circuit in a switching power supply circuit, but because of beta-Ga2O3The material is difficult to realize p-type doping, so that the vertical SBD device cannot use a terminal voltage-resistant protection structure. Thus vertical form of beta-Ga2O3The SBD device is getting more and more attentive to achieve higher breakdown voltage.
Conventional vertical structure Ga2O3In the preparation method of the metal oxide semiconductor field effect transistor, SiO is deposited on the cleaned epitaxial wafer2(ii) a Removing part of SiO by photoetching and etching2Forming a region to be annealed; placing the etched epitaxial wafer into SiO2Annealing in the environment; then washing off the residual SiO2 by using HF; performing N + + Si ion implantation of shallow junctions below the source region and annealing; growing Al by ALD2O3A gate dielectric; removing source region Al by photolithography and etching2O3(ii) a Photoetching to form a source electrode area and a drain electrode area, evaporating drain electrode metal and annealing to form ohmic contact; and photoetching to form a gate region and evaporating the gate electrode metal to finish the manufacture of the device.
However, the conventional vertical structure Ga2O3In the preparation method of metal oxide semiconductor field effect transistor, SiO is adopted2Passivation is carried out to result in Ga2O3The critical breakdown field of the SBD device is high and also results in Ga2O3The leakage current of the SBD device is too high.
Disclosure of Invention
For the conventional vertical structure Ga described above2O3The defects of the metal oxide semiconductor field effect transistor in the preparation process are overcome, and the passivation layer of the gallium oxide power device and the passivation method thereof are provided for solving the problem of the existing Ga with a vertical structure2O3In the preparation method of metal oxide semiconductor field effect transistor, SiO is adopted2Ga resulting from performing passivation2O3The critical breakdown electric field of the SBD device is high, and the leakage current is overhigh.
In order to solve the technical problems, the invention adopts the following technical scheme: a gallium oxide power device passivation layer, comprising:
Ga2O3an epitaxial layer;
a SIPOS passivation layer disposed at the Ga2O3The surface of the epitaxial layer;
a gallium oxide power device passivation layer disposed on the SIPOS passivation layer.
Optionally, the passivation layer of the gallium oxide power device and the passivation layer of the SIPOS are the same layer.
Optionally, the SIPOS passivation layer is a SIPOS film.
Optionally, the thickness of the SIPOS passivation layer is 0.1-1 μm.
The invention also provides a preparation method of the passivation layer of the gallium oxide power device, which comprises the following steps:
s101. formation of Ga2O3An epitaxial layer;
s102. in the Ga2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer;
and S103, forming a gallium oxide power device passivation layer on the SIPOS passivation layer.
Optionally, in step S102, the Ga is deposited2O3And forming a SIPOS passivation layer on the surface of the epitaxial layer.
Optionally, in step S102, the Ga is deposited by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process2O3And forming a SIPOS passivation layer on the surface of the epitaxial layer.
Optionally, step S103 includes:
after the SIPOS passivation layer is subjected to thermal annealing treatment, forming the SIPOS passivation layer subjected to thermal annealing treatment;
and carrying out imaging treatment on the SIPOS passivation layer after the thermal annealing treatment to form the gallium oxide power device passivation layer.
Optionally, step S103 includes:
after the SIPOS passivation layer after the thermal annealing treatment is treated by adopting an etching process, the silicon nitride oxide (SIPOS) passivation layer is continuously remained in the Ga2O3A residual target substance on the surface of the epitaxial layer;
and forming the gallium oxide power device passivation layer by using the residual target substance.
Optionally, step S101 includes:
determination of Ga2O3An epitaxial wafer;
applying RCA standard cleaning process to the Ga2O3Cleaning the epitaxial wafer to form the Ga2O3An epitaxial layer.
The invention has the beneficial effects that: the invention discloses a passivation layer of a gallium oxide power device and a passivation method thereof, belonging to the technical field of semiconductor power devices, wherein the preparation method of the passivation layer of the gallium oxide power device comprises the following steps: formation of Ga2O3An epitaxial layer; in the Ga2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer; and forming a gallium oxide power device passivation layer on the SIPOS passivation layer. That is, the present invention is achieved by adding Ga2O3The method for forming the oxygen-doped polysilicon passivation layer on the surface of the epitaxial layer can effectively shield the influence of factors such as defects, traps and the like introduced by the prior passivation process on the terminal performance of the gallium oxide power device, and avoids the problem that SiO is adopted in the prior art2Ga resulting from performing passivation2O3The problem that the critical breakdown electric field of the SBD device is high and the leakage current is overhigh is solved, the influence of factors such as defects, traps and the like introduced by the existing passivation process on the terminal performance of the gallium oxide power device is shielded, the quality of a passivation layer of a device terminal area is improved, the influence of factors such as interface states, interface traps, interface charges and the like on a device terminal structure is reduced, the device performance is also improved, the structure is simple, the process is simple, the energy consumption is low, the high efficiency and the reliability of preparing the gallium oxide power device are greatly improved, and the efficiency and the reliability of preparing the gallium oxide power device are also improvedService life.
Drawings
Fig. 1 is a schematic view of a passivation layer structure of a gallium oxide power device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for fabricating a passivation layer of a gallium oxide power device according to another embodiment of the present invention;
FIG. 3 is a flow chart illustrating the process of fabricating a passivation layer of a gallium oxide power device according to another embodiment of the present invention;
wherein: 1. ga2O3An epitaxial layer; a SIPOS passivation layer; 3. and (3) passivating a gallium oxide power device layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical" and the like do not imply that the components are required to be absolutely horizontal or pendant, but rather may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terms to which the present invention relates will be explained first:
Ga2O3：Ga2O3is gallium sesquioxide, is a wide bandgap semiconductor, Eg =4.9eV, and has a high dielectric constant2O3Is a transparent oxide semiconductor material, is white triangular crystal particle, is insoluble in water, slightly soluble in hot acid or alkali solution, has melting point of 1900 deg.C (converted into beta form at 600 deg.C), is easily soluble in alkali metal hydroxide and dilute inorganic acid, and has alpha-Ga2O3And beta-Ga2O3Two variants, alpha-Ga2O3The hexagonal crystal form is white rhombohedral, beta-Ga2O3Belongs to a monoclinic crystal form.
SBD (schottky barrierriediode, SBD): SBDs are Schottky barrier diodes, which are named by their inventor Schottky (Schottky). The SBD is not manufactured by utilizing the principle that a P-type semiconductor and an N-type semiconductor contact form a PN junction, but is manufactured by utilizing the principle that a metal and a semiconductor contact form a metal-semiconductor junction. Thus, SBDs are also known as metal-semiconductor (contact) diodes or surface barrier diodes, which are a type of hot carrier diode. The schottky diode is a metal-semiconductor device in which a noble metal (gold, silver, aluminum, platinum, or the like) a is used as a positive electrode, an N-type semiconductor B is used as a negative electrode, and a barrier formed on a contact surface between the two has rectifying characteristics.
Etching: the english is Etch, which is a very important step in semiconductor manufacturing process, microelectronic IC manufacturing process and micro-nano manufacturing process. Is one of the main processes of patterning (pattern) processing associated with lithography [1 ]. Etching is actually understood in a narrow sense as photolithographic etching, in which the photoresist is first subjected to a photolithographic exposure process by photolithography and then etched away by other means to remove the portions to be removed. Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, with the primary objective being to properly replicate the mask pattern on a gummed silicon wafer. With the development of micro-fabrication technology, etching is a general term for stripping and removing materials by solution, reactive ion or other mechanical means, which is a common name for micro-fabrication.
RCA Standard cleaning method: the RCA standard clean was first initiated in 1965 by Kern and Puotinen et al in the RCA laboratory in n.j.princeton and is hence the name. RCA is a typical, and by far the most commonly used, wet chemical cleaning method. The general idea of cleaning is to remove organic contaminants on the surface of the silicon wafer first, because organic substances cover part of the surface of the silicon wafer, thereby making the oxide film and the contaminants related thereto difficult to remove; the oxide film is then dissolved, since the oxide layer is a "contamination trap", epitaxial defects are also introduced; finally removing the contamination of particles, metals and the like, and simultaneously passivating the surface of the silicon wafer.
Annealing treatment: annealing is a heat treatment process in which a material is exposed to high temperature for a long period of time and then slowly cooled. The main purposes are to relieve stress, increase material ductility and toughness, create special microstructures, etc.
Currently, beta-Ga2O3As a newly developed ultra-wide bandgap semiconductor material, the bandgap width is about 4.8-4.9 eV, the breakdown electric field reaches 8MV/cm, which is equivalent to 26 times of Si and more than 2 times of SiC and GaN. Baliga (bali plus figure of merit) figure of merit is 3000 times that of Si; 8 times of SiC material and 4 times of GaN material; the high-frequency Baliga optimal value is 150 times that of the Si material; 3 times of SiC; and 1.5 times the GaN material. For unipolar power devices with the same voltage withstanding level, the on-resistance can be reduced to 1/10 of SiC and 1/3 of GaN, and the power consumption of the device can be effectively reduced. Theoretical calculations show that n-type Ga of 30 μm thickness is used2O3The theoretical breakdown voltage of the vertical Schottky diode (SBD) prepared from the material can reach 24000V, and the reverse recovery current is almost zero, so that the switching loss of a device can be greatly reduced, the performance of a motor driver is improved, and a protection circuit in a switching power supply circuit is simplified.
Due to beta-Ga2O3The p-type doping of the material is difficult to realize, so that the field plate terminal is generally adopted by the vertical SBD power device as a main structure for improving the breakdown voltage of the device. However, since the conventional field plate structure is a metal/dielectric layer/semiconductor material structure, the performance of the field plate terminal is often affected by the quality of the dielectric layer. Ga2O3Since the critical breakdown field of the SBD device is high, the silicon dioxide, which is a commonly used dielectric layer material at present, often causes the leakage current of the device to be too high. Thus, a novel Ga compound was developed2O3The surface passivation method of the power device terminal area effectively reduces the device leakage current, and for beta-Ga2O3The performance improvement and application of the SBD device are of great significance.
However, Ga in the prior art2O3The power device usually adopts SiO2Passivation layer of Ga2O3SBD devices often have too high a device leakage current due to the high critical breakdown field of silicon dioxide, which is a commonly used dielectric material. Therefore, the present inventionObviously provides a passivation layer of a gallium oxide power device and a passivation method thereof, aiming at solving the problem of Ga in the prior art2O3The power device usually adopts SiO2Passivation layer of Ga2O3The SBD device has a high critical breakdown field, so that the commonly used dielectric layer material, silicon dioxide, often causes a problem of too high device leakage current.
The passivation layer of the gallium oxide power device and the passivation method thereof according to the embodiments of the present invention will be described in detail below with reference to fig. 1 to 3.
As shown in fig. 1, the passivation layer of the gallium oxide power device provided by the embodiment of the present invention may include: ga2O3Epitaxial layer 1, SIPOS passivation layer 2 and gallium oxide power device passivation layer 3.
Wherein SIPOS (semi-insulating polysilicon) passivation layer can be arranged on Ga2O3On the surface of the epitaxial layer, a gallium oxide power device passivation layer may be disposed on the SIPOS passivation layer.
Optionally, the gallium oxide power device passivation layer and the SIPOS passivation layer may be the same layer. Such as a gallium oxide power device passivation layer and a SIPOS passivation layer, may be of the same depth range or the same thickness range.
Optionally, the SIPOS passivation layer may be a SIPOS film.
Optionally, the thickness of the SIPOS passivation layer is 0.1-1 μm.
The invention discloses a passivation layer of a gallium oxide power device, which comprises: ga2O3An epitaxial layer; a SIPOS passivation layer disposed at the Ga2O3The surface of the epitaxial layer; a gallium oxide power device passivation layer disposed on the SIPOS passivation layer. That is, the present invention is applied to Ga by using SIPOS instead of conventional silica2O3The SBD field plate terminal dielectric layer mode can effectively shield the influence of factors such as defects, traps and the like introduced by the prior passivation process on the terminal performance of the gallium oxide power device, and avoids the problem that SiO is adopted in the prior art2Ga resulting from performing passivation2O3Temporary of SBD deviceThe problems of high boundary breakdown electric field and overhigh leakage current are solved, the influence of factors such as defects, traps and the like introduced by the existing passivation process on the terminal performance of the gallium oxide power device is shielded, the quality of a passivation layer in a terminal area of the device is improved, the influence of factors such as interface states, interface traps, interface charges and the like on a terminal structure of the device is reduced, the device performance is also improved, the structure is simple, the process is simple, the energy consumption is low, and the service life of the gallium oxide power device is greatly prolonged.
In another possible embodiment, the present invention further provides a method for preparing a passivation layer of a gallium oxide power device, and fig. 2 is a flowchart of a method for preparing a passivation layer of a gallium oxide power device according to another embodiment of the present invention. The steps involved in the method are described in detail below with reference to fig. 2.
Step S101 of forming Ga2O3An epitaxial layer.
In the actual process, step S101 can be realized by the following sub-steps:
step S1011, determining Ga2O3And (7) an epitaxial wafer.
Specifically, Ga is formed2O3Ga may be carried out before epitaxial layer2O3Preparation of epitaxial wafer for subsequent Ga2O3Cleaning the epitaxial wafer to form Ga2O3An epitaxial layer. Wherein Ga2O3The epitaxial wafer may be made of Ga2O3An epitaxial wafer of material.
Step S1012, adopting RCA standard cleaning process to clean the Ga2O3Cleaning the epitaxial wafer to form the Ga2O3An epitaxial layer.
In particular, since Ga2O3The epitaxial wafer is often contaminated with organic contaminants such that it is difficult to remove the oxide film and contaminants associated therewith, and thus, the Ga is prepared2O3When the epitaxial wafer is used, the standard cleaning process of RCA can be adopted to further clean Ga2O3Cleaning the epitaxial wafer to remove Ga2O3Other contamination of particles, metals, etc. on the epitaxial waferThen, Ga can be formed by using the remaining material after the cleaning treatment2O3An epitaxial layer.
Step S102 of forming a metal layer on the Ga2O3And forming a SIPOS passivation layer on the surface of the epitaxial layer.
During the actual treatment, Ga may be in2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer by SIPOS deposition, wherein the deposition can comprise the following steps: the low pressure chemical vapor deposition process or the plasma enhanced chemical vapor deposition process, i.e., the vapor deposition process can be performed on Ga by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process2O3And forming a SIPOS passivation layer on the surface of the epitaxial layer. Thus, step S102 may be implemented by the following procedure:
ga can be deposited by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process2O3Ga formed after epitaxial wafer is processed by RCA standard cleaning process2O3The epitaxial layer is subjected to a SIPOS deposition process to thereby form Ga2O3The surface of the epitaxial layer is deposited with SIPOS passivation layer with thickness of 0.1-1 μm.
Alternatively, the SIPOS passivation layer of 0.1-1 μm may be a SIPOS film of 0.1-1 μm.
In the actual process, the basic principle of Low Pressure Chemical Vapor Deposition (LPCVD) is to deposit one or more gaseous substances on the surface of a substrate by thermal decomposition or Chemical reaction under Low Pressure, which can be widely used for silicon oxide, nitride, and polysilicon Deposition, and the process is performed in a tube furnace, and requires relatively high temperature. The basic principle of Plasma Enhanced Chemical Vapor Deposition (PECVD) is to ionize a gas containing atoms of a film component by means of microwave or radio frequency, etc., to locally form a Plasma, which is chemically active and easily reacts to deposit a desired film on a substrate. In order to allow the chemical reaction to proceed at a relatively low temperature, the activity of the plasma is utilized to promote the reaction. Such chemical vapor deposition is thus referred to as plasma enhanced chemical vapor deposition.
And step S103, forming a gallium oxide power device passivation layer on the SIPOS passivation layer.
In the actual processing procedure, step S103 can be realized by the following substeps:
and step S1031, performing thermal annealing treatment on the SIPOS passivation layer, and then forming the SIPOS passivation layer after the thermal annealing treatment.
Specifically, the SIPOS passivation layer can be a SIPOS film with the thickness of 0.1-1 μm, so that the SIPOS passivation layer is subjected to thermal annealing treatment, or the SIPOS film is subjected to thermal annealing treatment to be more compact, so that the SIPOS passivation layer after the thermal annealing treatment is formed. The environment for thermal annealing treatment may include NO and NO2、O2、N2At least one of (1).
Optionally, the SIPOS passivation layer after the thermal annealing treatment can be an epitaxial wafer deposited with SIPOS.
And S1032, imaging the SIPOS passivation layer after the thermal annealing treatment to form the gallium oxide power device passivation layer.
Specifically, step S1032 may be implemented by the following processes:
and step S21, processing the SIPOS passivation layer after the thermal annealing treatment by adopting an etching process to obtain residual target substances which continuously stay on the surface of the Ga2O3 epitaxial layer.
Specifically, the SIPOS passivation layer after the thermal annealing treatment may be processed by an etching process, for example, the SIPOS passivation layer after the thermal annealing treatment is first photo-etched to form an area to be annealed, and then the SIPOS covering the area to be annealed is etched to obtain a continuous residue in the Ga2O3The remaining target species on the surface of the epitaxial layer. Wherein the remaining target substance may comprise unprocessed SIPOS.
And step S22, forming the gallium oxide power device passivation layer by using the residual target substance.
In particular, the remaining target substance may be washedAnd after treatment and blow-drying treatment, forming a passivation layer of the gallium oxide power device. Thereby realizing the replacement of the traditional silicon dioxide for Ga by SIPOS2O3The purpose of forming the passivation layer of the gallium oxide power device by the SBD field plate terminal dielectric layer is achieved, and Ga brought by the traditional silicon dioxide dielectric is shielded2O3The excessive leakage current of the field plate terminal of the SBD.
Optionally, the gallium oxide power device passivation layer and the SIPOS passivation layer may be the same layer. Such as a gallium oxide power device passivation layer and a SIPOS passivation layer, may be of the same depth range or the same thickness range.
Illustratively, as shown in FIG. 3, Ga may be performed first2O3Preparation of epitaxial wafer and then of Ga2O3After the epitaxial wafer is subjected to RCA cleaning treatment, Ga is formed2O3Film, further using low pressure chemical vapor deposition process or plasma enhanced chemical vapor deposition process to Ga2O3The film is subjected to SIPOS deposition treatment to thereby form Ga2O3And a SIPOS passivation layer with the thickness of 0.1-1 μm is deposited on the surface of the epitaxial layer. Then in the presence of NO, NO2、O2And/or N2Performing thermal annealing treatment on the SIPOS passivation layer in the environment to form the SIPOS passivation layer after the thermal annealing treatment, and finally, after the SIPOS passivation layer after the thermal annealing treatment is treated by adopting an etching process, utilizing the continuous retention in Ga2O3And forming a gallium oxide power device passivation layer by the residual target substances on the surface of the epitaxial layer.
In the embodiment of the invention, the preparation method of the passivation layer of the gallium oxide power device comprises the following steps: formation of Ga2O3An epitaxial layer; in the Ga2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer; and forming a gallium oxide power device passivation layer on the SIPOS passivation layer. That is, the present invention is achieved by adding Ga2O3The method for forming the oxygen-doped polysilicon passivation layer on the surface of the epitaxial layer can effectively shield the influence of factors such as defects, traps and the like introduced by the prior passivation process on the terminal performance of the gallium oxide power device, and avoids the problem that SiO is adopted in the prior art2Is passivated to conductGa thereby2O3The problem that the critical breakdown electric field of the SBD device is high and the leakage current is too high is solved, the influence of factors such as defects and traps introduced by the existing passivation process on the terminal performance of the gallium oxide power device is shielded, the quality of a passivation layer of a device terminal area is improved, the influence of factors such as an interface state, an interface trap and an interface charge on a device terminal structure is reduced, the device performance is also improved, the structure is simple, the process is simple, the energy consumption is low, the high efficiency and the reliability of preparing the gallium oxide power device are greatly improved, and the service life of the gallium oxide power device is also prolonged.
In a possible embodiment, the present invention further provides an electronic device, which includes the passivation layer of the gallium oxide power device in the foregoing embodiment, or the passivation layer of the gallium oxide power device included in the electronic device can be prepared by any one of the above passivation methods. The specific implementation and technical effects are similar, and are not described herein again.
In the electronic device provided in the embodiment of the present invention, the passivation layer of the gallium oxide power device includes: ga2O3An epitaxial layer; a SIPOS passivation layer arranged at Ga2O3The surface of the epitaxial layer; and the gallium oxide power device passivation layer is arranged on the SIPOS passivation layer.
Preferably, the present invention also provides a computer-readable storage medium comprising a program which, when executed by a processor, is adapted to perform the above-described method embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (10)
1. A gallium oxide power device passivation layer, comprising:
Ga2O3an epitaxial layer;
a SIPOS passivation layer disposed at the Ga2O3The surface of the epitaxial layer;
a gallium oxide power device passivation layer disposed on the SIPOS passivation layer.
2. The gallium oxide power device passivation layer of claim 1, wherein the gallium oxide power device passivation layer and the SIPOS passivation layer are the same layer.
3. The gallium oxide power device passivation layer of claim 1, wherein the SIPOS passivation layer is a SIPOS thin film.
4. The passivation layer of a gallium oxide power device according to claim 1, wherein the thickness of the SIPOS passivation layer is 0.1-1 μm.
5. A preparation method of a passivation layer of a gallium oxide power device is characterized by comprising the following steps:
s101. formation of Ga2O3An epitaxial layer;
s102. in the Ga2O3Forming a SIPOS passivation layer on the surface of the epitaxial layer;
and S103, forming a gallium oxide power device passivation layer on the SIPOS passivation layer.
6. The method for preparing the passivation layer of the gallium oxide power device according to claim 5, wherein the Ga is deposited in step S1022O3And forming a SIPOS passivation layer on the surface of the epitaxial layer.
7. The method for preparing the passivation layer of the gallium oxide power device according to claim 6, wherein in step S102
By a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process on the Ga2O3And forming a SIPOS passivation layer on the surface of the epitaxial layer.
8. The method for preparing the passivation layer of the gallium oxide power device according to claim 6, wherein the step S103 comprises:
after the SIPOS passivation layer is subjected to thermal annealing treatment, forming the SIPOS passivation layer subjected to thermal annealing treatment;
and carrying out imaging treatment on the SIPOS passivation layer after the thermal annealing treatment to form the gallium oxide power device passivation layer.
9. The method for preparing the passivation layer of the gallium oxide power device according to claim 8, wherein the step S103 comprises:
after the SIPOS passivation layer after the thermal annealing treatment is treated by adopting an etching process, the silicon nitride oxide (SIPOS) passivation layer is continuously remained in the Ga2O3A residual target substance on the surface of the epitaxial layer;
and forming the gallium oxide power device passivation layer by using the residual target substance.
10. The method for preparing the passivation layer of the gallium oxide power device according to claim 5, wherein the step S101 comprises:
determination of Ga2O3An epitaxial wafer;
applying RCA standard cleaning process to the Ga2O3Cleaning the epitaxial wafer to form the Ga2O3An epitaxial layer.
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| WO2019116736A1 (en) * | 2017-12-12 | 2019-06-20 | 三菱電機株式会社 | Pressure-contact type semiconductor device and method for producing pressure-contact type semiconductor device |
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