CN112286716A - 1024-byte storage system error control module - Google Patents
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
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Abstract
The invention belongs to the technical field of error correction of storage systems, and particularly relates to a 1024-byte storage system error control module. The error control module includes: a BCH coding module and a BCH decoding module; the BCH coding module comprises: an encoding arithmetic unit and an encoding control unit; the BCH decoding module comprises: a decoding arithmetic unit and a decoding control unit; according to the decoding principle of the BCH code, the BCH decoding unit further comprises: the syndrome calculation module, the error position polynomial module, the Chien search module and the error correction module; the invention is applied to the NAND Flash memory controller, can have larger bit width of information data than a common error control system under the condition of keeping the correctness and stability of error correction, and simultaneously, the high efficiency of an error control scheme can be ensured by the design of a 32-bit pipeline.
Description
Technical Field
The invention belongs to the technical field of error correction of storage systems, and particularly relates to a 1024-byte storage system error control module.
Background
In the process of manufacturing the NAND flash memory, due to the fact that the NAND flash memory has the possibility of generating defects due to its own characteristics, particularly, the level distance of the storage unit is smaller and smaller with the improvement of the process precision, the leakage is obvious, the yield and the reliability are reduced due to the adoption of the structure of the multi-bit storage unit for improving the storage capacity, data errors may be generated when the NAND flash memory is subjected to an erasing operation, and the above effects are finally expressed as randomly generated bit errors, so that an error control mechanism needs to be added to a data storage controller to ensure the correctness of data entering and exiting the storage system.
The method usually adopted is that when data is written, an encoder is used to generate ECC parity bits to be stored in a redundant area outside a flash memory data area, and when data is read, a decoder is used to decode and check to confirm that the received data has no errors. If the data is confirmed to have interference or errors, the error positions are further found out and then bit inversion is carried out to recover the correct data.
Because the data or program storage requirements of the current electronic system equipment are increasingly vigorous, the reliability requirements of the NAND Flash are continuously improved. In order to adapt to a specific working environment, the FPGA is often used as a NAND Flash storage controller to directly access the NAND Flash particles, so that an ECC algorithm acceleration module is required to be integrated to complete data error detection and correction. With the higher requirements of various application scenarios on reliability and throughput, the ECC function is required to have a higher bit width error correction capability, and meanwhile, the ECC function can have a configurable adjustment function in design and implementation.
The process of writing and reading data in the memory is similar to the channel transmission process of data transmission and reception in a communication system, there may be error bit interference to cause data unreliability, and thus it is necessary to implement automatic error detection and correction capability by using channel coding technology. Common channel error control methods include a retransmission feedback mode (ARQ), a forward error correction mode (FEC), an information feedback system (IRQ), a hybrid error correction mode (HEC), and the like, and the forward error correction mode, especially linear block code, is a currently main application algorithm in consideration of the read-write characteristics, performance requirements, and the random error location characteristics of the storage system. The most important error correction algorithm in this aspect includes hamming code, BCH code, LDPC code, and the like, but considering the aspects of error correction performance, resource occupation, performance, and the like comprehensively, BCH code error correction is currently the most mainstream hardware error correction algorithm.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to improve the reliability and data error control efficiency of a data storage system.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a 1024-byte error control module for a storage system, wherein the error control module is a binary BCH codec, and comprises: a BCH coding module and a BCH decoding module; the BCH coding module comprises: an encoding arithmetic unit and an encoding control unit; the BCH decoding module comprises: a decoding arithmetic unit and a decoding control unit; according to the decoding principle of the BCH code, the BCH decoding unit further comprises: the syndrome calculation module, the error position polynomial module, the Chien search module and the error correction module; wherein,
the coding control unit and the decoding control unit are the control core of the BCH codec and are responsible for managing and scheduling the normal work of the coding operation unit and the decoding operation unit;
the coding operation unit is used for coding data serving as information bits in the programming process of the Flash page to generate required check bits; when reading Flash, enabling a decoding operation unit by a decoding control unit, and judging whether read data have errors by a syndrome calculation module in the decoding operation unit; if errors are detected, the positions where bit reversal occurs are found through an error position polynomial module and a Chien searching module, and the data bits are turned from 0 to 1 or from 1 to 0 due to the fact that only two conditions exist when the data bits in Flash are in error reversal; thus. And finally, the error correction module can complete error correction only by carrying out negation operation on the searched error position.
The error control module adopts a binary BCH coding and decoding algorithm principle to carry out scheme design; it uses 1024 bytes data as one time information code element, selects binary finite field GF (2)14) As the domain computation space, polynomial 1+ x is chosen2+x4+x6+x7+x8+x14Adopting 32-bit data parallel processing for the primitive polynomial; the error control module parameter settings are as follows:
| description of the invention | Parameter design (bit) |
| Dimension of finite field | 14 |
| Error correction data space | 8192 |
| |
1+x2+x4+x6+x7+x8+x14 |
| Bit width of |
32 |
。
Wherein, the encoding arithmetic unit adopts 32 bit stream parallel processing;
the coding operation unit is used for obtaining a check bit r (x) by utilizing an information bit m (x) and a generating polynomial g (x); 8192bit information bits of original data enter the encoding arithmetic unit in parallel and successively by a bit width of 32 bits, each calculation period modulus functional unit calculates the information bits, the result is stored in a register at present, and the information bits of the original data are also used as the output of the current circuit at the same time; and when all the information bits are input, stopping the calculation of the modular division functional unit, and gradually outputting the data in the current register in a 32-bit parallel mode to obtain check bit data.
The decoding working process of the decoding arithmetic unit comprises four steps:
the first step is the calculation of the syndrome, firstly, a multiply-accumulate operation is carried out through an SC _ FFMA module, and then the domain platform operation result value of the SC _ SEQ module is brought into an SC _ MUL module to carry out finite domain multiply-accumulate operation to obtain the syndrome;
the second step is the calculation of an error position polynomial module which realizes the SiBM algorithm and leads the syndrome SiAs inputs, the error location polynomial module comprises a calculation control module PE _ CTRL and an arithmetic unit PE; the operation unit PE completes the basic operation function of each step, and the calculation control module PE _ CTRL is responsible for state judgment and control of the operation of the circuit;
the third step is Chien search calculation, wherein a Chien search module takes an error position polynomial as input data, introduces finite field elements one by one, and calculates a polynomial result sigma (alpha)i) Whether or not it is 0 to judge alphaiWhether it is the root of a polynomial; if the number of the final root is the same as the power of the error position polynomial, indicating that the error mode of the data can be corrected, otherwise indicating that the number of the errors exceeds the error correction capability, and failing to correct the errors; in the scheme, σ (α) is first calculatedi) Corresponding mu0,μ1,μ2,…,μtThen each mu is measuredjMultiplying by corresponding alpha0,α1,α2,…,αtThus realizing 32-path parallel processing;
in the last step, the decoded data can be obtained by performing bit inversion on the obtained corresponding data bits at the error positions and using exclusive-or operation.
In the third step, the number of the final roots is the same as the power of the error position polynomial, and the difference between the number of the final roots and the power of the error position polynomial is smaller than or equal to a preset value t.
(III) advantageous effects
The invention provides a 1024-byte storage system error control module for fully playing the error control capability of a storage system controller and the data integrity and reliability capability of the storage system, which can improve the reliability and data error control efficiency of a data storage system by adjusting error control error correction code algorithm parameters and optimizing error control under the condition of ensuring the data correctness of a data port of the storage system.
Compared with the prior art, the invention is applied to the NAND Flash memory controller, can have larger bit width of information bit data compared with a common error control system under the condition of keeping the correctness and stability of error correction, and meanwhile, the high efficiency of an error control scheme can be ensured by the design of a 32-bit pipeline. The scheme has obvious beneficial effects based on the storage characteristics of the storage system, particularly the storage randomness errors which are easy to occur in the storage process. The method has the advantages that the safety and reliability of the system are improved and the efficiency is improved more and more important for various information system devices, especially data integrity sensitive devices.
Drawings
Fig. 1 is a block diagram of an error control scheme.
Fig. 2 is a view showing the structure of an encoder.
Fig. 3 is a schematic diagram of decoder syndrome calculation.
FIG. 4 is a diagram illustrating the calculation of the error location polynomial of the decoder.
Fig. 5 is a schematic diagram of the decoder chien search computation.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
To solve the problems in the prior art, the present invention provides a 1024-byte error control module for a storage system, as shown in fig. 1, where the error control module is a binary BCH codec, and includes: a BCH coding module and a BCH decoding module; the BCH coding module comprises: an encoding arithmetic unit and an encoding control unit; the BCH decoding module comprises: a decoding arithmetic unit and a decoding control unit; according to the decoding principle of the BCH code, the BCH decoding unit further comprises: the syndrome calculation module, the error position polynomial module, the Chien search module and the error correction module; wherein,
the coding control unit and the decoding control unit are the control core of the BCH codec and are responsible for managing and scheduling the normal work of the coding operation unit and the decoding operation unit;
the coding operation unit is used for coding data serving as information bits in the programming process of the Flash page to generate required check bits; when reading Flash, enabling a decoding operation unit by a decoding control unit, and judging whether read data have errors by a syndrome calculation module in the decoding operation unit; if errors are detected, the positions where bit reversal occurs are found through an error position polynomial module and a Chien searching module, and the data bits are turned from 0 to 1 or from 1 to 0 due to the fact that only two conditions exist when the data bits in Flash are in error reversal; thus. And finally, the error correction module can complete error correction only by carrying out negation operation on the searched error position.
The error control module adopts a binary BCH coding and decoding algorithm principle to carry out scheme design; it uses 1024 bytes data as one time information code element, selects binary finite field GF (2)14) As the domain computation space, polynomial 1+ x is chosen2+x4+x6+x7+x8+x14Adopting 32-bit data parallel processing for the primitive polynomial; the error control module parameter settings are as follows:
| description of the invention | Parameter design (bit) |
| Dimension of finite field | 14 |
| Error correction data space | 8192 |
| |
1+x2+x4+x6+x7+x8+x14 |
| Bit width of |
32 |
。
Wherein, the encoding arithmetic unit adopts 32 bit stream parallel processing;
the encoding operation unit is configured to obtain a check bit r (x) by using the information bit m (x) and the generator polynomial g (x), and a structure of an implementation scheme is shown in fig. 2; 8192bit (8 × 1024Byte) information bits of original data enter the encoding arithmetic unit in parallel and successively in a 32-bit data bit width, each calculation period modulo division functional unit calculates the information bits, the current result is stored in a register, and the information bits of the original data are also used as the output of the current circuit; and when all the information bits are input, stopping the calculation of the modular division functional unit, and gradually outputting the data in the current register in a 32-bit parallel mode to obtain check bit data.
The decoding working process of the decoding arithmetic unit comprises four steps:
the first step is the calculation of the syndrome as shown in fig. 3, firstly, a multiply-accumulate operation is carried out through the SC _ FFMA module, and then the domain platform operation result value of the SC _ SEQ module is brought into the SC _ MUL module to carry out finite domain multiply-add operation to obtain the syndrome;
the second step is the calculation of the error location polynomial module, which implements the SiBM algorithm, which will accompany the equation S, as shown in FIG. 4iAs inputs, the error location polynomial module comprises a calculation control module PE _ CTRL and an arithmetic unit PE; the operation unit PE completes the basic operation function of each step, and the calculation control module PE _ CTRL is responsible for state judgment and control of the operation of the circuit;
the third step is Chien search calculation as shown in FIG. 5, wherein a Chien search module takes the error position polynomial as input data, introduces finite field elements one by one, and calculates a polynomial result sigma (alpha)i) Whether or not it is 0 to judge alphaiWhether it is the root of a polynomial; if the number of the final root is the same as the power of the error position polynomial (less than or equal to t), indicating that the error mode of the data can be corrected, otherwise indicating that the number of the errors exceeds the error correction capability, and failing to correct the errors; in the scheme, σ (α) is first calculatedi) Corresponding mu0,μ1,μ2,…,μtThen each mu is measuredjMultiplying by corresponding alpha0,α1,α2,…,αtThus realizing 32-path parallel processing;
in the last step, the decoded (i.e. error correction completed) data can be obtained by only carrying out bit reversal on the obtained corresponding data bits at the error positions and using exclusive-or operation.
In the third step, the number of the final roots is the same as the power of the error position polynomial, and the difference between the number of the final roots and the power of the error position polynomial is smaller than or equal to a preset value t.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A 1024byte memory system error control module, wherein the error control module is a binary BCH codec comprising: a BCH coding module and a BCH decoding module; the BCH coding module comprises: an encoding arithmetic unit and an encoding control unit; the BCH decoding module comprises: a decoding arithmetic unit and a decoding control unit; according to the decoding principle of the BCH code, the BCH decoding unit further comprises: the syndrome calculation module, the error position polynomial module, the Chien search module and the error correction module; wherein,
the coding control unit and the decoding control unit are the control core of the BCH codec and are responsible for managing and scheduling the normal work of the coding operation unit and the decoding operation unit;
the coding operation unit is used for coding data serving as information bits in the programming process of the Flash page to generate required check bits; when reading Flash, enabling a decoding operation unit by a decoding control unit, and judging whether read data have errors by a syndrome calculation module in the decoding operation unit; if errors are detected, the positions where bit reversal occurs are found through an error position polynomial module and a Chien searching module, and the data bits are turned from 0 to 1 or from 1 to 0 due to the fact that only two conditions exist when the data bits in Flash are in error reversal; thus. And finally, the error correction module can complete error correction only by carrying out negation operation on the searched error position.
2. The 1024-byte memory system error control module of claim 1, wherein the error control module is designed using a binary BCH codec algorithm principle; it uses 1024 bytes data as one time information code element, selects binary finite field GF (2)14) As the domain computation space, polynomial 1+ x is chosen2+x4+x6+x7+x8+x14Adopting 32-bit data parallel processing for the primitive polynomial; the error control module parameter settings are as follows:
。
3. The 1024-byte storage system error control module of claim 2, wherein the encoding arithmetic unit employs 32 bit streams for parallel processing;
the coding operation unit is used for obtaining a check bit r (x) by utilizing an information bit m (x) and a generating polynomial g (x); 8192bit information bits of original data enter the encoding arithmetic unit in parallel and successively by a bit width of 32 bits, each calculation period modulus functional unit calculates the information bits, the result is stored in a register at present, and the information bits of the original data are also used as the output of the current circuit at the same time; and when all the information bits are input, stopping the calculation of the modular division functional unit, and gradually outputting the data in the current register in a 32-bit parallel mode to obtain check bit data.
4. The 1024-byte memory system error control module of claim 3, wherein the decoding operation of the decoding arithmetic unit is performed in four steps:
the first step is the calculation of the syndrome, firstly, a multiply-accumulate operation is carried out through an SC _ FFMA module, and then the domain platform operation result value of the SC _ SEQ module is brought into an SC _ MUL module to carry out finite domain multiply-accumulate operation to obtain the syndrome;
the second step is the calculation of an error position polynomial module which realizes the SiBM algorithm and leads the syndrome SiAs inputs, the error location polynomial module comprises a calculation control module PE _ CTRL and an arithmetic unit PE; the arithmetic unit PE completes the basic arithmetic function of each step, and the calculation control module PE _ CTRL is responsible for state judgment and circuit controlRunning;
the third step is Chien search calculation, wherein a Chien search module takes an error position polynomial as input data, introduces finite field elements one by one, and calculates a polynomial result sigma (alpha)i) Whether or not it is 0 to judge alphaiWhether it is the root of a polynomial; if the number of the final root is the same as the power of the error position polynomial, indicating that the error mode of the data can be corrected, otherwise indicating that the number of the errors exceeds the error correction capability, and failing to correct the errors; in the scheme, σ (α) is first calculatedi) Corresponding mu0,μ1,μ2,…,μtThen each mu is measuredjMultiplying by corresponding alpha0,α1,α2,…,αtThus realizing 32-path parallel processing;
in the last step, the decoded data can be obtained by performing bit inversion on the obtained corresponding data bits at the error positions and using exclusive-or operation.
5. The 1024-byte memory system error control module of claim 1, wherein in the third step, the number of the final roots is equal to the power of the error location polynomial, as indicated by the difference between the number of the final roots and the power of the error location polynomial being equal to or less than a predetermined value t.
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| CN117632577A (en) * | 2023-12-05 | 2024-03-01 | 浙江大学 | Quick ECC error correction circuit based on BCH coding |
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