CN112234058A - A SiC MOSFET device with integrated gate protection structure - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
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- 238000006263 metalation reaction Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 description 10
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
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- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- -1 or TiNiAg Inorganic materials 0.000 description 1
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- 229910001258 titanium gold Inorganic materials 0.000 description 1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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Abstract
本发明涉及半导体技术领域，尤其是涉及一种集成栅保护结构的SiC MOSFET器件，所述SiC MOSFET器件从边缘向中心依次包括划片槽区和终端区、p+主环、在所述p+主环上的栅跑道和源跑道、由多个原胞结构并联组成的有源区以及所述有源区上的源和栅的压块金属；其特征在于，所述栅跑道和所述源跑道之间集成了两个或多个反向串联的多晶硅pn二极管结构，作为器件的栅保护结构。本发明通过在芯片上集成栅保护器件，当器件的栅极电压超过最大允许电压时，栅保护器件发生击穿，使栅源电压钳位在最大允许的电压，保护了MOS栅介质避免承受高的电压。
The invention relates to the technical field of semiconductors, and in particular to a SiC MOSFET device with an integrated gate protection structure. The SiC MOSFET device sequentially includes a scribing groove region and a terminal region, a p+ main ring, and a p+ main ring from the edge to the center. The grid raceway and the source racetrack on the grid, the active region composed of a plurality of primitive cell structures in parallel, and the source and grid briquetting metal on the active region; it is characterized in that the grid raceway and the source racetrack are between Two or more polysilicon pn diode structures connected in reverse series are integrated between them as the gate protection structure of the device. The invention integrates the gate protection device on the chip, when the gate voltage of the device exceeds the maximum allowable voltage, the gate protection device breaks down, so that the gate-source voltage is clamped at the maximum allowable voltage, and the MOS gate dielectric is protected from being subjected to high voltage. voltage.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a SiC MOSFET device integrated with a gate protection structure.
Background
The wide bandgap semiconductor material SiC has a bandgap width of about 3 times, a critical breakdown electric field strength of 10 times, and a thermal conductivity of 3 times as compared with Si. Therefore, compared with a Si device, the SiC device has the advantages of higher voltage resistance, higher working frequency, higher temperature resistance and the like. Both theory and practice have demonstrated that SiC MOSFETs have switching frequencies above 10 and better switching efficiency than Si-based IGBTs, and therefore SiC devices will have a very large field of application and market.
Presence in SiC materialSi and C atoms are formed, so that the thermal oxidation mechanism is more complicated than that of a Si material, and SiC/SiO in the SiC MOS structure2The interface state density of (A) is more than one order of magnitude higher than that of Si MOS. Simultaneously because of SiC and SiO2Band offset ratio of Si to SiO of intermediate conduction band2Even lower, according to Fowler-Nordheim tunneling current formula, the tunneling current increases exponentially, and thus the gate lifetime decreases sharply. In order to obtain a very long device lifetime, the gate-source voltage of the SiC MOSFET, which is used in a much smaller range than the Si device, must be strictly limited in practical applications. This is also a popular approach for the current commercial SiC MOSFET products. However, in practical circuit applications, there are often some current and voltage disturbances, such as sudden on/off of a load, circuit failure, external electromagnetic interference, etc., which may cause voltage fluctuation at the gate, and if the gate voltage fluctuation range exceeds the allowable range of the gate voltage, this may reduce the life and reliability of the gate, and even directly cause the gate dielectric breakdown failure. In order to avoid this phenomenon, the gate protection circuit is usually disposed in the driving circuit in circuit application to protect the gate, which not only increases the cost, but also makes the driving circuit complex and fragile.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a SiC MOSFET device integrated with a gate protection structure, wherein the gate protection device is integrated on a chip, and when the gate voltage of the device exceeds the maximum allowable voltage, the gate protection device is broken down, so that the gate-source voltage is clamped at the maximum allowable voltage, and an MOS gate medium is protected from bearing high voltage.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a SiC MOSFET device integrated with a gate protection structure, which sequentially comprises a scribing groove area, a terminal area, a p + main ring, a gate runway and a source runway on the p + main ring, an active area formed by connecting a plurality of primitive cell structures in parallel and briquetting metal of a source and a gate on the active area from the edge to the center; two or more reverse-series-connected polysilicon pn diode structures are integrated between the gate track and the source track and serve as gate protection structures of devices.
As a further technical scheme, the gate protection structure sequentially comprises a drain electrode, an n + substrate, an n + type buffer layer, an n type drift region, a p + region, a field oxide layer, polycrystalline silicon, an interlayer dielectric, ohmic contact metal, source track metal, gate track metal and a passivation layer from bottom to top.
As a further solution, the polysilicon comprises three portions of different doping, respectively a first highly doped n + type region, an n/p +/n doped region and a second highly doped n + type region, to form two pn diodes with np + and p + n in anti-series.
As a further technical solution, the first highly doped n + type region and the second highly doped n + type region of the polysilicon are respectively connected with the gate track metal and the source track metal in ohmic contact with a low resistance, and the source track metal is also connected with the ohmic contact metal on the p + main ring.
As a further technical scheme, the active region sequentially comprises a drain electrode, an n + substrate, an n + buffer layer, an n-type drift region, an n-type JFET region, a p-well, a p + region, an n + region, a gate dielectric, a polysilicon gate, an interlayer dielectric, a source ohmic contact and a source press metal from bottom to top.
As a further aspect, the electrodes of the source runner are in electrical communication with the source of the active region, and the electrodes of the gate runner are in electrical communication with the gate of the active region.
As a further technical scheme, the gate runway and the source runway are isolated by a passivation layer.
A SiC MOSFET device integrated with a gate protection structure sequentially comprises a scribing groove region, a terminal region, a p + main ring, a gate runway and a source runway on the p + main ring, an active region formed by connecting a plurality of primitive cell structures in parallel, and briquetting metal of a source and a gate on the active region from the edge to the center; the p + main ring and the gate track are also arranged in the middle area of the SiC MOSFET device, and two or more reverse-series polycrystalline silicon pn diode structures are integrated between the gate track and the source pressing block metal and serve as gate protection structures of the device.
By adopting the technical scheme, the invention has the following beneficial effects:
according to the invention, the gate protection device is integrated on the chip, and when the gate voltage of the device exceeds the maximum allowable voltage, the gate protection device is broken down, so that the gate-source voltage is clamped at the maximum allowable voltage, and the MOS gate dielectric is protected from bearing high voltage. Meanwhile, due to the avalanche resistance robustness of the pn junction, the gate protection device is not damaged after breakdown and can continuously work.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic circuit structure diagram of a SiC MOSFET device integrated with a gate protection structure according to an embodiment of the present invention;
FIG. 2 is a graph of intrinsic carrier concentration (ordinate) versus temperature (abscissa) in SiC and Si materials;
fig. 3 is a schematic front side structural diagram of a SiC MOSFET device integrated with a gate protection structure according to an embodiment of the present invention;
fig. 4 is a schematic front side structural diagram of a SiC MOSFET device integrated with a gate protection structure according to a second embodiment of the present invention;
FIG. 5 is a schematic view of the structure of FIG. 3 or FIG. 4 taken along the direction A-A';
icon: 01-terminal and scribe-lane regions, 02-p + main ring, 03-gate racetrack, 04-source racetrack, 05-cell structure, 06-source bulk metal, 07-gate bulk metal, 1-drain, 2-n + substrate, 3-n + buffer layer, 4-n drift region, 5-p + region, 6-field oxide layer, 7-polysilicon, 8-interlayer dielectric, 9-ohmic contact metal, 10-source bulk metal, 11-gate bulk metal, 12-passivation layer, 701-first highly doped n + region 701, 702-n/p +/n doped region, JFET-second highly doped n + region, 21-n type region, 22-p well, 23-p + region, 24-n + region, 25-gate dielectric, 26-polysilicon gate, 27-interlayer dielectric, 28-source ohmic contact and 29-source briquetting metal.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
The gate protection structure can be applied to various SiC transistor dies, such as a planar MOSFET, a groove type MOSFET, an MOSFET integrated with a Schottky diode, an MOSFET integrated with a current sensor, a SiC IGBT, a SiC JFET and the like, and the principle and the method are consistent. The method of the invention can also be used for transistor devices made of other wide bandgap materials, such as GaN and Ga2O3And the like in various semiconductor material devices.
Example one
As shown in fig. 1, fig. 3 and fig. 5, the present embodiment provides a SiC MOSFET device with an integrated gate protection structure, which includes, in order from an edge to a center, a scribe lane region and a termination region 01, a p + main ring 02, a gate track 03 and a source track 04 on the p + main ring 02, an active region formed by connecting a plurality of cell structures 05 in parallel, and a source bulk metal 06 and a gate bulk metal 07 on the active region; two or more reverse series-connected polysilicon pn diode structures are integrated between the gate track 03 and the source track 04 to serve as gate protection structures of devices.
A pair of reverse series-connected polysilicon pn diodes D1 and D2 are connected between the grid source in parallel, and the breakdown voltage of D1 and D2 is designed according to the following scheme that when the forward voltage drop of the grid is larger than the allowed maximum forward voltage drop, D1 breaks down, so that the protection of a grid medium is realized. When the gate reverse voltage drop is larger than the maximum allowed reverse voltage drop, D2 breaks down, and the gate dielectric is protected. Due to the very good avalanche breakdown resistance of the pn diode, the voltage remains substantially constant as the current increases when the pn diode breaks down, thus creating a voltage clamping effect.
Preferably, the integrated polysilicon pn diodes D1 and D2 are each made up of multiple diodes to achieve the designed forward and reverse breakdown voltages.
Likewise, the integrated polysilicon pn diode also has junction temperature protection function. When the SiC MOSFET device passes a very large voltage drop and saturation current due to abnormal causes such as short circuit, power consumption is very large, and junction temperature rapidly rises. Along with the rising of junction temperature, the intrinsic carrier concentration of the semiconductor material rises exponentially and sharply, see the formula:
wherein EGT is the junction temperature, and is the forbidden bandwidth of the semiconductor material. The device fails when the intrinsic carrier concentration approaches the device doping concentration. The higher the forbidden band width, the lower the intrinsic carrier concentration, and therefore the better the high temperature resistance, the higher the allowed junction temperature. Fig. 2 is a graph of intrinsic carrier concentration versus junction temperature for SiC and Si materials. The intrinsic carrier concentration of SiC is about 9 orders of magnitude lower than that of Si at room temperature. The carrier concentration of SiC is much lower than that of Si materials, so SiC devices can withstand much higher junction temperatures than Si devices. Therefore, when the junction temperature rises to a certain temperature, the intrinsic carrier concentration in the integrated polysilicon diode rises sharply to become a conductor firstly, the grid source is short-circuited, the grid voltage drops to be close to zero volt, and the device is turned off, so that the protection of the device is realized.
In this embodiment, as a further technical solution, the gate protection structure sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + type buffer layer 3, an n type drift region 4, a p + region 5, a field oxide layer 6, polysilicon 7, an interlayer dielectric 8, an ohmic contact metal 9, a source track metal 10, a gate track metal 11, and a passivation layer 12.
In this embodiment, as a further solution, the polysilicon 7 includes three portions with different dopings, namely a first highly doped n + type region 701, an n/p +/n doped region 702, and a second highly doped n + type region 703, to form two pn diodes with np + and p + n connected in anti-series. The first highly doped n + type region 701 and the second highly doped n + type region 703 form a low resistance connection of ohmic contact with the gate track metal 11 and the source track metal 10, respectively, and the source track metal 10 is also connected with the ohmic contact metal 9. Thus, the final source also forms an electrical connection with the p + main ring 02. The gate runner metal 11 and the source runner metal 10 are also the two electrodes of the integrated gate protection structure. The n/p +/n doped region 702 is a multi-region differently doped polysilicon, such as an n/p +/n doped structure, which, together with the n + doping at both ends, forms an n +/n/p +/n/n + device structure. Namely the series connection of two diodes of n +/n/p + and p +/n/n +.
In this embodiment, as a further technical solution, the active region sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + buffer layer 3, an n-type drift region 4, an n-type JFET region 21, a p well 22, a p + region 23, an n + region 24, a gate dielectric 25, a polysilicon gate 26, an interlayer dielectric 27, a source ohmic contact 28, and a source briquetting metal 29.
In this embodiment, as a further technical solution, the electrode of the source track 04 is electrically communicated with the source of the active region, and the electrode of the gate track 03 is electrically communicated with the gate of the active region.
In this embodiment, as a further technical solution, the gate track 03 and the source track 04 are isolated by a passivation layer.
Example two
As shown in fig. 1, 4 and 5, the present embodiment provides a SiC MOSFET device with an integrated gate protection structure, which includes, in order from the edge to the center, a scribe line region and a termination region 01, a p + main ring 02, a gate track 03 and a source track 04 on the p + main ring 02, an active region formed by connecting a plurality of cell structures 05 in parallel, and a source bulk metal 06 and a gate bulk metal 07 on the active region; the p + main ring 02 and the gate track 03 also exist in the middle area of the SiC MOSFET device at the same time, so that the non-uniformity of gate voltage among the cells in the SiC MOSFET device is further reduced; two or more reverse series-connected polysilicon pn diode structures are integrated between the gate track 03 and the source briquetting metal 06 as gate protection structures of devices. At this time, a gate protection structure is integrated between the gate track 03 and the source compact metal 06, and the structure is the same as that of the gate protection structure in the first embodiment.
The drain electrode 1 consists of drain electrode ohmic contact and drain electrode pressing metal which is TiNiAg and the like and has large thicknessAt 1 micron. The n + type buffer layer 3 has a doping concentration less than that of the n + substrate, and is typically 1E18cm-3And the thickness is between 0.5 and 5 microns. The doping concentration and thickness of the n-type drift region 4 are determined according to the designed breakdown voltage of the device, for example, for a 1200V device, the concentration can be 5E15-2E16cm-3And a thickness of between 7-15 microns. The width of n-type JFET region 21 depends on the device breakdown voltage, the maximum electric field of the gate dielectric at off, and the on-resistance. The doping concentration is greater than that of the n-type drift region 4, which is beneficial to reducing the on-resistance. p-well 22 bulk doping concentration greater than 1E18cm-3The surface channel region is 1E15-2E17cm-3Depending on the threshold voltage. Bulk doping of p + region 23 greater than 1E18cm-3Surface concentration greater than 1E19cm-3And low-resistance ohmic contact is formed. Doping of n + region 24 is greater than 1E19cm-3. The gate dielectric 25 is typically a thermally oxidized grown SiO2The thickness is between 20nm and 100nm according to the design of threshold voltage. The polysilicon gate 26 is heavily doped low resistivity polysilicon and the interlayer dielectric 27(ILD) is SiO2Or SiN, typically greater than 0.5 microns thick. The source ohmic contact 28 is formed by RTA rapid annealing after Ni deposition and the source block metal 29 may be TiAl, or TiNiAg, or TiAu, etc., with a thickness greater than 1 micron.
The ohmic contact in the integrated gate protection structure is completed together with the ohmic contact in the active region. The p + region 5 is coincident with the p + region 23 of the active region and is completed at the same time, as is the interlayer dielectric 8 and interlayer dielectric 27. The gate track metal is identical to the source track metal and the source metal compact, and the process is completed simultaneously. The polysilicon 7 and the polysilicon gate 26 are deposited simultaneously, and after deposition, different regions are doped differently. Wherein the polysilicon gate 26 is heavily doped low resistance polysilicon. The doping of the polysilicon 7 is divided into several regions, forming two pn diodes in anti-series connection of D1 and D2, wherein the reverse breakdown voltage of the two polysilicon diodes is designed to be the maximum allowable voltage of the MOSFET gate. The first highly doped n + type region 701 and the second highly doped n + type region 703 in the polysilicon 7 are both heavily n + doped and form a low resistance connection of ohmic contacts with the gate runner metal and the source runner metal, respectively. The gate runner metal and the source runner metal are also the two electrodes of the integrated gate protection structure. The n/p +/n doped region 702 is a multi-region differently doped polysilicon, such as an n/p +/n doped structure, which, together with the n + doping at both ends, forms an n +/n/p +/n/n + device structure. Namely the series connection of two diodes of n +/n/p + and p +/n/n +. The doping concentration and width of the n-region polysilicon are determined according to the designed breakdown voltage.
The n-type doping and the p-type doping mentioned in the embodiments of the present invention are relative, and may also be referred to as a first doping and a second doping, i.e., the interchanging of n-type and p-type is also applicable to the device.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
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| CN112802840A (en) * | 2021-04-08 | 2021-05-14 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with over-temperature turn-off function |
| CN115732564A (en) * | 2022-11-30 | 2023-03-03 | 西安理工大学 | SiC MOSFET with gate protection function and preparation method |
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| CN112802840A (en) * | 2021-04-08 | 2021-05-14 | 成都蓉矽半导体有限公司 | Silicon carbide MOSFET with over-temperature turn-off function |
| CN115732564A (en) * | 2022-11-30 | 2023-03-03 | 西安理工大学 | SiC MOSFET with gate protection function and preparation method |
| CN115732564B (en) * | 2022-11-30 | 2023-06-06 | 西安理工大学 | SiC MOSFET with gate protection function and preparation method thereof |
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